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53003 Commits

Author SHA1 Message Date
Tom Stellard 00d80b3a6f llvmpipe: Fix build with LLVM 2.8 
Commit 8d9778589f added all-targets to the
LLVM_COMPONENTS list, but this component does not exist with LLVM 2.8.

Adding all-targets is not necessary for any drivers, and it seems to be
left over from earlier versions of the commit mentioned above.

Tested-by: Stéphane Marchesin <marcheu@chromium.org>
 2012-10-01 17:42:56 -04:00
Tom Stellard 67fcb3c2b4 configure.ac: Use amdgpu component for LLVM 3.2 
The amdgpu component actually does exist.  I must have been using an
older version of llvm-config by accident when I first made this change.
 2012-10-01 21:14:10 +00:00
Tom Stellard f2f17fc348 radeon/llvm: Only initialize the AMDGPU target 2012-10-01 21:14:10 +00:00
Tom Stellard cbd09a9e5c radeon: Fix build with LLVM 3.1 
The build was broken by commit 8d9778589f
 2012-10-01 15:47:31 -04:00
Tom Stellard 8d9778589f radeon: Support LLVM 3.2 
LLVM 3.2 and newer requires that the R600/SI backend be part of the
LLVM tree.
 2012-10-01 15:37:17 +00:00
Tom Stellard 91ee735001 r600g: Re-enable growing of the compute memory pool 2012-10-01 15:37:16 +00:00
Tom Stellard 44b1050e6c r600g: Fix bug when adding new items to the compute memory pool 
The items are ordered in the item list by their offsets, with the lowest
offset coming first in the list.  The old code was assuming that new
items being added to the list would always have a greater offset than
the first item in the list, however this is not always the case.
 2012-10-01 15:37:16 +00:00
Tom Stellard eacca90f43 r600g: Use a RAT buffer as the backing bo for the compute memory pool 2012-10-01 15:37:16 +00:00
Tom Stellard 5cd1c65dc1 r600g: Make sure to init the compute memory pool with enough memory 2012-10-01 15:37:16 +00:00
Tom Stellard 2508d43c36 r600g: Add evergreen_init_color_surface_rat() v2 
This can be used to initialize the CB* registers for buffers without a
radeon_surface.

v2:
  - Get correct group_bytes value from r600_screen
  - Stop setting unnecessary fields

Reviewed-by: Marek Olšák <maraeo@gmail.com>
 2012-10-01 15:37:16 +00:00
Tom Stellard d13c3b19f9 r600g: Add register field definitions for 028C70_RESOURCE_TYPE 
Reviewed-by: Marek Olšák <maraeo@gmail.com>
 2012-10-01 15:37:16 +00:00
Oliver McFadden 9545d9611f intel: add support for ANGLE_texture_compression_dxt. 
Signed-off-by: Oliver McFadden <oliver.mcfadden@linux.intel.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-10-01 17:21:51 +03:00
Alex Deucher 304beb81bb radeonsi: emit PA_SU_PRIM_FILTER_CNTL 
has no default value.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <deathsimple@vodafone.de>
 2012-10-01 10:29:51 +02:00
Alex Deucher 7d76767f21 radeonsi: remove some old r600g cruft 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <deathsimple@vodafone.de>
 2012-10-01 10:29:50 +02:00
Alex Deucher 918e302a19 radeonsi: fix range checking for state regs 
end value is exclusive, but in practice we shouldn't
hit this.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
 2012-10-01 10:29:50 +02:00
Alex Deucher f1a3de5e9d radeonsi: drop some cayman remnants 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <deathsimple@vodafone.de>
 2012-10-01 10:29:50 +02:00
Christian König 22ae062fa1 radeonsi: define SGPR register numbers 
Instead of hardcoding them.

Signed-off-by: Christian König <deathsimple@vodafone.de>
 2012-10-01 10:29:50 +02:00
Christoph Bumiller c321b1bef1 nvc0: make sure handles for unbound textures/samplers are uploaded on nve4 2012-09-30 23:09:37 +02:00
Christoph Bumiller 2149ce41ed nv50,nvc0: fix 3d engine blit for nvc0 2012-09-30 23:09:29 +02:00
Christoph Bumiller 36ea744f58 nv50,nvc0: implement blit 2012-09-30 21:31:45 +02:00
Marek Olšák de80660c2b gallium: remove resource_resolve 
The functionality is provided by the new blit function.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:57 +02:00
Marek Olšák d37e6b15ad st/mesa: implement decompress_with_blit using gallium blit 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:57 +02:00
Marek Olšák d1b929a137 st/mesa: implement BlitFramebuffer using gallium blit 
This also fixes a lot tests, especially all the clip-and-scissor-blit MSAA
piglit tests.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:57 +02:00
Marek Olšák ad3d5dbcc5 svga: implement blit 
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:57 +02:00
Marek Olšák 3d9d4b1ce6 softpipe: implement blit 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:57 +02:00
Marek Olšák 5f3054dcc4 radeonsi: implement blit 
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:57 +02:00
Marek Olšák fc887d687b r600g: implement blit 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:57 +02:00
Marek Olšák 95b777e688 r300g: implement blit 
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák ced065a079 nv30: implement blit 
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák db85443922 nv30: use util_format_is_supported 
Hardware drivers *must* use it.

Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák ff2d192ec5 llvmpipe: implement blit 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák 6d2f59ce54 i915g: implement blit 
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák 2a309dc2b4 gallium: implement blit in driver wrappers 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák ab3070c5fa gallium: add helpers for dumping pipe_box and pipe_blit_info 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák cecfb452ab gallium/u_blitter: add helper for blitting via resource_copy_region 
v2: fix off-by-one error in is_box_inside_resource, add comments

Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák 0b0697e80d gallium/u_blitter: add gallium blit implementation 
The original blit function is extended and the otAher functions reuse it.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák 84d2f2295e gallium/u_blitter: add ability to disable and restore the render condition 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák 59dfe0af60 gallium/u_blitter: facilitate co-existence with the Draw module 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák 9cc257ad40 gallium/u_blitter: check PIPE_CAP_TEXTURE_MULTISAMPLE 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák c4df2e3337 gallium: add blit into the interface 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák b9c9dd4783 gallium: add PIPE_CAP_TEXTURE_MULTISAMPLE 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Marek Olšák c15dbd7ef2 softpipe: fix set_framebuffer_state with uninitialized surfaces past nr_cbufs-1 
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-30 18:57:56 +02:00
Vinson Lee 0615e8324c scons: Use full path of texture_builtins.py. 
Fixes this build error on Cygwin.
Explicit dependency `src/glsl/builtins/tools/texture_builtins.py' not
found, needed by target
`build/cygwin-x86-debug/glsl/builtin_function.cpp'.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
 2012-09-29 14:38:37 -07:00
Brian Paul 46328296bd mesa: add fall-through comment, just to be clear 2012-09-29 08:53:59 -06:00
Brian Paul bd81ebf085 mesa: remove useless GLenum casts 2012-09-29 08:53:59 -06:00
Brian Paul e77fc1279a mesa: add const qualifier in check_for_ending() to silence warning 2012-09-29 08:24:44 -06:00
Kenneth Graunke 225276c696 i965: Complain about variable index lowering when INTEL_DEBUG=perf. 
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
 2012-09-29 00:36:56 -07:00
Kenneth Graunke 33dbac78a8 i965: Dump linked shaders on MESA_GLSL=dump. 
Often, the original shader IR isn't terribly interesting because a lot
of crucial optimizations haven't been done (such as inlining built-ins).

ir_to_mesa used to print this out for us, but since we don't use it, we
have to do it ourselves.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
 2012-09-29 00:36:45 -07:00
Kenneth Graunke 5cadb3ef7e glsl: Rename variable_entry2 back to variable_entry in struct splitting. 
The anonymous namespace should keep these private classes to file scope,
preventing clashes with other symbols of the same name elsewhere.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
 2012-09-29 00:36:01 -07:00
Anuj Phogat ea0d088727 intel/i965: Disable SampleAlphaToOne if dual source blending enabled 
From SandyBridge PRM, volume 2 Part 1, section 12.2.3, BLEND_STATE:
DWord 1, Bit 30 (AlphaToOne Enable):
"If Dual Source Blending is enabled, this bit must be disabled"

Note: This is a candidate for stable branches.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
 2012-09-29 00:10:09 -07:00