2010-10-10 23:42:37 +01:00
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/*
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* Copyright © 2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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2017-03-20 16:04:38 +00:00
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#ifndef BRW_FS_H
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#define BRW_FS_H
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2012-04-10 20:01:50 +01:00
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2011-05-03 18:55:50 +01:00
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#include "brw_shader.h"
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2015-02-05 23:11:18 +00:00
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#include "brw_ir_fs.h"
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2015-06-03 17:59:44 +01:00
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#include "brw_fs_builder.h"
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2016-01-18 10:54:03 +00:00
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#include "compiler/nir/nir.h"
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2010-10-10 23:42:37 +01:00
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2014-06-15 06:53:40 +01:00
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struct bblock_t;
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2012-06-06 18:57:54 +01:00
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namespace {
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2013-01-08 03:42:38 +00:00
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struct acp_entry;
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2012-06-06 18:57:54 +01:00
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}
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2012-05-11 00:10:15 +01:00
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2012-06-05 19:37:22 +01:00
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namespace brw {
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class fs_live_variables;
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}
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2015-06-30 06:50:28 +01:00
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struct brw_gs_compile;
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2015-06-25 18:55:51 +01:00
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static inline fs_reg
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2016-05-27 07:09:46 +01:00
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offset(const fs_reg ®, const brw::fs_builder &bld, unsigned delta)
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2015-06-25 18:55:51 +01:00
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{
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2016-05-27 07:09:46 +01:00
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return offset(reg, bld.dispatch_width(), delta);
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2015-06-25 18:55:51 +01:00
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}
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2016-11-29 13:20:20 +00:00
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#define UBO_START ((1 << 16) - 4)
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2012-11-09 09:05:47 +00:00
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/**
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* The fragment shader front-end.
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*
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* Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
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*/
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2015-05-20 18:35:34 +01:00
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class fs_visitor : public backend_shader
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2010-10-10 23:42:37 +01:00
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{
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public:
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2015-06-23 01:17:56 +01:00
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fs_visitor(const struct brw_compiler *compiler, void *log_data,
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2014-05-14 09:21:02 +01:00
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void *mem_ctx,
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2015-03-12 05:41:49 +00:00
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const void *key,
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struct brw_stage_prog_data *prog_data,
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struct gl_program *prog,
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2015-10-06 03:26:02 +01:00
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const nir_shader *shader,
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2015-06-19 23:40:09 +01:00
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unsigned dispatch_width,
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2015-11-10 22:35:27 +00:00
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int shader_time_index,
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const struct brw_vue_map *input_vue_map = NULL);
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2015-06-30 06:50:28 +01:00
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fs_visitor(const struct brw_compiler *compiler, void *log_data,
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void *mem_ctx,
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struct brw_gs_compile *gs_compile,
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struct brw_gs_prog_data *prog_data,
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2015-11-03 20:51:32 +00:00
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const nir_shader *shader,
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int shader_time_index);
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2015-06-30 06:50:28 +01:00
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void init();
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2012-07-04 21:12:50 +01:00
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~fs_visitor();
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2010-10-10 23:42:37 +01:00
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2014-05-16 10:21:51 +01:00
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fs_reg vgrf(const glsl_type *const type);
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2011-07-26 02:13:04 +01:00
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void import_uniforms(fs_visitor *v);
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2017-09-29 00:25:31 +01:00
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void setup_uniform_clipplane_values();
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void compute_clip_distance();
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2010-10-10 23:42:37 +01:00
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2015-06-03 20:22:39 +01:00
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void VARYING_PULL_CONSTANT_LOAD(const brw::fs_builder &bld,
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const fs_reg &dst,
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const fs_reg &surf_index,
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const fs_reg &varying_offset,
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uint32_t const_offset);
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2015-06-03 20:22:10 +01:00
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void DEP_RESOLVE_MOV(const brw::fs_builder &bld, int grf);
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2012-11-09 00:06:24 +00:00
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2016-05-16 22:30:25 +01:00
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bool run_fs(bool allow_spilling, bool do_rep_send);
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2017-09-29 00:25:31 +01:00
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bool run_vs();
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2015-11-15 01:40:43 +00:00
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bool run_tcs_single_patch();
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2015-11-10 22:35:27 +00:00
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bool run_tes();
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2015-03-12 06:14:31 +00:00
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bool run_gs();
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2017-08-22 03:16:45 +01:00
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bool run_cs(unsigned min_dispatch_width);
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2014-11-14 00:28:18 +00:00
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void optimize();
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2017-08-22 03:16:45 +01:00
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void allocate_registers(unsigned min_dispatch_width, bool allow_spilling);
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2016-02-11 05:20:01 +00:00
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void setup_fs_payload_gen4();
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void setup_fs_payload_gen6();
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2014-10-28 05:42:50 +00:00
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void setup_vs_payload();
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2015-03-12 06:14:31 +00:00
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void setup_gs_payload();
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2014-08-31 03:57:39 +01:00
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void setup_cs_payload();
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2014-12-30 04:33:12 +00:00
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void fixup_3src_null_dest();
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2010-10-10 23:42:37 +01:00
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void assign_curb_setup();
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void calculate_urb_setup();
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void assign_urb_setup();
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2015-03-12 06:14:31 +00:00
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void convert_attr_sources_to_hw_regs(fs_inst *inst);
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2014-10-28 05:42:50 +00:00
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void assign_vs_urb_setup();
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2015-11-15 01:40:43 +00:00
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void assign_tcs_single_patch_urb_setup();
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2015-11-10 22:35:27 +00:00
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void assign_tes_urb_setup();
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2015-03-12 06:14:31 +00:00
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void assign_gs_urb_setup();
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2016-05-16 22:30:25 +01:00
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bool assign_regs(bool allow_spilling, bool spill_all);
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2010-10-10 23:42:37 +01:00
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void assign_regs_trivial();
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2015-06-12 20:01:35 +01:00
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void calculate_payload_ranges(int payload_node_count,
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int *payload_last_use_ip);
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2012-10-02 23:01:24 +01:00
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void setup_payload_interference(struct ra_graph *g, int payload_reg_count,
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int first_payload_node);
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2010-10-19 17:25:51 +01:00
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int choose_spill_reg(struct ra_graph *g);
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2018-12-10 22:49:49 +00:00
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void spill_reg(unsigned spill_reg);
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2010-10-14 04:17:15 +01:00
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void split_virtual_grfs();
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2014-09-16 21:14:09 +01:00
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bool compact_virtual_grfs();
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2014-03-11 21:35:27 +00:00
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void assign_constant_locations();
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2017-06-02 17:54:31 +01:00
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bool get_pull_locs(const fs_reg &src, unsigned *out_surf_index,
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unsigned *out_pull_index);
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2015-12-09 01:14:49 +00:00
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void lower_constant_loads();
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2014-09-01 18:54:00 +01:00
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void invalidate_live_intervals();
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2014-07-12 04:54:52 +01:00
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void calculate_live_intervals();
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2013-08-05 07:27:14 +01:00
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void calculate_register_pressure();
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2015-07-02 23:41:02 +01:00
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void validate();
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2011-07-23 00:45:15 +01:00
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bool opt_algebraic();
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2014-07-06 06:10:41 +01:00
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bool opt_redundant_discard_jumps();
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2012-05-11 00:10:15 +01:00
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bool opt_cse();
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2014-07-12 04:35:31 +01:00
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bool opt_cse_local(bblock_t *block);
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2016-11-28 18:45:08 +00:00
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bool opt_copy_propagation();
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2012-06-06 18:57:54 +01:00
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bool try_copy_propagate(fs_inst *inst, int arg, acp_entry *entry);
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2014-09-24 01:22:09 +01:00
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bool try_constant_propagate(fs_inst *inst, acp_entry *entry);
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2016-11-28 18:45:08 +00:00
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bool opt_copy_propagation_local(void *mem_ctx, bblock_t *block,
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exec_list *acp);
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2016-04-20 22:22:53 +01:00
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bool opt_drop_redundant_mov_to_flags();
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2014-04-14 23:01:37 +01:00
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bool opt_register_renaming();
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2017-06-15 23:23:57 +01:00
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bool opt_bank_conflicts();
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2017-12-06 19:42:54 +00:00
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unsigned bank_conflict_cycles(const fs_inst *inst) const;
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2013-11-30 06:16:14 +00:00
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bool register_coalesce();
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2010-10-08 22:00:14 +01:00
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bool compute_to_mrf();
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2015-02-20 18:25:04 +00:00
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bool eliminate_find_live_channel();
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2010-10-10 23:42:37 +01:00
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bool dead_code_eliminate();
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2010-11-19 07:57:05 +00:00
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bool remove_duplicate_mrf_writes();
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2017-07-01 07:14:56 +01:00
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bool remove_extra_rounding_modes();
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2015-02-08 21:59:57 +00:00
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bool opt_sampler_eot();
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2010-10-10 23:42:37 +01:00
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bool virtual_grf_interferes(int a, int b);
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2013-11-07 01:38:23 +00:00
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void schedule_instructions(instruction_scheduler_mode mode);
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2013-02-05 23:46:22 +00:00
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void insert_gen4_send_dependency_workarounds();
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2014-08-25 03:07:01 +01:00
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void insert_gen4_pre_send_dependency_workarounds(bblock_t *block,
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fs_inst *inst);
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void insert_gen4_post_send_dependency_workarounds(bblock_t *block,
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fs_inst *inst);
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i965: Accurately bail on SIMD16 compiles.
Ideally, we'd like to never even attempt the SIMD16 compile if we could
know ahead of time that it won't succeed---it's purely a waste of time.
This is especially important for state-based recompiles, which happen at
draw time.
The fragment shader compiler has a number of checks like:
if (dispatch_width == 16)
fail("...some reason...");
This patch introduces a new no16() function which replaces the above
pattern. In the SIMD8 compile, it sets a "SIMD16 will never work" flag.
Then, brw_wm_fs_emit can check that flag, skip the SIMD16 compile, and
issue a helpful performance warning if INTEL_DEBUG=perf is set. (In
SIMD16 mode, no16() calls fail(), for safety's sake.)
The great part is that this is not a heuristic---if the flag is set, we
know with 100% certainty that the SIMD16 compile would fail. (It might
fail anyway if we run out of registers, but it's always worth trying.)
v2: Fix missing va_end in early-return case (caught by Ilia Mirkin).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz> [v1]
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> [v1]
Reviewed-by: Eric Anholt <eric@anholt.net>
2014-03-07 08:49:45 +00:00
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void vfail(const char *msg, va_list args);
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2011-03-13 20:43:05 +00:00
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void fail(const char *msg, ...);
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2016-05-18 22:39:52 +01:00
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void limit_dispatch_width(unsigned n, const char *msg);
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2013-02-16 03:26:48 +00:00
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void lower_uniform_pull_constant_loads();
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2014-04-18 19:56:46 +01:00
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bool lower_load_payload();
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2016-05-05 10:45:19 +01:00
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bool lower_pack();
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2018-12-29 12:00:13 +00:00
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bool lower_regioning();
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2015-07-13 15:44:58 +01:00
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bool lower_logical_sends();
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2015-05-11 17:29:56 +01:00
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bool lower_integer_multiplication();
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2016-02-11 20:27:02 +00:00
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bool lower_minmax();
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2015-07-13 19:15:31 +01:00
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bool lower_simd_width();
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2014-02-12 19:00:46 +00:00
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bool opt_combine_constants();
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2011-01-19 01:16:49 +00:00
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2010-10-10 23:42:37 +01:00
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void emit_dummy_fs();
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2014-09-26 22:47:03 +01:00
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void emit_repclear_shader();
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2016-07-15 00:52:10 +01:00
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void emit_fragcoord_interpolation(fs_reg wpos);
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2014-08-05 18:29:00 +01:00
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fs_reg *emit_frontfacing_interpolation();
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2014-08-05 19:10:07 +01:00
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fs_reg *emit_samplepos_setup();
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2014-10-17 20:59:18 +01:00
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fs_reg *emit_sampleid_setup();
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i965: Fix gl_SampleMaskIn[] in per-sample shading mode.
The coverage mask is not sufficient - in per-sample mode, we also need
to AND with a mask representing the samples being processed by the
current fragment shader invocation.
Fixes 18 dEQP-GLES31.functional.shaders.sample_variables tests:
sample_mask_in.bit_count_per_sample.multisample_{rbo,texture}_{1,2,4,8}
sample_mask_in.bit_count_per_two_samples.multisample_{rbo,texture}_{4,8}
sample_mask_in.bits_unique_per_sample.multisample_{rbo,texture}_{1,2,4,8}
sample_mask_in.bits_unique_per_two_samples.multisample_{rbo,texture}_{4,8}
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2016-04-06 04:14:22 +01:00
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fs_reg *emit_samplemaskin_setup();
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2010-10-10 23:42:37 +01:00
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void emit_interpolation_setup_gen4();
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void emit_interpolation_setup_gen6();
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2013-10-24 23:53:05 +01:00
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void compute_sample_position(fs_reg dst, fs_reg int_sample_pos);
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2015-07-17 16:23:31 +01:00
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fs_reg emit_mcs_fetch(const fs_reg &coordinate, unsigned components,
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const fs_reg &sampler);
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2014-02-03 09:15:16 +00:00
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void emit_gen6_gather_wa(uint8_t wa, fs_reg dst);
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2015-08-10 19:52:50 +01:00
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fs_reg resolve_source_modifiers(const fs_reg &src);
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2015-03-05 23:48:39 +00:00
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void emit_discard_jump();
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2013-10-23 01:51:28 +01:00
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bool opt_peephole_sel();
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2018-02-22 02:06:56 +00:00
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bool opt_peephole_csel();
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2013-10-23 01:51:28 +01:00
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bool opt_peephole_predicated_break();
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2013-12-12 08:30:16 +00:00
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bool opt_saturate_propagation();
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2014-08-22 18:54:43 +01:00
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bool opt_cmod_propagation();
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2015-04-24 00:56:53 +01:00
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bool opt_zero_samples();
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2010-10-08 22:35:34 +01:00
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2014-08-15 18:32:07 +01:00
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void emit_nir_code();
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2015-10-01 20:23:53 +01:00
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void nir_setup_outputs();
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void nir_setup_uniforms();
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void nir_emit_system_values();
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2014-08-15 18:32:07 +01:00
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void nir_emit_impl(nir_function_impl *impl);
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void nir_emit_cf_list(exec_list *list);
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void nir_emit_if(nir_if *if_stmt);
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void nir_emit_loop(nir_loop *loop);
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void nir_emit_block(nir_block *block);
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void nir_emit_instr(nir_instr *instr);
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2015-06-03 18:59:26 +01:00
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void nir_emit_alu(const brw::fs_builder &bld, nir_alu_instr *instr);
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2015-06-26 00:22:26 +01:00
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void nir_emit_load_const(const brw::fs_builder &bld,
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nir_load_const_instr *instr);
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2015-11-05 07:05:07 +00:00
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void nir_emit_vs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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2015-11-15 01:40:43 +00:00
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void nir_emit_tcs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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2015-11-05 07:05:07 +00:00
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void nir_emit_gs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_fs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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void nir_emit_cs_intrinsic(const brw::fs_builder &bld,
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nir_intrinsic_instr *instr);
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2018-08-16 22:23:10 +01:00
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fs_reg get_nir_image_intrinsic_image(const brw::fs_builder &bld,
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|
|
nir_intrinsic_instr *instr);
|
2018-10-20 16:05:33 +01:00
|
|
|
fs_reg get_nir_ssbo_intrinsic_index(const brw::fs_builder &bld,
|
|
|
|
nir_intrinsic_instr *instr);
|
2015-06-03 19:01:32 +01:00
|
|
|
void nir_emit_intrinsic(const brw::fs_builder &bld,
|
|
|
|
nir_intrinsic_instr *instr);
|
2015-11-10 22:35:27 +00:00
|
|
|
void nir_emit_tes_intrinsic(const brw::fs_builder &bld,
|
|
|
|
nir_intrinsic_instr *instr);
|
2015-06-01 08:41:47 +01:00
|
|
|
void nir_emit_ssbo_atomic(const brw::fs_builder &bld,
|
|
|
|
int op, nir_intrinsic_instr *instr);
|
2018-04-18 22:02:33 +01:00
|
|
|
void nir_emit_ssbo_atomic_float(const brw::fs_builder &bld,
|
|
|
|
int op, nir_intrinsic_instr *instr);
|
2015-10-10 21:01:03 +01:00
|
|
|
void nir_emit_shared_atomic(const brw::fs_builder &bld,
|
|
|
|
int op, nir_intrinsic_instr *instr);
|
2018-04-18 22:02:33 +01:00
|
|
|
void nir_emit_shared_atomic_float(const brw::fs_builder &bld,
|
|
|
|
int op, nir_intrinsic_instr *instr);
|
2015-06-03 19:02:57 +01:00
|
|
|
void nir_emit_texture(const brw::fs_builder &bld,
|
|
|
|
nir_tex_instr *instr);
|
2015-06-03 18:57:12 +01:00
|
|
|
void nir_emit_jump(const brw::fs_builder &bld,
|
|
|
|
nir_jump_instr *instr);
|
2016-05-19 22:43:23 +01:00
|
|
|
fs_reg get_nir_src(const nir_src &src);
|
|
|
|
fs_reg get_nir_src_imm(const nir_src &src);
|
|
|
|
fs_reg get_nir_dest(const nir_dest &dest);
|
2015-11-10 22:35:27 +00:00
|
|
|
fs_reg get_indirect_offset(nir_intrinsic_instr *instr);
|
2015-06-03 19:12:49 +01:00
|
|
|
void emit_percomp(const brw::fs_builder &bld, const fs_inst &inst,
|
|
|
|
unsigned wr_mask);
|
2014-08-15 18:32:07 +01:00
|
|
|
|
2016-01-21 17:10:09 +00:00
|
|
|
bool optimize_extract_to_float(nir_alu_instr *instr,
|
|
|
|
const fs_reg &result);
|
2015-02-15 21:45:04 +00:00
|
|
|
bool optimize_frontfacing_ternary(nir_alu_instr *instr,
|
|
|
|
const fs_reg &result);
|
|
|
|
|
2013-10-27 00:32:03 +01:00
|
|
|
void emit_alpha_test();
|
2015-06-03 19:07:52 +01:00
|
|
|
fs_inst *emit_single_fb_write(const brw::fs_builder &bld,
|
|
|
|
fs_reg color1, fs_reg color2,
|
2015-07-16 14:12:48 +01:00
|
|
|
fs_reg src0_alpha, unsigned components);
|
2010-10-10 23:42:37 +01:00
|
|
|
void emit_fb_writes();
|
2016-07-22 04:25:28 +01:00
|
|
|
fs_inst *emit_non_coherent_fb_read(const brw::fs_builder &bld,
|
|
|
|
const fs_reg &dst, unsigned target);
|
2015-03-12 06:14:31 +00:00
|
|
|
void emit_urb_writes(const fs_reg &gs_vertex_count = fs_reg());
|
|
|
|
void set_gs_stream_control_data_bits(const fs_reg &vertex_count,
|
|
|
|
unsigned stream_id);
|
|
|
|
void emit_gs_control_data_bits(const fs_reg &vertex_count);
|
|
|
|
void emit_gs_end_primitive(const nir_src &vertex_count_nir_src);
|
|
|
|
void emit_gs_vertex(const nir_src &vertex_count_nir_src,
|
|
|
|
unsigned stream_id);
|
|
|
|
void emit_gs_thread_end();
|
|
|
|
void emit_gs_input_load(const fs_reg &dst, const nir_src &vertex_src,
|
2015-11-25 22:14:05 +00:00
|
|
|
unsigned base_offset, const nir_src &offset_src,
|
2016-05-19 06:58:51 +01:00
|
|
|
unsigned num_components, unsigned first_component);
|
2015-04-12 10:06:57 +01:00
|
|
|
void emit_cs_terminate();
|
2014-10-10 16:28:24 +01:00
|
|
|
fs_reg *emit_cs_work_group_id_setup();
|
2012-11-27 22:10:52 +00:00
|
|
|
|
2014-08-27 19:32:08 +01:00
|
|
|
void emit_barrier();
|
|
|
|
|
2012-11-27 22:10:52 +00:00
|
|
|
void emit_shader_time_begin();
|
|
|
|
void emit_shader_time_end();
|
2015-06-03 18:43:09 +01:00
|
|
|
void SHADER_TIME_ADD(const brw::fs_builder &bld,
|
2015-06-19 23:40:09 +01:00
|
|
|
int shader_time_subindex,
|
2015-06-19 22:46:03 +01:00
|
|
|
fs_reg value);
|
2012-11-27 22:10:52 +00:00
|
|
|
|
2015-06-03 18:43:09 +01:00
|
|
|
fs_reg get_timestamp(const brw::fs_builder &bld);
|
2012-11-27 22:10:52 +00:00
|
|
|
|
2016-04-26 02:33:22 +01:00
|
|
|
fs_reg interp_reg(int location, int channel);
|
2015-06-28 19:04:17 +01:00
|
|
|
|
2017-12-12 04:24:53 +00:00
|
|
|
int implied_mrf_writes(fs_inst *inst) const;
|
2010-10-10 23:42:37 +01:00
|
|
|
|
2013-08-05 07:34:01 +01:00
|
|
|
virtual void dump_instructions();
|
2014-05-29 21:08:59 +01:00
|
|
|
virtual void dump_instructions(const char *name);
|
2013-04-29 22:21:14 +01:00
|
|
|
void dump_instruction(backend_instruction *inst);
|
2014-05-29 19:45:15 +01:00
|
|
|
void dump_instruction(backend_instruction *inst, FILE *file);
|
2012-10-30 22:35:44 +00:00
|
|
|
|
2014-08-29 20:50:46 +01:00
|
|
|
const void *const key;
|
2015-03-09 08:58:51 +00:00
|
|
|
const struct brw_sampler_prog_key_data *key_tex;
|
|
|
|
|
2015-06-30 06:50:28 +01:00
|
|
|
struct brw_gs_compile *gs_compile;
|
|
|
|
|
2014-08-29 20:50:46 +01:00
|
|
|
struct brw_stage_prog_data *prog_data;
|
2015-10-01 23:21:57 +01:00
|
|
|
struct gl_program *prog;
|
2010-10-10 23:42:37 +01:00
|
|
|
|
2015-11-10 22:35:27 +00:00
|
|
|
const struct brw_vue_map *input_vue_map;
|
|
|
|
|
2013-04-30 23:00:40 +01:00
|
|
|
int *virtual_grf_start;
|
|
|
|
int *virtual_grf_end;
|
2012-06-05 19:37:22 +01:00
|
|
|
brw::fs_live_variables *live_intervals;
|
2010-10-10 23:42:37 +01:00
|
|
|
|
2013-08-05 07:27:14 +01:00
|
|
|
int *regs_live_at_ip;
|
|
|
|
|
2014-02-19 14:27:01 +00:00
|
|
|
/** Number of uniform variable components visited. */
|
|
|
|
unsigned uniforms;
|
|
|
|
|
2014-05-14 05:00:35 +01:00
|
|
|
/** Byte-offset for the next available spot in the scratch space buffer. */
|
|
|
|
unsigned last_scratch;
|
|
|
|
|
2014-03-07 10:10:14 +00:00
|
|
|
/**
|
|
|
|
* Array mapping UNIFORM register numbers to the pull parameter index,
|
|
|
|
* or -1 if this uniform register isn't being uploaded as a pull constant.
|
|
|
|
*/
|
|
|
|
int *pull_constant_loc;
|
|
|
|
|
2014-03-11 21:35:27 +00:00
|
|
|
/**
|
|
|
|
* Array mapping UNIFORM register numbers to the push parameter index,
|
|
|
|
* or -1 if this uniform register isn't being uploaded as a push constant.
|
2011-07-26 02:13:04 +01:00
|
|
|
*/
|
2014-03-11 21:35:27 +00:00
|
|
|
int *push_constant_loc;
|
2011-07-26 02:13:04 +01:00
|
|
|
|
2017-08-24 19:40:31 +01:00
|
|
|
fs_reg subgroup_id;
|
2012-09-18 17:12:48 +01:00
|
|
|
fs_reg frag_depth;
|
2015-10-20 22:29:39 +01:00
|
|
|
fs_reg frag_stencil;
|
2013-10-25 00:21:13 +01:00
|
|
|
fs_reg sample_mask;
|
2014-10-28 05:42:50 +00:00
|
|
|
fs_reg outputs[VARYING_SLOT_MAX];
|
2012-04-25 21:58:07 +01:00
|
|
|
fs_reg dual_src_output;
|
2010-10-10 23:42:37 +01:00
|
|
|
int first_non_payload_grf;
|
2012-10-02 00:39:54 +01:00
|
|
|
/** Either BRW_MAX_GRF or GEN7_MRF_HACK_START */
|
2015-02-10 13:51:34 +00:00
|
|
|
unsigned max_grf;
|
2010-10-10 23:42:37 +01:00
|
|
|
|
2014-11-12 19:05:51 +00:00
|
|
|
fs_reg *nir_locals;
|
2015-06-24 20:28:47 +01:00
|
|
|
fs_reg *nir_ssa_values;
|
2014-12-17 20:34:27 +00:00
|
|
|
fs_reg *nir_system_values;
|
2014-08-15 18:32:07 +01:00
|
|
|
|
2011-03-13 20:43:05 +00:00
|
|
|
bool failed;
|
2011-05-16 23:10:26 +01:00
|
|
|
char *fail_msg;
|
2010-10-10 23:42:37 +01:00
|
|
|
|
2014-05-14 05:52:51 +01:00
|
|
|
/** Register numbers for thread payload fields. */
|
2015-07-27 14:14:36 +01:00
|
|
|
struct thread_payload {
|
2017-01-13 23:36:51 +00:00
|
|
|
uint8_t subspan_coord_reg[2];
|
|
|
|
uint8_t source_depth_reg[2];
|
|
|
|
uint8_t source_w_reg[2];
|
|
|
|
uint8_t aa_dest_stencil_reg[2];
|
|
|
|
uint8_t dest_depth_reg[2];
|
|
|
|
uint8_t sample_pos_reg[2];
|
|
|
|
uint8_t sample_mask_in_reg[2];
|
|
|
|
uint8_t barycentric_coord_reg[BRW_BARYCENTRIC_MODE_COUNT][2];
|
|
|
|
uint8_t local_invocation_id_reg[2];
|
2014-05-14 05:52:51 +01:00
|
|
|
|
|
|
|
/** The number of thread payload registers the hardware will supply. */
|
|
|
|
uint8_t num_regs;
|
|
|
|
} payload;
|
|
|
|
|
2014-05-14 08:08:58 +01:00
|
|
|
bool source_depth_to_render_target;
|
|
|
|
bool runtime_check_aads_emit;
|
|
|
|
|
2010-10-10 23:42:37 +01:00
|
|
|
fs_reg pixel_x;
|
|
|
|
fs_reg pixel_y;
|
|
|
|
fs_reg wpos_w;
|
|
|
|
fs_reg pixel_w;
|
2016-07-12 00:24:12 +01:00
|
|
|
fs_reg delta_xy[BRW_BARYCENTRIC_MODE_COUNT];
|
2012-11-27 22:10:52 +00:00
|
|
|
fs_reg shader_start_time;
|
2014-10-28 05:42:50 +00:00
|
|
|
fs_reg userplane[MAX_CLIP_PLANES];
|
2015-03-12 06:14:31 +00:00
|
|
|
fs_reg final_gs_vertex_count;
|
|
|
|
fs_reg control_data_bits;
|
2015-11-15 01:40:43 +00:00
|
|
|
fs_reg invocation_id;
|
2010-10-10 23:42:37 +01:00
|
|
|
|
2015-02-10 13:51:34 +00:00
|
|
|
unsigned grf_used;
|
2013-10-29 19:46:18 +00:00
|
|
|
bool spilled_any_registers;
|
2011-03-12 03:19:01 +00:00
|
|
|
|
2016-05-18 22:39:52 +01:00
|
|
|
const unsigned dispatch_width; /**< 8, 16 or 32 */
|
|
|
|
unsigned max_dispatch_width;
|
2015-03-16 19:18:31 +00:00
|
|
|
|
2015-06-19 23:40:09 +01:00
|
|
|
int shader_time_index;
|
|
|
|
|
2015-03-16 19:18:31 +00:00
|
|
|
unsigned promoted_constants;
|
2015-06-03 17:59:44 +01:00
|
|
|
brw::fs_builder bld;
|
2010-10-10 23:42:37 +01:00
|
|
|
};
|
|
|
|
|
2012-11-09 09:05:47 +00:00
|
|
|
/**
|
|
|
|
* The fragment shader code generator.
|
|
|
|
*
|
|
|
|
* Translates FS IR to actual i965 assembly code.
|
|
|
|
*/
|
|
|
|
class fs_generator
|
|
|
|
{
|
|
|
|
public:
|
2015-04-16 22:34:04 +01:00
|
|
|
fs_generator(const struct brw_compiler *compiler, void *log_data,
|
2014-05-14 09:21:02 +01:00
|
|
|
void *mem_ctx,
|
2014-10-21 06:53:31 +01:00
|
|
|
struct brw_stage_prog_data *prog_data,
|
2015-03-16 19:18:31 +00:00
|
|
|
unsigned promoted_constants,
|
2015-01-13 22:28:13 +00:00
|
|
|
bool runtime_check_aads_emit,
|
2016-01-15 04:27:51 +00:00
|
|
|
gl_shader_stage stage);
|
2012-11-09 09:05:47 +00:00
|
|
|
~fs_generator();
|
|
|
|
|
2014-10-28 02:40:47 +00:00
|
|
|
void enable_debug(const char *shader_name);
|
2014-11-14 00:28:08 +00:00
|
|
|
int generate_code(const cfg_t *cfg, int dispatch_width);
|
2018-02-27 00:34:55 +00:00
|
|
|
const unsigned *get_assembly();
|
2012-11-09 09:05:47 +00:00
|
|
|
|
|
|
|
private:
|
2014-06-05 14:03:08 +01:00
|
|
|
void fire_fb_write(fs_inst *inst,
|
2014-09-16 23:16:20 +01:00
|
|
|
struct brw_reg payload,
|
2014-06-05 14:03:08 +01:00
|
|
|
struct brw_reg implied_header,
|
|
|
|
GLuint nr);
|
2018-10-29 20:06:14 +00:00
|
|
|
void generate_send(fs_inst *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg desc,
|
|
|
|
struct brw_reg ex_desc,
|
|
|
|
struct brw_reg payload,
|
|
|
|
struct brw_reg payload2);
|
2014-09-16 23:16:20 +01:00
|
|
|
void generate_fb_write(fs_inst *inst, struct brw_reg payload);
|
2016-07-22 00:52:33 +01:00
|
|
|
void generate_fb_read(fs_inst *inst, struct brw_reg dst,
|
|
|
|
struct brw_reg payload);
|
2015-09-29 22:32:02 +01:00
|
|
|
void generate_urb_read(fs_inst *inst, struct brw_reg dst, struct brw_reg payload);
|
2014-10-21 07:00:50 +01:00
|
|
|
void generate_urb_write(fs_inst *inst, struct brw_reg payload);
|
2014-08-27 19:33:25 +01:00
|
|
|
void generate_cs_terminate(fs_inst *inst, struct brw_reg payload);
|
2014-08-27 19:32:08 +01:00
|
|
|
void generate_barrier(fs_inst *inst, struct brw_reg src);
|
2017-06-14 19:06:45 +01:00
|
|
|
bool generate_linterp(fs_inst *inst, struct brw_reg dst,
|
2012-11-09 09:05:47 +00:00
|
|
|
struct brw_reg *src);
|
2014-08-03 10:23:31 +01:00
|
|
|
void generate_tex(fs_inst *inst, struct brw_reg dst, struct brw_reg src,
|
2015-11-02 23:24:05 +00:00
|
|
|
struct brw_reg surface_index,
|
2014-08-03 10:23:31 +01:00
|
|
|
struct brw_reg sampler_index);
|
2015-04-13 15:55:49 +01:00
|
|
|
void generate_get_buffer_size(fs_inst *inst, struct brw_reg dst,
|
|
|
|
struct brw_reg src,
|
|
|
|
struct brw_reg surf_index);
|
2017-06-15 23:41:40 +01:00
|
|
|
void generate_ddx(const fs_inst *inst,
|
|
|
|
struct brw_reg dst, struct brw_reg src);
|
|
|
|
void generate_ddy(const fs_inst *inst,
|
|
|
|
struct brw_reg dst, struct brw_reg src);
|
2013-10-16 19:45:06 +01:00
|
|
|
void generate_scratch_write(fs_inst *inst, struct brw_reg src);
|
|
|
|
void generate_scratch_read(fs_inst *inst, struct brw_reg dst);
|
2013-10-16 19:51:22 +01:00
|
|
|
void generate_scratch_read_gen7(fs_inst *inst, struct brw_reg dst);
|
2012-11-07 18:42:34 +00:00
|
|
|
void generate_uniform_pull_constant_load(fs_inst *inst, struct brw_reg dst,
|
|
|
|
struct brw_reg index,
|
|
|
|
struct brw_reg offset);
|
2012-12-05 08:06:30 +00:00
|
|
|
void generate_uniform_pull_constant_load_gen7(fs_inst *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg surf_index,
|
2016-10-26 22:25:06 +01:00
|
|
|
struct brw_reg payload);
|
2016-05-20 21:03:31 +01:00
|
|
|
void generate_varying_pull_constant_load_gen4(fs_inst *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg index);
|
2012-11-07 19:18:34 +00:00
|
|
|
void generate_varying_pull_constant_load_gen7(fs_inst *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg index,
|
|
|
|
struct brw_reg offset);
|
2012-12-06 18:36:11 +00:00
|
|
|
void generate_mov_dispatch_to_flags(fs_inst *inst);
|
2013-10-25 00:17:08 +01:00
|
|
|
|
2013-11-18 08:13:13 +00:00
|
|
|
void generate_pixel_interpolator_query(fs_inst *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src,
|
|
|
|
struct brw_reg msg_data,
|
|
|
|
unsigned msg_type);
|
|
|
|
|
2013-10-25 00:17:08 +01:00
|
|
|
void generate_set_sample_id(fs_inst *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg src0,
|
|
|
|
struct brw_reg src1);
|
|
|
|
|
2012-12-06 18:15:08 +00:00
|
|
|
void generate_discard_jump(fs_inst *inst);
|
|
|
|
|
2013-01-09 19:46:42 +00:00
|
|
|
void generate_pack_half_2x16_split(fs_inst *inst,
|
|
|
|
struct brw_reg dst,
|
|
|
|
struct brw_reg x,
|
|
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struct brw_reg y);
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|
|
|
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2013-03-19 22:28:11 +00:00
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|
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void generate_shader_time_add(fs_inst *inst,
|
|
|
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struct brw_reg payload,
|
|
|
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struct brw_reg offset,
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|
|
|
struct brw_reg value);
|
|
|
|
|
2015-11-08 02:58:34 +00:00
|
|
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void generate_mov_indirect(fs_inst *inst,
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|
|
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struct brw_reg dst,
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|
|
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struct brw_reg reg,
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|
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struct brw_reg indirect_byte_offset);
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|
|
|
2017-08-29 17:21:32 +01:00
|
|
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void generate_shuffle(fs_inst *inst,
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|
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struct brw_reg dst,
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struct brw_reg src,
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|
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struct brw_reg idx);
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|
|
|
2018-12-06 22:11:34 +00:00
|
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void generate_quad_swizzle(const fs_inst *inst,
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struct brw_reg dst, struct brw_reg src,
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|
|
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unsigned swiz);
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|
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2014-05-16 21:06:45 +01:00
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bool patch_discard_jumps_to_fb_writes();
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2012-11-09 09:05:47 +00:00
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2015-04-16 22:13:52 +01:00
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const struct brw_compiler *compiler;
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2015-04-16 22:34:04 +01:00
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void *log_data; /* Passed to compiler->*_log functions */
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|
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2016-08-22 23:01:08 +01:00
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const struct gen_device_info *devinfo;
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2012-11-09 09:05:47 +00:00
|
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2015-04-16 19:06:57 +01:00
|
|
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struct brw_codegen *p;
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2014-08-29 20:50:46 +01:00
|
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struct brw_stage_prog_data * const prog_data;
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2012-11-09 09:05:47 +00:00
|
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|
|
2016-05-18 22:39:52 +01:00
|
|
|
unsigned dispatch_width; /**< 8, 16 or 32 */
|
2012-11-09 09:05:47 +00:00
|
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|
|
2012-12-06 18:15:08 +00:00
|
|
|
exec_list discard_halt_patches;
|
2015-03-16 19:18:31 +00:00
|
|
|
unsigned promoted_constants;
|
2014-06-05 14:03:06 +01:00
|
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|
bool runtime_check_aads_emit;
|
2014-10-28 02:40:47 +00:00
|
|
|
bool debug_flag;
|
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|
|
const char *shader_name;
|
2016-01-15 04:27:51 +00:00
|
|
|
gl_shader_stage stage;
|
2012-11-09 09:05:47 +00:00
|
|
|
void *mem_ctx;
|
|
|
|
};
|
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|
2017-01-13 23:23:48 +00:00
|
|
|
namespace brw {
|
|
|
|
inline fs_reg
|
2017-01-13 23:36:51 +00:00
|
|
|
fetch_payload_reg(const brw::fs_builder &bld, uint8_t regs[2],
|
2017-01-13 23:23:48 +00:00
|
|
|
brw_reg_type type = BRW_REGISTER_TYPE_F, unsigned n = 1)
|
|
|
|
{
|
2017-01-13 23:36:51 +00:00
|
|
|
if (!regs[0])
|
2017-01-13 23:23:48 +00:00
|
|
|
return fs_reg();
|
2017-01-13 23:36:51 +00:00
|
|
|
|
|
|
|
if (bld.dispatch_width() > 16) {
|
|
|
|
const fs_reg tmp = bld.vgrf(type, n);
|
|
|
|
const brw::fs_builder hbld = bld.exec_all().group(16, 0);
|
|
|
|
const unsigned m = bld.dispatch_width() / hbld.dispatch_width();
|
|
|
|
fs_reg *const components = new fs_reg[n * m];
|
|
|
|
|
|
|
|
for (unsigned c = 0; c < n; c++) {
|
|
|
|
for (unsigned g = 0; g < m; g++) {
|
|
|
|
components[c * m + g] =
|
|
|
|
offset(retype(brw_vec8_grf(regs[g], 0), type), hbld, c);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
hbld.LOAD_PAYLOAD(tmp, components, n * m, 0);
|
|
|
|
|
|
|
|
delete[] components;
|
|
|
|
return tmp;
|
|
|
|
|
2017-01-13 23:23:48 +00:00
|
|
|
} else {
|
2017-01-13 23:36:51 +00:00
|
|
|
return fs_reg(retype(brw_vec8_grf(regs[0], 0), type));
|
2017-01-13 23:23:48 +00:00
|
|
|
}
|
|
|
|
}
|
2018-12-29 09:44:00 +00:00
|
|
|
|
2018-12-29 12:00:13 +00:00
|
|
|
bool
|
|
|
|
lower_src_modifiers(fs_visitor *v, bblock_t *block, fs_inst *inst, unsigned i);
|
2017-01-13 23:23:48 +00:00
|
|
|
}
|
|
|
|
|
2018-06-09 10:45:22 +01:00
|
|
|
void shuffle_from_32bit_read(const brw::fs_builder &bld,
|
|
|
|
const fs_reg &dst,
|
|
|
|
const fs_reg &src,
|
|
|
|
uint32_t first_component,
|
|
|
|
uint32_t components);
|
|
|
|
|
|
|
|
fs_reg shuffle_for_32bit_write(const brw::fs_builder &bld,
|
|
|
|
const fs_reg &src,
|
|
|
|
uint32_t first_component,
|
|
|
|
uint32_t components);
|
|
|
|
|
2016-03-09 13:12:43 +00:00
|
|
|
fs_reg setup_imm_df(const brw::fs_builder &bld,
|
|
|
|
double v);
|
2016-07-12 11:57:25 +01:00
|
|
|
|
2018-07-27 12:38:38 +01:00
|
|
|
fs_reg setup_imm_b(const brw::fs_builder &bld,
|
|
|
|
int8_t v);
|
|
|
|
|
|
|
|
fs_reg setup_imm_ub(const brw::fs_builder &bld,
|
|
|
|
uint8_t v);
|
|
|
|
|
2016-07-12 11:57:25 +01:00
|
|
|
enum brw_barycentric_mode brw_barycentric_mode(enum glsl_interp_mode mode,
|
|
|
|
nir_intrinsic_op op);
|
2017-03-20 16:04:38 +00:00
|
|
|
|
|
|
|
#endif /* BRW_FS_H */
|