2015-10-24 19:30:31 +01:00
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/*
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* Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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2018-11-09 18:49:55 +00:00
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#include "util/debug.h"
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2019-05-07 14:05:58 +01:00
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#include "util/u_math.h"
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2015-10-24 19:30:31 +01:00
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#include "ir3_nir.h"
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#include "ir3_compiler.h"
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#include "ir3_shader.h"
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2016-03-28 15:28:29 +01:00
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static const nir_shader_compiler_options options = {
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.lower_fpow = true,
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.lower_scmp = true,
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2019-06-06 15:29:35 +01:00
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.lower_flrp16 = true,
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2016-03-28 15:28:29 +01:00
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.lower_flrp32 = true,
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.lower_flrp64 = true,
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.lower_ffract = true,
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2019-06-03 21:18:55 +01:00
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.lower_fmod = true,
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2016-05-14 18:40:48 +01:00
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.lower_fdiv = true,
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2019-02-06 21:32:21 +00:00
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.lower_isign = true,
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2018-02-27 08:19:21 +00:00
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.lower_ldexp = true,
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2019-03-08 23:42:22 +00:00
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.lower_uadd_carry = true,
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2019-11-27 18:43:54 +00:00
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.lower_usub_borrow = true,
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2019-03-08 23:42:22 +00:00
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.lower_mul_high = true,
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2019-12-15 19:18:13 +00:00
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.lower_mul_2x32_64 = true,
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2016-03-28 15:28:29 +01:00
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.fuse_ffma = true,
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.vertex_id_zero_based = true,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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2019-03-23 15:38:37 +00:00
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.lower_all_io_to_elements = true,
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2018-06-01 19:07:15 +01:00
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.lower_helper_invocation = true,
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2019-03-19 18:45:40 +00:00
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.lower_bitfield_insert_to_shifts = true,
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.lower_bitfield_extract_to_shifts = true,
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2019-12-15 18:43:39 +00:00
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.lower_pack_half_2x16 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_unpack_half_2x16 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_unorm_4x8 = true,
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.lower_unpack_unorm_2x16 = true,
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2020-04-24 19:27:33 +01:00
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.lower_pack_split = true,
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2019-03-23 15:38:37 +00:00
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.use_interpolated_input_intrinsics = true,
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2019-06-04 01:11:57 +01:00
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.lower_rotate = true,
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2019-10-08 03:46:00 +01:00
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.lower_to_scalar = true,
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2019-09-27 18:15:02 +01:00
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.has_imul24 = true,
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2020-06-21 21:26:57 +01:00
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.lower_wpos_pntc = true,
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2016-03-28 15:28:29 +01:00
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};
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2019-02-26 13:28:09 +00:00
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/* we don't want to lower vertex_id to _zero_based on newer gpus: */
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static const nir_shader_compiler_options options_a6xx = {
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.lower_fpow = true,
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.lower_scmp = true,
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2019-06-06 15:29:35 +01:00
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.lower_flrp16 = true,
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2019-02-26 13:28:09 +00:00
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.lower_flrp32 = true,
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.lower_flrp64 = true,
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.lower_ffract = true,
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2019-06-03 21:18:55 +01:00
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.lower_fmod = true,
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2019-02-26 13:28:09 +00:00
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.lower_fdiv = true,
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.lower_isign = true,
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.lower_ldexp = true,
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2019-03-08 23:42:22 +00:00
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.lower_uadd_carry = true,
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2019-11-27 18:43:54 +00:00
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.lower_usub_borrow = true,
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2019-03-08 23:42:22 +00:00
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.lower_mul_high = true,
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2019-12-15 19:18:13 +00:00
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.lower_mul_2x32_64 = true,
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2019-02-26 13:28:09 +00:00
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.fuse_ffma = true,
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.vertex_id_zero_based = false,
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.lower_extract_byte = true,
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.lower_extract_word = true,
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2019-03-23 15:38:37 +00:00
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.lower_all_io_to_elements = true,
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2019-02-26 13:28:09 +00:00
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.lower_helper_invocation = true,
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2019-03-19 18:45:40 +00:00
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.lower_bitfield_insert_to_shifts = true,
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.lower_bitfield_extract_to_shifts = true,
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2019-12-15 18:43:39 +00:00
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.lower_pack_half_2x16 = true,
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.lower_pack_snorm_4x8 = true,
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.lower_pack_snorm_2x16 = true,
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.lower_pack_unorm_4x8 = true,
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.lower_pack_unorm_2x16 = true,
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.lower_unpack_half_2x16 = true,
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.lower_unpack_snorm_4x8 = true,
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.lower_unpack_snorm_2x16 = true,
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.lower_unpack_unorm_4x8 = true,
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.lower_unpack_unorm_2x16 = true,
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2020-04-24 19:27:33 +01:00
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.lower_pack_split = true,
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2019-03-23 15:38:37 +00:00
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.use_interpolated_input_intrinsics = true,
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2019-06-04 01:11:57 +01:00
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.lower_rotate = true,
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2019-07-12 20:36:45 +01:00
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.vectorize_io = true,
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2019-10-08 03:46:00 +01:00
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.lower_to_scalar = true,
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2019-09-27 18:15:02 +01:00
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.has_imul24 = true,
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2019-11-19 07:20:10 +00:00
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.max_unroll_iterations = 32,
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2020-06-21 21:26:57 +01:00
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.lower_wpos_pntc = true,
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2019-02-26 13:28:09 +00:00
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};
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2016-03-28 15:28:29 +01:00
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const nir_shader_compiler_options *
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2017-05-23 14:09:41 +01:00
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ir3_get_compiler_options(struct ir3_compiler *compiler)
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2016-03-28 15:28:29 +01:00
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{
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2019-02-26 13:28:09 +00:00
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if (compiler->gpu_id >= 600)
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return &options_a6xx;
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2016-03-28 15:28:29 +01:00
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return &options;
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}
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2015-10-24 19:54:56 +01:00
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#define OPT(nir, pass, ...) ({ \
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bool this_progress = false; \
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NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
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this_progress; \
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})
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#define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
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2016-05-09 17:41:00 +01:00
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static void
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ir3_optimize_loop(nir_shader *s)
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{
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bool progress;
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2018-08-19 00:42:04 +01:00
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unsigned lower_flrp =
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(s->options->lower_flrp16 ? 16 : 0) |
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(s->options->lower_flrp32 ? 32 : 0) |
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(s->options->lower_flrp64 ? 64 : 0);
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2016-05-09 17:41:00 +01:00
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do {
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progress = false;
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OPT_V(s, nir_lower_vars_to_ssa);
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2018-03-28 05:00:01 +01:00
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progress |= OPT(s, nir_opt_copy_prop_vars);
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2018-08-30 01:26:03 +01:00
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progress |= OPT(s, nir_opt_dead_write_vars);
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2019-08-30 05:14:54 +01:00
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progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
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2016-09-13 23:14:28 +01:00
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progress |= OPT(s, nir_lower_phis_to_scalar);
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2016-05-09 17:41:00 +01:00
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progress |= OPT(s, nir_copy_prop);
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progress |= OPT(s, nir_opt_dce);
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progress |= OPT(s, nir_opt_cse);
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2018-01-29 19:53:13 +00:00
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static int gcm = -1;
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if (gcm == -1)
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2018-11-09 18:49:55 +00:00
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gcm = env_var_as_unsigned("GCM", 0);
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2018-01-29 19:53:13 +00:00
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if (gcm == 1)
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progress |= OPT(s, nir_opt_gcm, true);
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else if (gcm == 2)
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progress |= OPT(s, nir_opt_gcm, false);
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2018-06-19 00:11:55 +01:00
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progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
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2018-01-26 15:43:48 +00:00
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progress |= OPT(s, nir_opt_intrinsics);
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2016-05-09 17:41:00 +01:00
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progress |= OPT(s, nir_opt_algebraic);
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2019-12-15 19:18:13 +00:00
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progress |= OPT(s, nir_lower_alu);
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2020-04-24 19:28:58 +01:00
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progress |= OPT(s, nir_lower_pack);
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2016-05-09 17:41:00 +01:00
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progress |= OPT(s, nir_opt_constant_folding);
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2018-08-19 00:42:04 +01:00
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if (lower_flrp != 0) {
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if (OPT(s, nir_lower_flrp,
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lower_flrp,
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false /* always_precise */,
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s->options->lower_ffma)) {
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OPT(s, nir_opt_constant_folding);
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progress = true;
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}
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/* Nothing should rematerialize any flrps, so we only
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* need to do this lowering once.
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*/
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lower_flrp = 0;
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}
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2018-01-26 15:43:48 +00:00
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progress |= OPT(s, nir_opt_dead_cf);
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if (OPT(s, nir_opt_trivial_continues)) {
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progress |= true;
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/* If nir_opt_trivial_continues makes progress, then we need to clean
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* things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
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* to make progress.
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*/
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OPT(s, nir_copy_prop);
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OPT(s, nir_opt_dce);
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}
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2019-04-08 11:13:49 +01:00
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progress |= OPT(s, nir_opt_if, false);
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2018-01-26 15:43:48 +00:00
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progress |= OPT(s, nir_opt_remove_phis);
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progress |= OPT(s, nir_opt_undef);
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2016-05-09 17:41:00 +01:00
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} while (progress);
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}
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2020-05-06 22:58:28 +01:00
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static bool
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should_split_wrmask(const nir_instr *instr, const void *data)
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{
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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switch (intr->intrinsic) {
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_shared:
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case nir_intrinsic_store_global:
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return true;
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default:
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return false;
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}
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}
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2019-06-05 19:43:13 +01:00
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void
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2020-06-15 22:24:00 +01:00
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ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
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2015-10-24 19:30:31 +01:00
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{
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struct nir_lower_tex_options tex_options = {
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.lower_rect = 0,
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2019-03-19 18:55:21 +00:00
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.lower_tg4_offsets = true,
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2015-10-24 19:30:31 +01:00
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};
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2020-06-15 22:24:00 +01:00
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if (compiler->gpu_id >= 400) {
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2015-10-24 19:30:31 +01:00
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/* a4xx seems to have *no* sam.p */
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tex_options.lower_txp = ~0; /* lower all txp */
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} else {
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/* a3xx just needs to avoid sam.p for 3d tex */
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tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
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}
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2018-11-09 16:08:16 +00:00
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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2015-10-24 19:30:31 +01:00
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debug_printf("----------------------\n");
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nir_print_shader(s, stdout);
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debug_printf("----------------------\n");
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}
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2020-06-15 22:24:00 +01:00
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if (s->info.stage == MESA_SHADER_GEOMETRY)
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NIR_PASS_V(s, ir3_nir_lower_gs);
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2015-10-24 19:54:56 +01:00
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2020-06-15 22:24:00 +01:00
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NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
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2020-06-10 10:11:27 +01:00
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2020-06-15 22:24:00 +01:00
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NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
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OPT_V(s, nir_lower_regs_to_ssa);
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OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
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2015-10-24 19:54:56 +01:00
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OPT_V(s, nir_lower_tex, &tex_options);
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OPT_V(s, nir_lower_load_const_to_scalar);
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2020-06-15 22:24:00 +01:00
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if (compiler->gpu_id < 500)
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2017-11-19 17:28:53 +00:00
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OPT_V(s, ir3_nir_lower_tg4_to_tex);
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2015-10-24 19:30:31 +01:00
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2016-05-09 17:41:00 +01:00
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ir3_optimize_loop(s);
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2015-10-24 19:30:31 +01:00
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2020-06-15 20:14:04 +01:00
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/* do idiv lowering after first opt loop to get a chance to propagate
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* constants for divide by immed power-of-two:
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2016-05-09 17:41:00 +01:00
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*/
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2019-02-05 15:56:24 +00:00
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const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
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2020-05-02 00:00:17 +01:00
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2020-06-15 20:14:04 +01:00
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if (idiv_progress)
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2016-05-09 17:41:00 +01:00
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ir3_optimize_loop(s);
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2015-10-24 19:30:31 +01:00
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2020-06-10 10:11:27 +01:00
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OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
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if (ir3_shader_debug & IR3_DBG_DISASM) {
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debug_printf("----------------------\n");
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nir_print_shader(s, stdout);
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debug_printf("----------------------\n");
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}
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nir_sweep(s);
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}
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2020-06-15 22:24:00 +01:00
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/**
|
|
|
|
* Late passes that need to be done after pscreen->finalize_nir()
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
|
|
|
|
{
|
2020-06-10 23:42:15 +01:00
|
|
|
NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
|
|
|
|
ir3_glsl_type_size, (nir_lower_io_options)0);
|
2020-06-15 22:24:00 +01:00
|
|
|
|
|
|
|
if (s->info.stage == MESA_SHADER_FRAGMENT) {
|
|
|
|
/* NOTE: lower load_barycentric_at_sample first, since it
|
|
|
|
* produces load_barycentric_at_offset:
|
|
|
|
*/
|
|
|
|
NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
|
|
|
|
NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
|
|
|
|
NIR_PASS_V(s, ir3_nir_move_varying_inputs);
|
|
|
|
NIR_PASS_V(s, nir_lower_fb_read);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (compiler->gpu_id >= 600 &&
|
|
|
|
s->info.stage == MESA_SHADER_FRAGMENT &&
|
|
|
|
!(ir3_shader_debug & IR3_DBG_NOFP16)) {
|
|
|
|
NIR_PASS_V(s, nir_lower_mediump_outputs);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* we cannot ensure that ir3_finalize_nir() is only called once, so
|
|
|
|
* we also need to do trig workarounds here:
|
|
|
|
*/
|
|
|
|
OPT_V(s, ir3_nir_apply_trig_workarounds);
|
|
|
|
|
|
|
|
ir3_optimize_loop(s);
|
|
|
|
}
|
|
|
|
|
2020-06-10 10:11:27 +01:00
|
|
|
void
|
|
|
|
ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
|
|
|
|
{
|
|
|
|
if (ir3_shader_debug & IR3_DBG_DISASM) {
|
|
|
|
debug_printf("----------------------\n");
|
|
|
|
nir_print_shader(s, stdout);
|
|
|
|
debug_printf("----------------------\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
bool progress = false;
|
|
|
|
|
|
|
|
if (so->key.has_gs || so->key.tessellation) {
|
|
|
|
switch (so->shader->type) {
|
|
|
|
case MESA_SHADER_VERTEX:
|
2020-06-15 22:12:58 +01:00
|
|
|
NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
|
2020-06-10 10:11:27 +01:00
|
|
|
progress = true;
|
|
|
|
break;
|
|
|
|
case MESA_SHADER_TESS_CTRL:
|
2020-06-15 22:12:58 +01:00
|
|
|
NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
|
2020-06-10 10:11:27 +01:00
|
|
|
NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
|
|
|
|
progress = true;
|
|
|
|
break;
|
|
|
|
case MESA_SHADER_TESS_EVAL:
|
|
|
|
NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
|
|
|
|
if (so->key.has_gs)
|
2020-06-15 22:12:58 +01:00
|
|
|
NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
|
2020-06-10 10:11:27 +01:00
|
|
|
progress = true;
|
|
|
|
break;
|
|
|
|
case MESA_SHADER_GEOMETRY:
|
|
|
|
NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
|
|
|
|
progress = true;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->info.stage == MESA_SHADER_VERTEX) {
|
|
|
|
if (so->key.ucp_enables)
|
|
|
|
progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
|
|
|
|
if (so->key.vclamp_color)
|
|
|
|
progress |= OPT(s, nir_lower_clamp_color_outputs);
|
|
|
|
} else if (s->info.stage == MESA_SHADER_FRAGMENT) {
|
|
|
|
if (so->key.ucp_enables)
|
|
|
|
progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
|
|
|
|
if (so->key.fclamp_color)
|
|
|
|
progress |= OPT(s, nir_lower_clamp_color_outputs);
|
|
|
|
}
|
|
|
|
if (so->key.color_two_side) {
|
|
|
|
OPT_V(s, nir_lower_two_sided_color);
|
|
|
|
progress = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
struct nir_lower_tex_options tex_options = { };
|
|
|
|
|
|
|
|
switch (so->shader->type) {
|
|
|
|
case MESA_SHADER_FRAGMENT:
|
|
|
|
tex_options.saturate_s = so->key.fsaturate_s;
|
|
|
|
tex_options.saturate_t = so->key.fsaturate_t;
|
|
|
|
tex_options.saturate_r = so->key.fsaturate_r;
|
|
|
|
break;
|
|
|
|
case MESA_SHADER_VERTEX:
|
|
|
|
tex_options.saturate_s = so->key.vsaturate_s;
|
|
|
|
tex_options.saturate_t = so->key.vsaturate_t;
|
|
|
|
tex_options.saturate_r = so->key.vsaturate_r;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
/* TODO */
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (tex_options.saturate_s || tex_options.saturate_t ||
|
|
|
|
tex_options.saturate_r) {
|
|
|
|
progress |= OPT(s, nir_lower_tex, &tex_options);
|
|
|
|
}
|
|
|
|
|
2020-06-17 18:07:09 +01:00
|
|
|
if (!so->binning_pass)
|
|
|
|
OPT_V(s, ir3_nir_analyze_ubo_ranges, so);
|
|
|
|
|
|
|
|
progress |= OPT(s, ir3_nir_lower_ubo_loads, so);
|
2020-06-15 20:14:04 +01:00
|
|
|
|
|
|
|
/* UBO offset lowering has to come after we've decided what will
|
|
|
|
* be left as load_ubo
|
|
|
|
*/
|
|
|
|
OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
|
|
|
|
|
2020-06-10 10:11:27 +01:00
|
|
|
if (progress)
|
|
|
|
ir3_optimize_loop(s);
|
|
|
|
|
2019-09-27 11:49:06 +01:00
|
|
|
/* Do late algebraic optimization to turn add(a, neg(b)) back into
|
|
|
|
* subs, then the mandatory cleanup after algebraic. Note that it may
|
|
|
|
* produce fnegs, and if so then we need to keep running to squash
|
|
|
|
* fneg(fneg(a)).
|
|
|
|
*/
|
|
|
|
bool more_late_algebraic = true;
|
|
|
|
while (more_late_algebraic) {
|
|
|
|
more_late_algebraic = OPT(s, nir_opt_algebraic_late);
|
|
|
|
OPT_V(s, nir_opt_constant_folding);
|
|
|
|
OPT_V(s, nir_copy_prop);
|
|
|
|
OPT_V(s, nir_opt_dce);
|
|
|
|
OPT_V(s, nir_opt_cse);
|
|
|
|
}
|
|
|
|
|
2019-05-22 20:23:03 +01:00
|
|
|
OPT_V(s, nir_opt_sink, nir_move_const_undef);
|
2018-06-05 18:42:21 +01:00
|
|
|
|
2018-11-09 16:08:16 +00:00
|
|
|
if (ir3_shader_debug & IR3_DBG_DISASM) {
|
2015-10-24 19:30:31 +01:00
|
|
|
debug_printf("----------------------\n");
|
|
|
|
nir_print_shader(s, stdout);
|
|
|
|
debug_printf("----------------------\n");
|
|
|
|
}
|
|
|
|
|
|
|
|
nir_sweep(s);
|
2020-06-15 20:14:04 +01:00
|
|
|
|
|
|
|
/* Binning pass variants re-use the const_state of the corresponding
|
|
|
|
* draw pass shader, so that same const emit can be re-used for both
|
|
|
|
* passes:
|
|
|
|
*/
|
|
|
|
if (!so->binning_pass)
|
|
|
|
ir3_setup_const_state(s, so, ir3_const_state(so));
|
2015-10-24 19:30:31 +01:00
|
|
|
}
|
2017-10-30 17:23:37 +00:00
|
|
|
|
2019-05-07 14:05:58 +01:00
|
|
|
static void
|
2017-10-30 17:23:37 +00:00
|
|
|
ir3_nir_scan_driver_consts(nir_shader *shader,
|
2019-05-06 22:52:27 +01:00
|
|
|
struct ir3_const_state *layout)
|
2017-10-30 17:23:37 +00:00
|
|
|
{
|
2020-03-21 18:06:59 +00:00
|
|
|
nir_foreach_function (function, shader) {
|
2017-10-30 17:23:37 +00:00
|
|
|
if (!function->impl)
|
|
|
|
continue;
|
|
|
|
|
2020-03-21 18:06:59 +00:00
|
|
|
nir_foreach_block (block, function->impl) {
|
|
|
|
nir_foreach_instr (instr, block) {
|
2017-10-30 17:23:37 +00:00
|
|
|
if (instr->type != nir_instr_type_intrinsic)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
nir_intrinsic_instr *intr =
|
|
|
|
nir_instr_as_intrinsic(instr);
|
|
|
|
unsigned idx;
|
|
|
|
|
|
|
|
switch (intr->intrinsic) {
|
|
|
|
case nir_intrinsic_get_buffer_size:
|
2019-03-29 19:57:52 +00:00
|
|
|
idx = nir_src_as_uint(intr->src[0]);
|
2017-10-30 17:23:37 +00:00
|
|
|
if (layout->ssbo_size.mask & (1 << idx))
|
|
|
|
break;
|
|
|
|
layout->ssbo_size.mask |= (1 << idx);
|
|
|
|
layout->ssbo_size.off[idx] =
|
|
|
|
layout->ssbo_size.count;
|
|
|
|
layout->ssbo_size.count += 1; /* one const per */
|
|
|
|
break;
|
2020-02-05 22:54:42 +00:00
|
|
|
case nir_intrinsic_image_atomic_add:
|
|
|
|
case nir_intrinsic_image_atomic_imin:
|
|
|
|
case nir_intrinsic_image_atomic_umin:
|
|
|
|
case nir_intrinsic_image_atomic_imax:
|
|
|
|
case nir_intrinsic_image_atomic_umax:
|
|
|
|
case nir_intrinsic_image_atomic_and:
|
|
|
|
case nir_intrinsic_image_atomic_or:
|
|
|
|
case nir_intrinsic_image_atomic_xor:
|
|
|
|
case nir_intrinsic_image_atomic_exchange:
|
|
|
|
case nir_intrinsic_image_atomic_comp_swap:
|
|
|
|
case nir_intrinsic_image_store:
|
|
|
|
case nir_intrinsic_image_size:
|
|
|
|
idx = nir_src_as_uint(intr->src[0]);
|
2017-11-09 15:57:55 +00:00
|
|
|
if (layout->image_dims.mask & (1 << idx))
|
|
|
|
break;
|
|
|
|
layout->image_dims.mask |= (1 << idx);
|
2018-06-07 18:54:15 +01:00
|
|
|
layout->image_dims.off[idx] =
|
2017-11-09 15:57:55 +00:00
|
|
|
layout->image_dims.count;
|
|
|
|
layout->image_dims.count += 3; /* three const per */
|
|
|
|
break;
|
2019-08-01 22:22:46 +01:00
|
|
|
case nir_intrinsic_load_base_vertex:
|
|
|
|
case nir_intrinsic_load_first_vertex:
|
|
|
|
layout->num_driver_params =
|
|
|
|
MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
|
|
|
|
break;
|
2019-11-17 17:17:47 +00:00
|
|
|
case nir_intrinsic_load_base_instance:
|
|
|
|
layout->num_driver_params =
|
|
|
|
MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
|
|
|
|
break;
|
2019-08-01 22:22:46 +01:00
|
|
|
case nir_intrinsic_load_user_clip_plane:
|
2020-07-05 06:58:01 +01:00
|
|
|
idx = nir_intrinsic_ucp_id(intr);
|
2019-08-01 22:22:46 +01:00
|
|
|
layout->num_driver_params =
|
2020-07-05 06:58:01 +01:00
|
|
|
MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
|
2019-08-01 22:22:46 +01:00
|
|
|
break;
|
|
|
|
case nir_intrinsic_load_num_work_groups:
|
|
|
|
layout->num_driver_params =
|
|
|
|
MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
|
|
|
|
break;
|
|
|
|
case nir_intrinsic_load_local_group_size:
|
|
|
|
layout->num_driver_params =
|
|
|
|
MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
|
|
|
|
break;
|
2017-10-30 17:23:37 +00:00
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2019-05-07 14:05:58 +01:00
|
|
|
|
2020-06-15 20:14:04 +01:00
|
|
|
/* Sets up the variant-dependent constant state for the ir3_shader. Note
|
2020-05-30 00:31:43 +01:00
|
|
|
* that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
|
|
|
|
* maximum number of driver params that would eventually be used, to leave
|
|
|
|
* space for this function to allocate the driver params.
|
|
|
|
*/
|
|
|
|
void
|
2020-06-15 20:14:04 +01:00
|
|
|
ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
|
|
|
|
struct ir3_const_state *const_state)
|
2019-05-07 14:05:58 +01:00
|
|
|
{
|
2020-06-15 20:14:04 +01:00
|
|
|
struct ir3_compiler *compiler = v->shader->compiler;
|
2019-05-07 14:05:58 +01:00
|
|
|
|
|
|
|
memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
|
|
|
|
|
|
|
|
ir3_nir_scan_driver_consts(nir, const_state);
|
|
|
|
|
2019-08-01 22:22:46 +01:00
|
|
|
if ((compiler->gpu_id < 500) &&
|
2020-06-15 20:14:04 +01:00
|
|
|
(v->shader->stream_output.num_outputs > 0)) {
|
2019-08-01 22:22:46 +01:00
|
|
|
const_state->num_driver_params =
|
|
|
|
MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
|
|
|
|
}
|
|
|
|
|
2020-06-14 20:54:05 +01:00
|
|
|
const_state->num_ubos = nir->info.num_ubos;
|
2020-05-13 00:07:50 +01:00
|
|
|
|
2019-08-01 22:22:46 +01:00
|
|
|
/* num_driver_params is scalar, align to vec4: */
|
|
|
|
const_state->num_driver_params = align(const_state->num_driver_params, 4);
|
|
|
|
|
2020-06-14 20:44:17 +01:00
|
|
|
debug_assert((const_state->ubo_state.size % 16) == 0);
|
|
|
|
unsigned constoff = const_state->ubo_state.size / 16;
|
2019-05-07 14:05:58 +01:00
|
|
|
unsigned ptrsz = ir3_pointer_size(compiler);
|
|
|
|
|
|
|
|
if (const_state->num_ubos > 0) {
|
|
|
|
const_state->offsets.ubo = constoff;
|
2020-05-13 00:07:50 +01:00
|
|
|
constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
|
2019-05-07 14:05:58 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
if (const_state->ssbo_size.count > 0) {
|
|
|
|
unsigned cnt = const_state->ssbo_size.count;
|
|
|
|
const_state->offsets.ssbo_sizes = constoff;
|
|
|
|
constoff += align(cnt, 4) / 4;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (const_state->image_dims.count > 0) {
|
|
|
|
unsigned cnt = const_state->image_dims.count;
|
|
|
|
const_state->offsets.image_dims = constoff;
|
|
|
|
constoff += align(cnt, 4) / 4;
|
|
|
|
}
|
|
|
|
|
2020-06-24 20:58:44 +01:00
|
|
|
if (const_state->num_driver_params > 0) {
|
|
|
|
/* offset cannot be 0 for vs params loaded by CP_DRAW_INDIRECT_MULTI */
|
|
|
|
if (v->type == MESA_SHADER_VERTEX && compiler->gpu_id >= 600)
|
|
|
|
constoff = MAX2(constoff, 1);
|
2019-08-01 22:22:46 +01:00
|
|
|
const_state->offsets.driver_param = constoff;
|
2020-06-24 20:58:44 +01:00
|
|
|
}
|
2019-08-01 22:22:46 +01:00
|
|
|
constoff += const_state->num_driver_params / 4;
|
2019-05-07 14:05:58 +01:00
|
|
|
|
2020-06-15 20:14:04 +01:00
|
|
|
if ((v->type == MESA_SHADER_VERTEX) &&
|
2019-05-07 14:05:58 +01:00
|
|
|
(compiler->gpu_id < 500) &&
|
2020-06-15 20:14:04 +01:00
|
|
|
v->shader->stream_output.num_outputs > 0) {
|
2019-05-07 14:05:58 +01:00
|
|
|
const_state->offsets.tfbo = constoff;
|
|
|
|
constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
|
|
|
|
}
|
|
|
|
|
2020-06-15 20:14:04 +01:00
|
|
|
switch (v->type) {
|
2019-10-11 05:02:45 +01:00
|
|
|
case MESA_SHADER_VERTEX:
|
|
|
|
const_state->offsets.primitive_param = constoff;
|
|
|
|
constoff += 1;
|
|
|
|
break;
|
2019-10-23 03:44:42 +01:00
|
|
|
case MESA_SHADER_TESS_CTRL:
|
|
|
|
case MESA_SHADER_TESS_EVAL:
|
|
|
|
constoff = align(constoff - 1, 4) + 3;
|
|
|
|
const_state->offsets.primitive_param = constoff;
|
|
|
|
const_state->offsets.primitive_map = constoff + 5;
|
|
|
|
constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
|
|
|
|
break;
|
2019-10-11 05:02:45 +01:00
|
|
|
case MESA_SHADER_GEOMETRY:
|
|
|
|
const_state->offsets.primitive_param = constoff;
|
|
|
|
const_state->offsets.primitive_map = constoff + 1;
|
|
|
|
constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2019-05-07 14:05:58 +01:00
|
|
|
const_state->offsets.immediate = constoff;
|
2020-05-30 00:31:43 +01:00
|
|
|
|
2020-06-24 11:03:59 +01:00
|
|
|
assert(constoff <= ir3_max_const(v));
|
2019-05-07 14:05:58 +01:00
|
|
|
}
|