2015-04-16 18:41:33 +01:00
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/*
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* Copyright © 2011 Red Hat All Rights Reserved.
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* Copyright © 2014 Advanced Micro Devices, Inc.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE COPYRIGHT HOLDERS, AUTHORS
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* AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*/
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/* Contact:
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* Marek Olšák <maraeo@gmail.com>
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*/
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#include "amdgpu_winsys.h"
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2016-10-23 19:17:32 +01:00
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#include "util/u_format.h"
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2015-04-16 18:41:33 +01:00
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#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
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#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
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#endif
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2016-10-21 12:31:40 +01:00
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#ifndef CIASICIDGFXENGINE_ARCTICISLAND
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#define CIASICIDGFXENGINE_ARCTICISLAND 0x0000000D
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#endif
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2015-04-16 18:41:33 +01:00
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2016-10-23 19:17:32 +01:00
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static int amdgpu_surface_sanity(const struct pipe_resource *tex)
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2015-04-16 18:41:33 +01:00
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{
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/* all dimension must be at least 1 ! */
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2016-10-23 19:17:32 +01:00
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if (!tex->width0 || !tex->height0 || !tex->depth0 ||
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!tex->array_size)
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2015-04-16 18:41:33 +01:00
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return -EINVAL;
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2016-10-23 19:17:32 +01:00
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switch (tex->nr_samples) {
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case 0:
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2015-04-16 18:41:33 +01:00
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case 1:
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case 2:
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case 4:
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case 8:
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break;
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default:
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return -EINVAL;
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}
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2016-10-23 19:17:32 +01:00
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switch (tex->target) {
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case PIPE_TEXTURE_1D:
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if (tex->height0 > 1)
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2015-04-16 18:41:33 +01:00
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return -EINVAL;
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/* fall through */
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2016-10-23 19:17:32 +01:00
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case PIPE_TEXTURE_2D:
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case PIPE_TEXTURE_RECT:
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if (tex->depth0 > 1 || tex->array_size > 1)
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2015-04-16 18:41:33 +01:00
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return -EINVAL;
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break;
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2016-10-23 19:17:32 +01:00
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case PIPE_TEXTURE_3D:
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if (tex->array_size > 1)
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2015-04-16 18:41:33 +01:00
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return -EINVAL;
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break;
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2016-10-23 19:17:32 +01:00
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case PIPE_TEXTURE_1D_ARRAY:
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if (tex->height0 > 1)
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2015-04-16 18:41:33 +01:00
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return -EINVAL;
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/* fall through */
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2016-10-23 19:17:32 +01:00
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case PIPE_TEXTURE_CUBE:
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case PIPE_TEXTURE_2D_ARRAY:
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case PIPE_TEXTURE_CUBE_ARRAY:
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if (tex->depth0 > 1)
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2015-04-16 18:41:33 +01:00
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return -EINVAL;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static void *ADDR_API allocSysMem(const ADDR_ALLOCSYSMEM_INPUT * pInput)
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{
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return malloc(pInput->sizeInBytes);
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}
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static ADDR_E_RETURNCODE ADDR_API freeSysMem(const ADDR_FREESYSMEM_INPUT * pInput)
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{
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free(pInput->pVirtAddr);
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return ADDR_OK;
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}
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ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
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{
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ADDR_CREATE_INPUT addrCreateInput = {0};
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ADDR_CREATE_OUTPUT addrCreateOutput = {0};
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ADDR_REGISTER_VALUE regValue = {0};
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ADDR_CREATE_FLAGS createFlags = {{0}};
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ADDR_E_RETURNCODE addrRet;
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addrCreateInput.size = sizeof(ADDR_CREATE_INPUT);
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addrCreateOutput.size = sizeof(ADDR_CREATE_OUTPUT);
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regValue.gbAddrConfig = ws->amdinfo.gb_addr_cfg;
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2016-10-21 12:31:40 +01:00
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createFlags.value = 0;
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if (ws->info.chip_class >= GFX9) {
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addrCreateInput.chipEngine = CIASICIDGFXENGINE_ARCTICISLAND;
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regValue.blockVarSizeLog2 = 0;
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2016-02-11 09:17:33 +00:00
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} else {
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2016-10-21 12:31:40 +01:00
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regValue.noOfBanks = ws->amdinfo.mc_arb_ramcfg & 0x3;
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regValue.noOfRanks = (ws->amdinfo.mc_arb_ramcfg & 0x4) >> 2;
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regValue.backendDisables = ws->amdinfo.enabled_rb_pipes_mask;
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regValue.pTileConfig = ws->amdinfo.gb_tile_mode;
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regValue.noOfEntries = ARRAY_SIZE(ws->amdinfo.gb_tile_mode);
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if (ws->info.chip_class == SI) {
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regValue.pMacroTileConfig = NULL;
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regValue.noOfMacroEntries = 0;
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} else {
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regValue.pMacroTileConfig = ws->amdinfo.gb_macro_tile_mode;
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regValue.noOfMacroEntries = ARRAY_SIZE(ws->amdinfo.gb_macro_tile_mode);
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}
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createFlags.useTileIndex = 1;
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createFlags.useHtileSliceAlign = 1;
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addrCreateInput.chipEngine = CIASICIDGFXENGINE_SOUTHERNISLAND;
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addrCreateInput.chipFamily = ws->family;
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addrCreateInput.chipRevision = ws->rev_id;
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2016-02-11 09:17:33 +00:00
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}
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2015-04-16 18:41:33 +01:00
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addrCreateInput.chipFamily = ws->family;
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addrCreateInput.chipRevision = ws->rev_id;
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addrCreateInput.callbacks.allocSysMem = allocSysMem;
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addrCreateInput.callbacks.freeSysMem = freeSysMem;
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addrCreateInput.callbacks.debugPrint = 0;
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2016-10-21 12:31:40 +01:00
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addrCreateInput.createFlags = createFlags;
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2015-04-16 18:41:33 +01:00
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addrCreateInput.regValue = regValue;
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addrRet = AddrCreate(&addrCreateInput, &addrCreateOutput);
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if (addrRet != ADDR_OK)
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return NULL;
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return addrCreateOutput.hLib;
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}
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2016-10-20 21:14:04 +01:00
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static int gfx6_compute_level(struct amdgpu_winsys *ws,
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const struct pipe_resource *tex,
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struct radeon_surf *surf, bool is_stencil,
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unsigned level, bool compressed,
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ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
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ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
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ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
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ADDR_COMPUTE_DCCINFO_OUTPUT *AddrDccOut,
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ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
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ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
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2015-04-16 18:41:33 +01:00
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{
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2016-10-23 12:08:46 +01:00
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struct legacy_surf_level *surf_level;
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2015-04-16 18:41:33 +01:00
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ADDR_E_RETURNCODE ret;
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AddrSurfInfoIn->mipLevel = level;
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2016-10-23 19:17:32 +01:00
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AddrSurfInfoIn->width = u_minify(tex->width0, level);
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AddrSurfInfoIn->height = u_minify(tex->height0, level);
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2015-04-16 18:41:33 +01:00
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2016-10-23 19:17:32 +01:00
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if (tex->target == PIPE_TEXTURE_3D)
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AddrSurfInfoIn->numSlices = u_minify(tex->depth0, level);
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else if (tex->target == PIPE_TEXTURE_CUBE)
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2015-04-16 18:41:33 +01:00
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AddrSurfInfoIn->numSlices = 6;
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else
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2016-10-23 19:17:32 +01:00
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AddrSurfInfoIn->numSlices = tex->array_size;
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2015-04-16 18:41:33 +01:00
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if (level > 0) {
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/* Set the base level pitch. This is needed for calculation
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* of non-zero levels. */
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if (is_stencil)
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2016-10-23 12:08:46 +01:00
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AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
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2015-04-16 18:41:33 +01:00
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else
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2016-10-23 12:08:46 +01:00
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AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
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2015-04-16 18:41:33 +01:00
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/* Convert blocks to pixels for compressed formats. */
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if (compressed)
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AddrSurfInfoIn->basePitch *= surf->blk_w;
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}
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ret = AddrComputeSurfaceInfo(ws->addrlib,
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AddrSurfInfoIn,
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AddrSurfInfoOut);
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if (ret != ADDR_OK) {
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return ret;
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}
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2016-10-23 12:08:46 +01:00
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surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
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2016-10-23 20:26:43 +01:00
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surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
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2015-04-16 18:41:33 +01:00
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surf_level->slice_size = AddrSurfInfoOut->sliceSize;
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surf_level->nblk_x = AddrSurfInfoOut->pitch;
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surf_level->nblk_y = AddrSurfInfoOut->height;
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switch (AddrSurfInfoOut->tileMode) {
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case ADDR_TM_LINEAR_ALIGNED:
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surf_level->mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
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break;
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case ADDR_TM_1D_TILED_THIN1:
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surf_level->mode = RADEON_SURF_MODE_1D;
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break;
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case ADDR_TM_2D_TILED_THIN1:
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surf_level->mode = RADEON_SURF_MODE_2D;
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break;
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default:
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assert(0);
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}
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if (is_stencil)
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2016-10-23 12:08:46 +01:00
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surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
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2015-04-16 18:41:33 +01:00
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else
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2016-10-23 12:08:46 +01:00
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surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
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2015-04-16 18:41:33 +01:00
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2016-10-23 20:26:43 +01:00
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surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
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2015-10-20 23:10:36 +01:00
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2016-06-03 19:40:30 +01:00
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/* Clear DCC fields at the beginning. */
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surf_level->dcc_offset = 0;
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2016-06-03 19:48:01 +01:00
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/* The previous level's flag tells us if we can use DCC for this level. */
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if (AddrSurfInfoIn->flags.dccCompatible &&
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(level == 0 || AddrDccOut->subLvlCompressible)) {
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2015-10-20 23:10:36 +01:00
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AddrDccIn->colorSurfSize = AddrSurfInfoOut->surfSize;
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AddrDccIn->tileMode = AddrSurfInfoOut->tileMode;
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AddrDccIn->tileInfo = *AddrSurfInfoOut->pTileInfo;
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AddrDccIn->tileIndex = AddrSurfInfoOut->tileIndex;
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AddrDccIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
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ret = AddrComputeDccInfo(ws->addrlib,
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AddrDccIn,
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AddrDccOut);
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if (ret == ADDR_OK) {
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surf_level->dcc_offset = surf->dcc_size;
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2016-06-03 19:48:01 +01:00
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surf_level->dcc_fast_clear_size = AddrDccOut->dccFastClearSize;
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2016-10-26 16:43:19 +01:00
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surf->num_dcc_levels = level + 1;
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2015-10-20 23:10:36 +01:00
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surf->dcc_size = surf_level->dcc_offset + AddrDccOut->dccRamSize;
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surf->dcc_alignment = MAX2(surf->dcc_alignment, AddrDccOut->dccRamBaseAlign);
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}
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}
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2016-10-11 22:19:46 +01:00
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/* TC-compatible HTILE. */
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if (!is_stencil &&
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AddrSurfInfoIn->flags.depth &&
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AddrSurfInfoIn->flags.tcCompatible &&
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surf_level->mode == RADEON_SURF_MODE_2D &&
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level == 0) {
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AddrHtileIn->flags.tcCompatible = 1;
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AddrHtileIn->pitch = AddrSurfInfoOut->pitch;
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AddrHtileIn->height = AddrSurfInfoOut->height;
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AddrHtileIn->numSlices = AddrSurfInfoOut->depth;
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AddrHtileIn->blockWidth = ADDR_HTILE_BLOCKSIZE_8;
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AddrHtileIn->blockHeight = ADDR_HTILE_BLOCKSIZE_8;
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AddrHtileIn->pTileInfo = AddrSurfInfoOut->pTileInfo;
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AddrHtileIn->tileIndex = AddrSurfInfoOut->tileIndex;
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AddrHtileIn->macroModeIndex = AddrSurfInfoOut->macroModeIndex;
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ret = AddrComputeHtileInfo(ws->addrlib,
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AddrHtileIn,
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AddrHtileOut);
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if (ret == ADDR_OK) {
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surf->htile_size = AddrHtileOut->htileBytes;
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surf->htile_alignment = AddrHtileOut->baseAlign;
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}
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}
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2015-04-16 18:41:33 +01:00
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return 0;
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}
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2016-06-08 19:24:21 +01:00
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#define G_009910_MICRO_TILE_MODE(x) (((x) >> 0) & 0x03)
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#define G_009910_MICRO_TILE_MODE_NEW(x) (((x) >> 22) & 0x07)
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2016-10-20 21:14:04 +01:00
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static void gfx6_set_micro_tile_mode(struct radeon_surf *surf,
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struct radeon_info *info)
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2016-06-08 19:24:21 +01:00
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{
|
2016-10-23 12:08:46 +01:00
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uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
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2016-06-08 19:24:21 +01:00
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if (info->chip_class >= CIK)
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surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
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else
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surf->micro_tile_mode = G_009910_MICRO_TILE_MODE(tile_mode);
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}
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2016-10-24 18:05:10 +01:00
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static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
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{
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unsigned index, tileb;
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tileb = 8 * 8 * surf->bpe;
|
2016-10-23 12:08:46 +01:00
|
|
|
tileb = MIN2(surf->u.legacy.tile_split, tileb);
|
2016-10-24 18:05:10 +01:00
|
|
|
|
|
|
|
for (index = 0; tileb > 64; index++)
|
|
|
|
tileb >>= 1;
|
|
|
|
|
|
|
|
assert(index < 16);
|
|
|
|
return index;
|
|
|
|
}
|
|
|
|
|
2016-10-20 21:14:04 +01:00
|
|
|
static int gfx6_surface_init(struct radeon_winsys *rws,
|
|
|
|
const struct pipe_resource *tex,
|
|
|
|
unsigned flags, unsigned bpe,
|
|
|
|
enum radeon_surf_mode mode,
|
|
|
|
struct radeon_surf *surf)
|
2015-04-16 18:41:33 +01:00
|
|
|
{
|
|
|
|
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
|
2016-10-23 19:17:32 +01:00
|
|
|
unsigned level;
|
2015-04-16 18:41:33 +01:00
|
|
|
bool compressed;
|
|
|
|
ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
|
|
|
|
ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
|
2015-10-20 23:10:36 +01:00
|
|
|
ADDR_COMPUTE_DCCINFO_INPUT AddrDccIn = {0};
|
|
|
|
ADDR_COMPUTE_DCCINFO_OUTPUT AddrDccOut = {0};
|
2016-10-11 22:19:46 +01:00
|
|
|
ADDR_COMPUTE_HTILE_INFO_INPUT AddrHtileIn = {0};
|
|
|
|
ADDR_COMPUTE_HTILE_INFO_OUTPUT AddrHtileOut = {0};
|
2015-04-16 18:41:33 +01:00
|
|
|
ADDR_TILEINFO AddrTileInfoIn = {0};
|
|
|
|
ADDR_TILEINFO AddrTileInfoOut = {0};
|
|
|
|
int r;
|
|
|
|
|
2016-10-23 19:17:32 +01:00
|
|
|
r = amdgpu_surface_sanity(tex);
|
2015-04-16 18:41:33 +01:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
AddrSurfInfoIn.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_INPUT);
|
|
|
|
AddrSurfInfoOut.size = sizeof(ADDR_COMPUTE_SURFACE_INFO_OUTPUT);
|
2015-10-20 23:10:36 +01:00
|
|
|
AddrDccIn.size = sizeof(ADDR_COMPUTE_DCCINFO_INPUT);
|
|
|
|
AddrDccOut.size = sizeof(ADDR_COMPUTE_DCCINFO_OUTPUT);
|
2016-10-11 22:19:46 +01:00
|
|
|
AddrHtileIn.size = sizeof(ADDR_COMPUTE_HTILE_INFO_INPUT);
|
|
|
|
AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
|
|
|
|
|
2016-10-23 19:17:32 +01:00
|
|
|
surf->blk_w = util_format_get_blockwidth(tex->format);
|
|
|
|
surf->blk_h = util_format_get_blockheight(tex->format);
|
|
|
|
surf->bpe = bpe;
|
|
|
|
surf->flags = flags;
|
|
|
|
|
2015-04-16 18:41:33 +01:00
|
|
|
compressed = surf->blk_w == 4 && surf->blk_h == 4;
|
|
|
|
|
|
|
|
/* MSAA and FMASK require 2D tiling. */
|
2016-10-23 19:17:32 +01:00
|
|
|
if (tex->nr_samples > 1 ||
|
|
|
|
(flags & RADEON_SURF_FMASK))
|
2015-04-16 18:41:33 +01:00
|
|
|
mode = RADEON_SURF_MODE_2D;
|
|
|
|
|
|
|
|
/* DB doesn't support linear layouts. */
|
2016-10-23 19:17:32 +01:00
|
|
|
if (flags & (RADEON_SURF_Z_OR_SBUFFER) &&
|
2015-04-16 18:41:33 +01:00
|
|
|
mode < RADEON_SURF_MODE_1D)
|
|
|
|
mode = RADEON_SURF_MODE_1D;
|
|
|
|
|
|
|
|
/* Set the requested tiling mode. */
|
|
|
|
switch (mode) {
|
|
|
|
case RADEON_SURF_MODE_LINEAR_ALIGNED:
|
|
|
|
AddrSurfInfoIn.tileMode = ADDR_TM_LINEAR_ALIGNED;
|
|
|
|
break;
|
|
|
|
case RADEON_SURF_MODE_1D:
|
|
|
|
AddrSurfInfoIn.tileMode = ADDR_TM_1D_TILED_THIN1;
|
|
|
|
break;
|
|
|
|
case RADEON_SURF_MODE_2D:
|
|
|
|
AddrSurfInfoIn.tileMode = ADDR_TM_2D_TILED_THIN1;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* The format must be set correctly for the allocation of compressed
|
|
|
|
* textures to work. In other cases, setting the bpp is sufficient. */
|
|
|
|
if (compressed) {
|
2016-10-23 19:17:32 +01:00
|
|
|
switch (bpe) {
|
2015-04-16 18:41:33 +01:00
|
|
|
case 8:
|
|
|
|
AddrSurfInfoIn.format = ADDR_FMT_BC1;
|
|
|
|
break;
|
|
|
|
case 16:
|
|
|
|
AddrSurfInfoIn.format = ADDR_FMT_BC3;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
assert(0);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else {
|
2016-10-23 19:17:32 +01:00
|
|
|
AddrDccIn.bpp = AddrSurfInfoIn.bpp = bpe * 8;
|
2015-04-16 18:41:33 +01:00
|
|
|
}
|
|
|
|
|
2016-10-23 19:17:32 +01:00
|
|
|
AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
|
|
|
|
tex->nr_samples ? tex->nr_samples : 1;
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoIn.tileIndex = -1;
|
|
|
|
|
|
|
|
/* Set the micro tile type. */
|
2016-10-23 19:17:32 +01:00
|
|
|
if (flags & RADEON_SURF_SCANOUT)
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
|
2016-10-24 17:01:52 +01:00
|
|
|
else if (flags & (RADEON_SURF_Z_OR_SBUFFER | RADEON_SURF_FMASK))
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
|
|
|
|
else
|
|
|
|
AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
|
|
|
|
|
2016-10-23 19:17:32 +01:00
|
|
|
AddrSurfInfoIn.flags.color = !(flags & RADEON_SURF_Z_OR_SBUFFER);
|
|
|
|
AddrSurfInfoIn.flags.depth = (flags & RADEON_SURF_ZBUFFER) != 0;
|
|
|
|
AddrSurfInfoIn.flags.cube = tex->target == PIPE_TEXTURE_CUBE;
|
2016-10-24 17:01:52 +01:00
|
|
|
AddrSurfInfoIn.flags.fmask = (flags & RADEON_SURF_FMASK) != 0;
|
2016-10-23 19:17:32 +01:00
|
|
|
AddrSurfInfoIn.flags.display = (flags & RADEON_SURF_SCANOUT) != 0;
|
|
|
|
AddrSurfInfoIn.flags.pow2Pad = tex->last_level > 0;
|
|
|
|
AddrSurfInfoIn.flags.tcCompatible = (flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
|
2016-10-11 22:19:46 +01:00
|
|
|
|
|
|
|
/* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
|
|
|
|
* requested, because TC-compatible HTILE requires 2D tiling.
|
|
|
|
*/
|
2014-07-09 07:46:00 +01:00
|
|
|
AddrSurfInfoIn.flags.opt4Space = !AddrSurfInfoIn.flags.tcCompatible &&
|
|
|
|
!AddrSurfInfoIn.flags.fmask &&
|
|
|
|
tex->nr_samples <= 1 &&
|
|
|
|
(flags & RADEON_SURF_OPTIMIZE_FOR_SPACE);
|
2016-06-03 19:48:01 +01:00
|
|
|
|
|
|
|
/* DCC notes:
|
|
|
|
* - If we add MSAA support, keep in mind that CB can't decompress 8bpp
|
|
|
|
* with samples >= 4.
|
|
|
|
* - Mipmapped array textures have low performance (discovered by a closed
|
|
|
|
* driver team).
|
|
|
|
*/
|
2016-08-19 00:40:29 +01:00
|
|
|
AddrSurfInfoIn.flags.dccCompatible = ws->info.chip_class >= VI &&
|
2016-10-23 19:17:32 +01:00
|
|
|
!(flags & RADEON_SURF_Z_OR_SBUFFER) &&
|
|
|
|
!(flags & RADEON_SURF_DISABLE_DCC) &&
|
2016-06-03 19:40:30 +01:00
|
|
|
!compressed && AddrDccIn.numSamples <= 1 &&
|
2016-10-23 19:17:32 +01:00
|
|
|
((tex->array_size == 1 && tex->depth0 == 1) ||
|
|
|
|
tex->last_level == 0);
|
2015-04-16 18:41:33 +01:00
|
|
|
|
2016-10-23 19:17:32 +01:00
|
|
|
AddrSurfInfoIn.flags.noStencil = (flags & RADEON_SURF_SBUFFER) == 0;
|
2016-05-19 19:10:10 +01:00
|
|
|
AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
|
|
|
|
|
2016-07-01 15:18:34 +01:00
|
|
|
/* noStencil = 0 can result in a depth part that is incompatible with
|
|
|
|
* mipmapped texturing. So set noStencil = 1 when mipmaps are requested (in
|
|
|
|
* this case, we may end up setting stencil_adjusted).
|
|
|
|
*
|
|
|
|
* TODO: update addrlib to a newer version, remove this, and
|
|
|
|
* use flags.matchStencilTileCfg = 1 as an alternative fix.
|
2016-05-19 19:10:10 +01:00
|
|
|
*/
|
2016-10-23 19:17:32 +01:00
|
|
|
if (tex->last_level > 0)
|
2016-07-01 15:18:34 +01:00
|
|
|
AddrSurfInfoIn.flags.noStencil = 1;
|
2015-04-16 18:41:33 +01:00
|
|
|
|
|
|
|
/* Set preferred macrotile parameters. This is usually required
|
|
|
|
* for shared resources. This is for 2D tiling only. */
|
|
|
|
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
|
2016-10-23 12:08:46 +01:00
|
|
|
surf->u.legacy.bankw && surf->u.legacy.bankh &&
|
|
|
|
surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
|
2016-10-24 17:22:31 +01:00
|
|
|
assert(!(flags & RADEON_SURF_FMASK));
|
|
|
|
|
2015-04-16 18:41:33 +01:00
|
|
|
/* If any of these parameters are incorrect, the calculation
|
|
|
|
* will fail. */
|
2016-10-23 12:08:46 +01:00
|
|
|
AddrTileInfoIn.banks = surf->u.legacy.num_banks;
|
|
|
|
AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
|
|
|
|
AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
|
|
|
|
AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
|
|
|
|
AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
|
|
|
|
AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
|
2014-07-09 07:46:00 +01:00
|
|
|
AddrSurfInfoIn.flags.opt4Space = 0;
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
|
|
|
|
|
|
|
|
/* If AddrSurfInfoIn.pTileInfo is set, Addrlib doesn't set
|
|
|
|
* the tile index, because we are expected to know it if
|
|
|
|
* we know the other parameters.
|
|
|
|
*
|
|
|
|
* This is something that can easily be fixed in Addrlib.
|
|
|
|
* For now, just figure it out here.
|
|
|
|
* Note that only 2D_TILE_THIN1 is handled here.
|
|
|
|
*/
|
2016-10-23 19:17:32 +01:00
|
|
|
assert(!(flags & RADEON_SURF_Z_OR_SBUFFER));
|
2015-04-16 18:41:33 +01:00
|
|
|
assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
|
|
|
|
|
2016-08-19 00:40:29 +01:00
|
|
|
if (ws->info.chip_class == SI) {
|
|
|
|
if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
|
2016-10-23 19:17:32 +01:00
|
|
|
if (bpe == 2)
|
2016-08-19 00:40:29 +01:00
|
|
|
AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
|
|
|
|
else
|
|
|
|
AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
|
|
|
|
} else {
|
2016-10-23 19:17:32 +01:00
|
|
|
if (bpe == 1)
|
2016-08-19 00:40:29 +01:00
|
|
|
AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
|
2016-10-23 19:17:32 +01:00
|
|
|
else if (bpe == 2)
|
2016-08-19 00:40:29 +01:00
|
|
|
AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
|
2016-10-23 19:17:32 +01:00
|
|
|
else if (bpe == 4)
|
2016-08-19 00:40:29 +01:00
|
|
|
AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
|
|
|
|
else
|
|
|
|
AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
/* CIK - VI */
|
|
|
|
if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE)
|
|
|
|
AddrSurfInfoIn.tileIndex = 10; /* 2D displayable */
|
|
|
|
else
|
|
|
|
AddrSurfInfoIn.tileIndex = 14; /* 2D non-displayable */
|
2016-10-24 18:05:10 +01:00
|
|
|
|
|
|
|
/* Addrlib doesn't set this if tileIndex is forced like above. */
|
|
|
|
AddrSurfInfoOut.macroModeIndex = cik_get_macro_tile_index(surf);
|
2016-08-19 00:40:29 +01:00
|
|
|
}
|
2015-04-16 18:41:33 +01:00
|
|
|
}
|
|
|
|
|
2016-10-26 16:43:19 +01:00
|
|
|
surf->num_dcc_levels = 0;
|
2016-10-23 20:26:43 +01:00
|
|
|
surf->surf_size = 0;
|
2015-10-20 23:10:36 +01:00
|
|
|
surf->dcc_size = 0;
|
|
|
|
surf->dcc_alignment = 1;
|
2016-10-11 22:19:46 +01:00
|
|
|
surf->htile_size = 0;
|
|
|
|
surf->htile_alignment = 1;
|
2015-04-16 18:41:33 +01:00
|
|
|
|
|
|
|
/* Calculate texture layout information. */
|
2016-10-23 19:17:32 +01:00
|
|
|
for (level = 0; level <= tex->last_level; level++) {
|
2016-10-20 21:14:04 +01:00
|
|
|
r = gfx6_compute_level(ws, tex, surf, false, level, compressed,
|
|
|
|
&AddrSurfInfoIn, &AddrSurfInfoOut,
|
|
|
|
&AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
|
2015-04-16 18:41:33 +01:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
|
|
|
if (level == 0) {
|
2016-10-23 20:26:43 +01:00
|
|
|
surf->surf_alignment = AddrSurfInfoOut.baseAlign;
|
2016-10-23 12:08:46 +01:00
|
|
|
surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
|
2016-10-20 21:14:04 +01:00
|
|
|
gfx6_set_micro_tile_mode(surf, &ws->info);
|
2015-04-16 18:41:33 +01:00
|
|
|
|
|
|
|
/* For 2D modes only. */
|
|
|
|
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
|
2016-10-23 12:08:46 +01:00
|
|
|
surf->u.legacy.bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
|
|
|
|
surf->u.legacy.bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
|
|
|
|
surf->u.legacy.mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
|
|
|
|
surf->u.legacy.tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
|
|
|
surf->u.legacy.num_banks = AddrSurfInfoOut.pTileInfo->banks;
|
|
|
|
surf->u.legacy.macro_tile_index = AddrSurfInfoOut.macroModeIndex;
|
2016-04-26 17:30:07 +01:00
|
|
|
} else {
|
2016-10-23 12:08:46 +01:00
|
|
|
surf->u.legacy.macro_tile_index = 0;
|
2015-04-16 18:41:33 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Calculate texture layout information for stencil. */
|
2016-10-23 19:17:32 +01:00
|
|
|
if (flags & RADEON_SURF_SBUFFER) {
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoIn.bpp = 8;
|
2016-05-19 19:10:10 +01:00
|
|
|
AddrSurfInfoIn.flags.depth = 0;
|
|
|
|
AddrSurfInfoIn.flags.stencil = 1;
|
2016-10-11 22:19:46 +01:00
|
|
|
AddrSurfInfoIn.flags.tcCompatible = 0;
|
2015-04-16 18:41:33 +01:00
|
|
|
/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
|
2016-10-23 12:08:46 +01:00
|
|
|
AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
|
2015-04-16 18:41:33 +01:00
|
|
|
|
2016-10-23 19:17:32 +01:00
|
|
|
for (level = 0; level <= tex->last_level; level++) {
|
2016-10-20 21:14:04 +01:00
|
|
|
r = gfx6_compute_level(ws, tex, surf, true, level, compressed,
|
|
|
|
&AddrSurfInfoIn, &AddrSurfInfoOut,
|
|
|
|
&AddrDccIn, &AddrDccOut,
|
|
|
|
NULL, NULL);
|
2015-04-16 18:41:33 +01:00
|
|
|
if (r)
|
|
|
|
return r;
|
|
|
|
|
2016-06-30 19:04:54 +01:00
|
|
|
/* DB uses the depth pitch for both stencil and depth. */
|
2016-10-23 12:08:46 +01:00
|
|
|
if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
|
|
|
|
surf->u.legacy.stencil_adjusted = true;
|
2016-06-30 19:04:54 +01:00
|
|
|
|
2015-04-16 18:41:33 +01:00
|
|
|
if (level == 0) {
|
|
|
|
/* For 2D modes only. */
|
|
|
|
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
|
2016-10-23 12:08:46 +01:00
|
|
|
surf->u.legacy.stencil_tile_split =
|
2015-04-16 18:41:33 +01:00
|
|
|
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-06-03 19:48:01 +01:00
|
|
|
/* Recalculate the whole DCC miptree size including disabled levels.
|
|
|
|
* This is what addrlib does, but calling addrlib would be a lot more
|
|
|
|
* complicated.
|
|
|
|
*/
|
2016-10-23 19:17:32 +01:00
|
|
|
if (surf->dcc_size && tex->last_level > 0) {
|
2016-10-23 20:26:43 +01:00
|
|
|
surf->dcc_size = align64(surf->surf_size >> 8,
|
2016-06-03 19:48:01 +01:00
|
|
|
ws->info.pipe_interleave_bytes *
|
|
|
|
ws->info.num_tile_pipes);
|
|
|
|
}
|
|
|
|
|
2016-10-11 22:19:46 +01:00
|
|
|
/* Make sure HTILE covers the whole miptree, because the shader reads
|
|
|
|
* TC-compatible HTILE even for levels where it's disabled by DB.
|
|
|
|
*/
|
2016-10-23 19:17:32 +01:00
|
|
|
if (surf->htile_size && tex->last_level)
|
2016-10-11 22:19:46 +01:00
|
|
|
surf->htile_size *= 2;
|
|
|
|
|
2016-10-23 12:08:46 +01:00
|
|
|
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
|
2015-04-16 18:41:33 +01:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
void amdgpu_surface_init_functions(struct amdgpu_winsys *ws)
|
|
|
|
{
|
2016-10-20 21:14:04 +01:00
|
|
|
if (ws->info.chip_class >= GFX9)
|
|
|
|
ws->base.surface_init = NULL;
|
|
|
|
else
|
|
|
|
ws->base.surface_init = gfx6_surface_init;
|
2015-04-16 18:41:33 +01:00
|
|
|
}
|