KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.* 

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2016-10-23 13:08:46 +02:00
parent 641b79774a
commit ba2e7c68ce
20 changed files with 357 additions and 345 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

104
src/gallium/drivers/r600/evergreen_state.c
View File

@ -700,14 +700,14 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
unsigned char array_mode = 0, non_disp_tiling = 0;
unsigned height, depth, width;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks, fmask_bankh;
struct radeon_surf_level *surflevel;
struct legacy_surf_level *surflevel;
unsigned base_level, first_level, last_level;
unsigned dim, last_layer;
uint64_t va;
bool do_endian_swap = FALSE;
tile_split = tmp->surface.tile_split;
surflevel = tmp->surface.level;
tile_split = tmp->surface.u.legacy.tile_split;
surflevel = tmp->surface.u.legacy.level;
/* Texturing with separate depth and stencil. */
if (tmp->db_compatible) {
@ -726,8 +726,8 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
case PIPE_FORMAT_S8X24_UINT:
case PIPE_FORMAT_X32_S8X24_UINT:
params->pipe_format = PIPE_FORMAT_S8_UINT;
tile_split = tmp->surface.stencil_tile_split;
surflevel = tmp->surface.stencil_level;
tile_split = tmp->surface.u.legacy.stencil_tile_split;
surflevel = tmp->surface.u.legacy.stencil_level;
break;
default:;
}
@ -777,9 +777,9 @@ static int evergreen_fill_tex_resource_words(struct r600_context *rctx,
array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
break;
}
macro_aspect = tmp->surface.mtilea;
bankw = tmp->surface.bankw;
bankh = tmp->surface.bankh;
macro_aspect = tmp->surface.u.legacy.mtilea;
bankw = tmp->surface.u.legacy.bankw;
bankh = tmp->surface.u.legacy.bankh;
tile_split = eg_tile_split(tile_split);
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
@ -1092,7 +1092,7 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx,
bool blend_clamp = 0, blend_bypass = 0, do_endian_swap = FALSE;
int i;
color->offset = rtex->surface.level[level].offset;
color->offset = rtex->surface.u.legacy.level[level].offset;
color->view = S_028C6C_SLICE_START(first_layer) |
S_028C6C_SLICE_MAX(last_layer);
@ -1100,14 +1100,14 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx,
color->offset >>= 8;
color->dim = 0;
pitch = (rtex->surface.level[level].nblk_x) / 8 - 1;
slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
pitch = (rtex->surface.u.legacy.level[level].nblk_x) / 8 - 1;
slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
if (slice) {
slice = slice - 1;
}
color->info = 0;
switch (rtex->surface.level[level].mode) {
switch (rtex->surface.u.legacy.level[level].mode) {
default:
case RADEON_SURF_MODE_LINEAR_ALIGNED:
color->info = S_028C70_ARRAY_MODE(V_028C70_ARRAY_LINEAR_ALIGNED);
@ -1122,14 +1122,14 @@ static void evergreen_set_color_surface_common(struct r600_context *rctx,
non_disp_tiling = rtex->non_disp_tiling;
break;
}
tile_split = rtex->surface.tile_split;
macro_aspect = rtex->surface.mtilea;
bankw = rtex->surface.bankw;
bankh = rtex->surface.bankh;
tile_split = rtex->surface.u.legacy.tile_split;
macro_aspect = rtex->surface.u.legacy.mtilea;
bankw = rtex->surface.u.legacy.bankw;
bankh = rtex->surface.u.legacy.bankh;
if (rtex->fmask.size)
fmask_bankh = rtex->fmask.bank_height;
else
fmask_bankh = rtex->surface.bankh;
fmask_bankh = rtex->surface.u.legacy.bankh;
tile_split = eg_tile_split(tile_split);
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
@ -1316,7 +1316,7 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
struct r600_screen *rscreen = rctx->screen;
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
unsigned level = surf->base.u.tex.level;
struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
uint64_t offset;
unsigned format, array_mode;
unsigned macro_aspect, tile_split, bankh, bankw, nbanks;
@ -1326,9 +1326,9 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
assert(format != ~0);
offset = rtex->resource.gpu_address;
offset += rtex->surface.level[level].offset;
offset += rtex->surface.u.legacy.level[level].offset;
switch (rtex->surface.level[level].mode) {
switch (rtex->surface.u.legacy.level[level].mode) {
case RADEON_SURF_MODE_2D:
array_mode = V_028C70_ARRAY_2D_TILED_THIN1;
break;
@ -1338,10 +1338,10 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
array_mode = V_028C70_ARRAY_1D_TILED_THIN1;
break;
}
tile_split = rtex->surface.tile_split;
macro_aspect = rtex->surface.mtilea;
bankw = rtex->surface.bankw;
bankh = rtex->surface.bankh;
tile_split = rtex->surface.u.legacy.tile_split;
macro_aspect = rtex->surface.u.legacy.mtilea;
bankw = rtex->surface.u.legacy.bankw;
bankh = rtex->surface.u.legacy.bankh;
tile_split = eg_tile_split(tile_split);
macro_aspect = eg_macro_tile_aspect(macro_aspect);
bankw = eg_bank_wh(bankw);
@ -1372,11 +1372,11 @@ static void evergreen_init_depth_surface(struct r600_context *rctx,
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
uint64_t stencil_offset;
unsigned stile_split = rtex->surface.stencil_tile_split;
unsigned stile_split = rtex->surface.u.legacy.stencil_tile_split;
stile_split = eg_tile_split(stile_split);
stencil_offset = rtex->surface.stencil_level[level].offset;
stencil_offset = rtex->surface.u.legacy.stencil_level[level].offset;
stencil_offset += rtex->resource.gpu_address;
surf->db_stencil_base = stencil_offset >> 8;
@ -3506,8 +3506,8 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
unsigned sub_cmd, bank_h, bank_w, mt_aspect, nbanks, tile_split, non_disp_tiling = 0;
uint64_t base, addr;
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
src_mode = rsrc->surface.u.legacy.level[src_level].mode;
assert(dst_mode != src_mode);
/* non_disp_tiling bit needs to be set for depth, stencil, and fmask surfaces */
@ -3523,7 +3523,7 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
/* T2L */
array_mode = evergreen_array_mode(src_mode);
slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
@ -3535,20 +3535,20 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
x = src_x;
y = src_y;
z = src_z;
base = rsrc->surface.level[src_level].offset;
addr = rdst->surface.level[dst_level].offset;
addr += rdst->surface.level[dst_level].slice_size * dst_z;
base = rsrc->surface.u.legacy.level[src_level].offset;
addr = rdst->surface.u.legacy.level[dst_level].offset;
addr += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
addr += dst_y * pitch + dst_x * bpp;
bank_h = eg_bank_wh(rsrc->surface.bankh);
bank_w = eg_bank_wh(rsrc->surface.bankw);
mt_aspect = eg_macro_tile_aspect(rsrc->surface.mtilea);
tile_split = eg_tile_split(rsrc->surface.tile_split);
bank_h = eg_bank_wh(rsrc->surface.u.legacy.bankh);
bank_w = eg_bank_wh(rsrc->surface.u.legacy.bankw);
mt_aspect = eg_macro_tile_aspect(rsrc->surface.u.legacy.mtilea);
tile_split = eg_tile_split(rsrc->surface.u.legacy.tile_split);
base += rsrc->resource.gpu_address;
addr += rdst->resource.gpu_address;
} else {
/* L2T */
array_mode = evergreen_array_mode(dst_mode);
slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
@ -3560,14 +3560,14 @@ static void evergreen_dma_copy_tile(struct r600_context *rctx,
x = dst_x;
y = dst_y;
z = dst_z;
base = rdst->surface.level[dst_level].offset;
addr = rsrc->surface.level[src_level].offset;
addr += rsrc->surface.level[src_level].slice_size * src_z;
base = rdst->surface.u.legacy.level[dst_level].offset;
addr = rsrc->surface.u.legacy.level[src_level].offset;
addr += rsrc->surface.u.legacy.level[src_level].slice_size * src_z;
addr += src_y * pitch + src_x * bpp;
bank_h = eg_bank_wh(rdst->surface.bankh);
bank_w = eg_bank_wh(rdst->surface.bankw);
mt_aspect = eg_macro_tile_aspect(rdst->surface.mtilea);
tile_split = eg_tile_split(rdst->surface.tile_split);
bank_h = eg_bank_wh(rdst->surface.u.legacy.bankh);
bank_w = eg_bank_wh(rdst->surface.u.legacy.bankw);
mt_aspect = eg_macro_tile_aspect(rdst->surface.u.legacy.mtilea);
tile_split = eg_tile_split(rdst->surface.u.legacy.tile_split);
base += rdst->resource.gpu_address;
addr += rsrc->resource.gpu_address;
}
@ -3640,14 +3640,14 @@ static void evergreen_dma_copy(struct pipe_context *ctx,
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
src_mode = rsrc->surface.u.legacy.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
/* FIXME evergreen can do partial blit */
@ -3678,11 +3678,11 @@ static void evergreen_dma_copy(struct pipe_context *ctx,
* dst_x/y == 0
* dst_pitch == src_pitch
*/
src_offset= rsrc->surface.level[src_level].offset;
src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
src_offset= rsrc->surface.u.legacy.level[src_level].offset;
src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
dst_offset = rdst->surface.level[dst_level].offset;
dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
evergreen_dma_copy_buffer(rctx, dst, src, dst_offset, src_offset,
src_box->height * src_pitch);

4
src/gallium/drivers/r600/r600_blit.c
View File

@ -792,7 +792,7 @@ static bool do_hardware_msaa_resolve(struct pipe_context *ctx,
info->src.box.width == dst_width &&
info->src.box.height == dst_height &&
info->src.box.depth == 1 &&
dst->surface.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
dst->surface.u.legacy.level[info->dst.level].mode >= RADEON_SURF_MODE_1D &&
(!dst->cmask.size || !dst->dirty_level_mask) /* dst cannot be fast-cleared */) {
r600_blitter_begin(ctx, R600_COLOR_RESOLVE |
(info->render_condition_enable ? 0 : R600_DISABLE_RENDER_COND));
@ -862,7 +862,7 @@ static void r600_blit(struct pipe_context *ctx,
* resource_copy_region can't do this yet, because dma_copy calls it
* on failure (recursion).
*/
if (rdst->surface.level[info->dst.level].mode ==
if (rdst->surface.u.legacy.level[info->dst.level].mode ==
RADEON_SURF_MODE_LINEAR_ALIGNED &&
rctx->b.dma_copy &&
util_can_blit_via_copy_region(info, false)) {

64
src/gallium/drivers/r600/r600_state.c
View File

@ -723,7 +723,7 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
width = width_first_level;
height = height_first_level;
depth = u_minify(texture->depth0, offset_level);
pitch = tmp->surface.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
pitch = tmp->surface.u.legacy.level[offset_level].nblk_x * util_format_get_blockwidth(state->format);
if (texture->target == PIPE_TEXTURE_1D_ARRAY) {
height = 1;
@ -733,7 +733,7 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
} else if (texture->target == PIPE_TEXTURE_CUBE_ARRAY)
depth = texture->array_size / 6;
switch (tmp->surface.level[offset_level].mode) {
switch (tmp->surface.u.legacy.level[offset_level].mode) {
default:
case RADEON_SURF_MODE_LINEAR_ALIGNED:
array_mode = V_038000_ARRAY_LINEAR_ALIGNED;
@ -755,11 +755,11 @@ r600_create_sampler_view_custom(struct pipe_context *ctx,
view->tex_resource_words[1] = (S_038004_TEX_HEIGHT(height - 1) |
S_038004_TEX_DEPTH(depth - 1) |
S_038004_DATA_FORMAT(format));
view->tex_resource_words[2] = tmp->surface.level[offset_level].offset >> 8;
view->tex_resource_words[2] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
if (offset_level >= tmp->resource.b.b.last_level) {
view->tex_resource_words[3] = tmp->surface.level[offset_level].offset >> 8;
view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level].offset >> 8;
} else {
view->tex_resource_words[3] = tmp->surface.level[offset_level + 1].offset >> 8;
view->tex_resource_words[3] = tmp->surface.u.legacy.level[offset_level + 1].offset >> 8;
}
view->tex_resource_words[4] = (word4 |
S_038010_REQUEST_SIZE(1) |
@ -824,17 +824,17 @@ static void r600_init_color_surface(struct r600_context *rctx,
assert(rtex);
}
offset = rtex->surface.level[level].offset;
offset = rtex->surface.u.legacy.level[level].offset;
color_view = S_028080_SLICE_START(surf->base.u.tex.first_layer) |
S_028080_SLICE_MAX(surf->base.u.tex.last_layer);
pitch = rtex->surface.level[level].nblk_x / 8 - 1;
slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
if (slice) {
slice = slice - 1;
}
color_info = 0;
switch (rtex->surface.level[level].mode) {
switch (rtex->surface.u.legacy.level[level].mode) {
default:
case RADEON_SURF_MODE_LINEAR_ALIGNED:
color_info = S_0280A0_ARRAY_MODE(V_038000_ARRAY_LINEAR_ALIGNED);
@ -1032,13 +1032,13 @@ static void r600_init_depth_surface(struct r600_context *rctx,
unsigned level, pitch, slice, format, offset, array_mode;
level = surf->base.u.tex.level;
offset = rtex->surface.level[level].offset;
pitch = rtex->surface.level[level].nblk_x / 8 - 1;
slice = (rtex->surface.level[level].nblk_x * rtex->surface.level[level].nblk_y) / 64;
offset = rtex->surface.u.legacy.level[level].offset;
pitch = rtex->surface.u.legacy.level[level].nblk_x / 8 - 1;
slice = (rtex->surface.u.legacy.level[level].nblk_x * rtex->surface.u.legacy.level[level].nblk_y) / 64;
if (slice) {
slice = slice - 1;
}
switch (rtex->surface.level[level].mode) {
switch (rtex->surface.u.legacy.level[level].mode) {
case RADEON_SURF_MODE_2D:
array_mode = V_0280A0_ARRAY_2D_TILED_THIN1;
break;
@ -1057,7 +1057,7 @@ static void r600_init_depth_surface(struct r600_context *rctx,
surf->db_depth_view = S_028004_SLICE_START(surf->base.u.tex.first_layer) |
S_028004_SLICE_MAX(surf->base.u.tex.last_layer);
surf->db_depth_size = S_028000_PITCH_TILE_MAX(pitch) | S_028000_SLICE_TILE_MAX(slice);
surf->db_prefetch_limit = (rtex->surface.level[level].nblk_y / 8) - 1;
surf->db_prefetch_limit = (rtex->surface.u.legacy.level[level].nblk_y / 8) - 1;
/* use htile only for first level */
if (rtex->htile_buffer && !level) {
@ -2834,8 +2834,8 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
unsigned ncopy, height, cheight, detile, i, x, y, z, src_mode, dst_mode;
uint64_t base, addr;
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
src_mode = rsrc->surface.u.legacy.level[src_level].mode;
assert(dst_mode != src_mode);
y = 0;
@ -2845,7 +2845,7 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
if (dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED) {
/* T2L */
array_mode = r600_array_mode(src_mode);
slice_tile_max = (rsrc->surface.level[src_level].nblk_x * rsrc->surface.level[src_level].nblk_y) / (8*8);
slice_tile_max = (rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.u.legacy.level[src_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
@ -2857,14 +2857,14 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
x = src_x;
y = src_y;
z = src_z;
base = rsrc->surface.level[src_level].offset;
addr = rdst->surface.level[dst_level].offset;
addr += rdst->surface.level[dst_level].slice_size * dst_z;
base = rsrc->surface.u.legacy.level[src_level].offset;
addr = rdst->surface.u.legacy.level[dst_level].offset;
addr += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
addr += dst_y * pitch + dst_x * bpp;
} else {
/* L2T */
array_mode = r600_array_mode(dst_mode);
slice_tile_max = (rdst->surface.level[dst_level].nblk_x * rdst->surface.level[dst_level].nblk_y) / (8*8);
slice_tile_max = (rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.u.legacy.level[dst_level].nblk_y) / (8*8);
slice_tile_max = slice_tile_max ? slice_tile_max - 1 : 0;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
@ -2876,9 +2876,9 @@ static boolean r600_dma_copy_tile(struct r600_context *rctx,
x = dst_x;
y = dst_y;
z = dst_z;
base = rdst->surface.level[dst_level].offset;
addr = rsrc->surface.level[src_level].offset;
addr += rsrc->surface.level[src_level].slice_size * src_z;
base = rdst->surface.u.legacy.level[dst_level].offset;
addr = rsrc->surface.u.legacy.level[src_level].offset;
addr += rsrc->surface.u.legacy.level[src_level].slice_size * src_z;
addr += src_y * pitch + src_x * bpp;
}
/* check that we are in dw/base alignment constraint */
@ -2956,14 +2956,14 @@ static void r600_dma_copy(struct pipe_context *ctx,
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
copy_height = src_box->height / rsrc->surface.blk_h;
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
src_mode = rsrc->surface.u.legacy.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w) {
/* strict requirement on r6xx/r7xx */
@ -2982,11 +2982,11 @@ static void r600_dma_copy(struct pipe_context *ctx,
* dst_x/y == 0
* dst_pitch == src_pitch
*/
src_offset= rsrc->surface.level[src_level].offset;
src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
src_offset= rsrc->surface.u.legacy.level[src_level].offset;
src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
dst_offset = rdst->surface.level[dst_level].offset;
dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
size = src_box->height * src_pitch;
/* must be dw aligned */

4
src/gallium/drivers/radeon/r600_test_dma.c
View File

@ -277,9 +277,9 @@ void r600_test_dma(struct r600_common_screen *rscreen)
printf("%4u: dst = (%5u x %5u x %u, %s), "
" src = (%5u x %5u x %u, %s), bpp = %2u, ",
i, tdst.width0, tdst.height0, tdst.array_size,
array_mode_to_string(rdst->surface.level[0].mode),
array_mode_to_string(rdst->surface.u.legacy.level[0].mode),
tsrc.width0, tsrc.height0, tsrc.array_size,
array_mode_to_string(rsrc->surface.level[0].mode), bpp);
array_mode_to_string(rsrc->surface.u.legacy.level[0].mode), bpp);
fflush(stdout);
/* set src pixels */

156
src/gallium/drivers/radeon/r600_texture.c
View File

@ -180,10 +180,10 @@ static void r600_copy_from_staging_texture(struct pipe_context *ctx, struct r600
static unsigned r600_texture_get_offset(struct r600_texture *rtex, unsigned level,
const struct pipe_box *box)
{
return rtex->surface.level[level].offset +
box->z * rtex->surface.level[level].slice_size +
return rtex->surface.u.legacy.level[level].offset +
box->z * rtex->surface.u.legacy.level[level].slice_size +
(box->y / rtex->surface.blk_h *
rtex->surface.level[level].nblk_x +
rtex->surface.u.legacy.level[level].nblk_x +
box->x / rtex->surface.blk_w) * rtex->surface.bpe;
}
@ -266,17 +266,17 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
}
if (pitch_in_bytes_override &&
pitch_in_bytes_override != surface->level[0].nblk_x * bpe) {
pitch_in_bytes_override != surface->u.legacy.level[0].nblk_x * bpe) {
/* old ddx on evergreen over estimate alignment for 1d, only 1 level
* for those
*/
surface->level[0].nblk_x = pitch_in_bytes_override / bpe;
surface->level[0].slice_size = pitch_in_bytes_override * surface->level[0].nblk_y;
surface->u.legacy.level[0].nblk_x = pitch_in_bytes_override / bpe;
surface->u.legacy.level[0].slice_size = pitch_in_bytes_override * surface->u.legacy.level[0].nblk_y;
}
if (offset) {
for (i = 0; i < ARRAY_SIZE(surface->level); ++i)
surface->level[i].offset += offset;
for (i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
surface->u.legacy.level[i].offset += offset;
}
return 0;
}
@ -287,17 +287,17 @@ static void r600_texture_init_metadata(struct r600_texture *rtex,
struct radeon_surf *surface = &rtex->surface;
memset(metadata, 0, sizeof(*metadata));
metadata->microtile = surface->level[0].mode >= RADEON_SURF_MODE_1D ?
metadata->microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
metadata->macrotile = surface->level[0].mode >= RADEON_SURF_MODE_2D ?
metadata->macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
metadata->pipe_config = surface->pipe_config;
metadata->bankw = surface->bankw;
metadata->bankh = surface->bankh;
metadata->tile_split = surface->tile_split;
metadata->mtilea = surface->mtilea;
metadata->num_banks = surface->num_banks;
metadata->stride = surface->level[0].nblk_x * surface->bpe;
metadata->pipe_config = surface->u.legacy.pipe_config;
metadata->bankw = surface->u.legacy.bankw;
metadata->bankh = surface->u.legacy.bankh;
metadata->tile_split = surface->u.legacy.tile_split;
metadata->mtilea = surface->u.legacy.mtilea;
metadata->num_banks = surface->u.legacy.num_banks;
metadata->stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
metadata->scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
}
@ -548,10 +548,10 @@ static boolean r600_texture_get_handle(struct pipe_screen* screen,
}
return rscreen->ws->buffer_get_handle(res->buf,
rtex->surface.level[0].nblk_x *
rtex->surface.u.legacy.level[0].nblk_x *
rtex->surface.bpe,
rtex->surface.level[0].offset,
rtex->surface.level[0].slice_size,
rtex->surface.u.legacy.level[0].offset,
rtex->surface.u.legacy.level[0].slice_size,
whandle);
}
@ -593,13 +593,13 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
if (rscreen->chip_class <= CAYMAN) {
/* Use the same parameters and tile mode. */
fmask.bankw = rtex->surface.bankw;
fmask.bankh = rtex->surface.bankh;
fmask.mtilea = rtex->surface.mtilea;
fmask.tile_split = rtex->surface.tile_split;
fmask.u.legacy.bankw = rtex->surface.u.legacy.bankw;
fmask.u.legacy.bankh = rtex->surface.u.legacy.bankh;
fmask.u.legacy.mtilea = rtex->surface.u.legacy.mtilea;
fmask.u.legacy.tile_split = rtex->surface.u.legacy.tile_split;
if (nr_samples <= 4)
fmask.bankh = 4;
fmask.u.legacy.bankh = 4;
}
switch (nr_samples) {
@ -628,15 +628,15 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
return;
}
assert(fmask.level[0].mode == RADEON_SURF_MODE_2D);
assert(fmask.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
out->slice_tile_max = (fmask.level[0].nblk_x * fmask.level[0].nblk_y) / 64;
out->slice_tile_max = (fmask.u.legacy.level[0].nblk_x * fmask.u.legacy.level[0].nblk_y) / 64;
if (out->slice_tile_max)
out->slice_tile_max -= 1;
out->tile_mode_index = fmask.tiling_index[0];
out->pitch_in_pixels = fmask.level[0].nblk_x;
out->bank_height = fmask.bankh;
out->tile_mode_index = fmask.u.legacy.tiling_index[0];
out->pitch_in_pixels = fmask.u.legacy.level[0].nblk_x;
out->bank_height = fmask.u.legacy.bankh;
out->alignment = MAX2(256, fmask.surf_alignment);
out->size = fmask.surf_size;
}
@ -808,7 +808,7 @@ static void r600_texture_get_htile_size(struct r600_common_screen *rscreen,
/* HTILE is broken with 1D tiling on old kernels and CIK. */
if (rscreen->chip_class >= CIK &&
rtex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
rscreen->info.drm_major == 2 && rscreen->info.drm_minor < 38)
return;
@ -911,9 +911,9 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
fprintf(f, " Layout: size=%"PRIu64", alignment=%u, bankw=%u, "
"bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.bankw,
rtex->surface.bankh, rtex->surface.num_banks, rtex->surface.mtilea,
rtex->surface.tile_split, rtex->surface.pipe_config,
rtex->surface.surf_size, rtex->surface.surf_alignment, rtex->surface.u.legacy.bankw,
rtex->surface.u.legacy.bankh, rtex->surface.u.legacy.num_banks, rtex->surface.u.legacy.mtilea,
rtex->surface.u.legacy.tile_split, rtex->surface.u.legacy.pipe_config,
(rtex->surface.flags & RADEON_SURF_SCANOUT) != 0);
if (rtex->fmask.size)
@ -943,41 +943,41 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
fprintf(f, " DCCLevel[%i]: enabled=%u, offset=%"PRIu64", "
"fast_clear_size=%"PRIu64"\n",
i, i < rtex->surface.num_dcc_levels,
rtex->surface.level[i].dcc_offset,
rtex->surface.level[i].dcc_fast_clear_size);
rtex->surface.u.legacy.level[i].dcc_offset,
rtex->surface.u.legacy.level[i].dcc_fast_clear_size);
}
for (i = 0; i <= rtex->resource.b.b.last_level; i++)
fprintf(f, " Level[%i]: offset=%"PRIu64", slice_size=%"PRIu64", "
"npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
"mode=%u, tiling_index = %u\n",
i, rtex->surface.level[i].offset,
rtex->surface.level[i].slice_size,
i, rtex->surface.u.legacy.level[i].offset,
rtex->surface.u.legacy.level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.height0, i),
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.level[i].nblk_x,
rtex->surface.level[i].nblk_y,
rtex->surface.level[i].mode,
rtex->surface.tiling_index[i]);
rtex->surface.u.legacy.level[i].nblk_x,
rtex->surface.u.legacy.level[i].nblk_y,
rtex->surface.u.legacy.level[i].mode,
rtex->surface.u.legacy.tiling_index[i]);
if (rtex->surface.flags & RADEON_SURF_SBUFFER) {
fprintf(f, " StencilLayout: tilesplit=%u\n",
rtex->surface.stencil_tile_split);
rtex->surface.u.legacy.stencil_tile_split);
for (i = 0; i <= rtex->resource.b.b.last_level; i++) {
fprintf(f, " StencilLevel[%i]: offset=%"PRIu64", "
"slice_size=%"PRIu64", npix_x=%u, "
"npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
"mode=%u, tiling_index = %u\n",
i, rtex->surface.stencil_level[i].offset,
rtex->surface.stencil_level[i].slice_size,
i, rtex->surface.u.legacy.stencil_level[i].offset,
rtex->surface.u.legacy.stencil_level[i].slice_size,
u_minify(rtex->resource.b.b.width0, i),
u_minify(rtex->resource.b.b.height0, i),
u_minify(rtex->resource.b.b.depth0, i),
rtex->surface.stencil_level[i].nblk_x,
rtex->surface.stencil_level[i].nblk_y,
rtex->surface.stencil_level[i].mode,
rtex->surface.stencil_tiling_index[i]);
rtex->surface.u.legacy.stencil_level[i].nblk_x,
rtex->surface.u.legacy.stencil_level[i].nblk_y,
rtex->surface.u.legacy.stencil_level[i].mode,
rtex->surface.u.legacy.stencil_tiling_index[i]);
}
}
}
@ -1030,7 +1030,7 @@ r600_texture_create_object(struct pipe_screen *screen,
/* Tiled depth textures utilize the non-displayable tile order.
* This must be done after r600_setup_surface.
* Applies to R600-Cayman. */
rtex->non_disp_tiling = rtex->is_depth && rtex->surface.level[0].mode >= RADEON_SURF_MODE_1D;
rtex->non_disp_tiling = rtex->is_depth && rtex->surface.u.legacy.level[0].mode >= RADEON_SURF_MODE_1D;
/* Applies to GCN. */
rtex->last_msaa_resolve_target_micro_mode = rtex->surface.micro_tile_mode;
@ -1044,8 +1044,8 @@ r600_texture_create_object(struct pipe_screen *screen,
if (base->flags & (R600_RESOURCE_FLAG_TRANSFER |
R600_RESOURCE_FLAG_FLUSHED_DEPTH) ||
rscreen->chip_class >= EVERGREEN) {
rtex->can_sample_z = !rtex->surface.depth_adjusted;
rtex->can_sample_s = !rtex->surface.stencil_adjusted;
rtex->can_sample_z = !rtex->surface.u.legacy.depth_adjusted;
rtex->can_sample_s = !rtex->surface.u.legacy.stencil_adjusted;
} else {
if (rtex->resource.b.b.nr_samples <= 1 &&
(rtex->resource.b.b.format == PIPE_FORMAT_Z16_UNORM ||
@ -1265,12 +1265,12 @@ static struct pipe_resource *r600_texture_from_handle(struct pipe_screen *screen
rscreen->ws->buffer_get_metadata(buf, &metadata);
surface.pipe_config = metadata.pipe_config;
surface.bankw = metadata.bankw;
surface.bankh = metadata.bankh;
surface.tile_split = metadata.tile_split;
surface.mtilea = metadata.mtilea;
surface.num_banks = metadata.num_banks;
surface.u.legacy.pipe_config = metadata.pipe_config;
surface.u.legacy.bankw = metadata.bankw;
surface.u.legacy.bankh = metadata.bankh;
surface.u.legacy.tile_split = metadata.tile_split;
surface.u.legacy.mtilea = metadata.mtilea;
surface.u.legacy.num_banks = metadata.num_banks;
if (metadata.macrotile == RADEON_LAYOUT_TILED)
array_mode = RADEON_SURF_MODE_2D;
@ -1560,9 +1560,9 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
offset = r600_texture_get_offset(staging_depth, level, box);
}
trans->transfer.stride = staging_depth->surface.level[level].nblk_x *
trans->transfer.stride = staging_depth->surface.u.legacy.level[level].nblk_x *
staging_depth->surface.bpe;
trans->transfer.layer_stride = staging_depth->surface.level[level].slice_size;
trans->transfer.layer_stride = staging_depth->surface.u.legacy.level[level].slice_size;
trans->staging = (struct r600_resource*)staging_depth;
buf = trans->staging;
} else if (use_staging_texture) {
@ -1582,9 +1582,9 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
return NULL;
}
trans->staging = &staging->resource;
trans->transfer.stride = staging->surface.level[0].nblk_x *
trans->transfer.stride = staging->surface.u.legacy.level[0].nblk_x *
staging->surface.bpe;
trans->transfer.layer_stride = staging->surface.level[0].slice_size;
trans->transfer.layer_stride = staging->surface.u.legacy.level[0].slice_size;
if (usage & PIPE_TRANSFER_READ)
r600_copy_to_staging_texture(ctx, trans);
@ -1594,9 +1594,9 @@ static void *r600_texture_transfer_map(struct pipe_context *ctx,
buf = trans->staging;
} else {
/* the resource is mapped directly */
trans->transfer.stride = rtex->surface.level[level].nblk_x *
trans->transfer.stride = rtex->surface.u.legacy.level[level].nblk_x *
rtex->surface.bpe;
trans->transfer.layer_stride = rtex->surface.level[level].slice_size;
trans->transfer.layer_stride = rtex->surface.u.legacy.level[level].slice_size;
offset = r600_texture_get_offset(rtex, level, box);
buf = &rtex->resource;
}
@ -2334,10 +2334,10 @@ void vi_dcc_clear_level(struct r600_common_context *rctx,
dcc_offset = rtex->dcc_offset;
}
dcc_offset += rtex->surface.level[level].dcc_offset;
dcc_offset += rtex->surface.u.legacy.level[level].dcc_offset;
rctx->clear_buffer(&rctx->b, dcc_buffer, dcc_offset,
rtex->surface.level[level].dcc_fast_clear_size,
rtex->surface.u.legacy.level[level].dcc_fast_clear_size,
clear_value, R600_COHERENCY_CB_META);
}
@ -2353,7 +2353,7 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
rtex->surface.micro_tile_mode == rtex->last_msaa_resolve_target_micro_mode)
return;
assert(rtex->surface.level[0].mode == RADEON_SURF_MODE_2D);
assert(rtex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_2D);
assert(rtex->resource.b.b.last_level == 0);
/* These magic numbers were copied from addrlib. It doesn't use any
@ -2363,13 +2363,13 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
if (rscreen->chip_class >= CIK) {
switch (rtex->last_msaa_resolve_target_micro_mode) {
case RADEON_MICRO_MODE_DISPLAY:
rtex->surface.tiling_index[0] = 10;
rtex->surface.u.legacy.tiling_index[0] = 10;
break;
case RADEON_MICRO_MODE_THIN:
rtex->surface.tiling_index[0] = 14;
rtex->surface.u.legacy.tiling_index[0] = 14;
break;
case RADEON_MICRO_MODE_ROTATED:
rtex->surface.tiling_index[0] = 28;
rtex->surface.u.legacy.tiling_index[0] = 28;
break;
default: /* depth, thick */
assert(!"unexpected micro mode");
@ -2380,29 +2380,29 @@ static void si_set_optimal_micro_tile_mode(struct r600_common_screen *rscreen,
case RADEON_MICRO_MODE_DISPLAY:
switch (rtex->surface.bpe) {
case 1:
rtex->surface.tiling_index[0] = 10;
rtex->surface.u.legacy.tiling_index[0] = 10;
break;
case 2:
rtex->surface.tiling_index[0] = 11;
rtex->surface.u.legacy.tiling_index[0] = 11;
break;
default: /* 4, 8 */
rtex->surface.tiling_index[0] = 12;
rtex->surface.u.legacy.tiling_index[0] = 12;
break;
}
break;
case RADEON_MICRO_MODE_THIN:
switch (rtex->surface.bpe) {
case 1:
rtex->surface.tiling_index[0] = 14;
rtex->surface.u.legacy.tiling_index[0] = 14;
break;
case 2:
rtex->surface.tiling_index[0] = 15;
rtex->surface.u.legacy.tiling_index[0] = 15;
break;
case 4:
rtex->surface.tiling_index[0] = 16;
rtex->surface.u.legacy.tiling_index[0] = 16;
break;
default: /* 8, 16 */
rtex->surface.tiling_index[0] = 17;
rtex->surface.u.legacy.tiling_index[0] = 17;
break;
}
break;
@ -2472,7 +2472,7 @@ void evergreen_do_fast_color_clear(struct r600_common_context *rctx,
/* fast color clear with 1D tiling doesn't work on old kernels and CIK */
if (rctx->chip_class == CIK &&
tex->surface.level[0].mode == RADEON_SURF_MODE_1D &&
tex->surface.u.legacy.level[0].mode == RADEON_SURF_MODE_1D &&
rctx->screen->info.drm_major == 2 &&
rctx->screen->info.drm_minor < 38) {
continue;

20
src/gallium/drivers/radeon/radeon_uvd.c
View File

@ -1321,8 +1321,8 @@ error:
/* calculate top/bottom offset */
static unsigned texture_offset(struct radeon_surf *surface, unsigned layer)
{
return surface->level[0].offset +
layer * surface->level[0].slice_size;
return surface->u.legacy.level[0].offset +
layer * surface->u.legacy.level[0].slice_size;
}
/* hw encode the aspect of macro tiles */
@ -1357,8 +1357,8 @@ static unsigned bank_wh(unsigned bankwh)
void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
struct radeon_surf *chroma)
{
msg->body.decode.dt_pitch = luma->level[0].nblk_x;
switch (luma->level[0].mode) {
msg->body.decode.dt_pitch = luma->u.legacy.level[0].nblk_x;
switch (luma->u.legacy.level[0].mode) {
case RADEON_SURF_MODE_LINEAR_ALIGNED:
msg->body.decode.dt_tiling_mode = RUVD_TILE_LINEAR;
msg->body.decode.dt_array_mode = RUVD_ARRAY_MODE_LINEAR;
@ -1386,11 +1386,11 @@ void ruvd_set_dt_surfaces(struct ruvd_msg *msg, struct radeon_surf *luma,
msg->body.decode.dt_chroma_bottom_offset = msg->body.decode.dt_chroma_top_offset;
}
assert(luma->bankw == chroma->bankw);
assert(luma->bankh == chroma->bankh);
assert(luma->mtilea == chroma->mtilea);
assert(luma->u.legacy.bankw == chroma->u.legacy.bankw);
assert(luma->u.legacy.bankh == chroma->u.legacy.bankh);
assert(luma->u.legacy.mtilea == chroma->u.legacy.mtilea);
msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->bankw));
msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->bankh));
msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->mtilea));
msg->body.decode.dt_surf_tile_config |= RUVD_BANK_WIDTH(bank_wh(luma->u.legacy.bankw));
msg->body.decode.dt_surf_tile_config |= RUVD_BANK_HEIGHT(bank_wh(luma->u.legacy.bankh));
msg->body.decode.dt_surf_tile_config |= RUVD_MACRO_TILE_ASPECT_RATIO(macro_tile_aspect(luma->u.legacy.mtilea));
}

8
src/gallium/drivers/radeon/radeon_vce.c
View File

@ -224,8 +224,8 @@ struct rvce_cpb_slot *l1_slot(struct rvce_encoder *enc)
void rvce_frame_offset(struct rvce_encoder *enc, struct rvce_cpb_slot *slot,
signed *luma_offset, signed *chroma_offset)
{
unsigned pitch = align(enc->luma->level[0].nblk_x * enc->luma->bpe, 128);
unsigned vpitch = align(enc->luma->level[0].nblk_y, 16);
unsigned pitch = align(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe, 128);
unsigned vpitch = align(enc->luma->u.legacy.level[0].nblk_y, 16);
unsigned fsize = pitch * (vpitch + vpitch / 2);
*luma_offset = slot->index * fsize;
@ -456,8 +456,8 @@ struct pipe_video_codec *rvce_create_encoder(struct pipe_context *context,
goto error;
get_buffer(((struct vl_video_buffer *)tmp_buf)->resources[0], NULL, &tmp_surf);
cpb_size = align(tmp_surf->level[0].nblk_x * tmp_surf->bpe, 128);
cpb_size = cpb_size * align(tmp_surf->level[0].nblk_y, 32);
cpb_size = align(tmp_surf->u.legacy.level[0].nblk_x * tmp_surf->bpe, 128);
cpb_size = cpb_size * align(tmp_surf->u.legacy.level[0].nblk_y, 32);
cpb_size = cpb_size * 3 / 2;
cpb_size = cpb_size * enc->cpb_num;
if (enc->dual_pipe)

16
src/gallium/drivers/radeon/radeon_vce_40_2_2.c
View File

@ -94,9 +94,9 @@ static void create(struct rvce_encoder *enc)
RVCE_CS(0x00000000); // encPicStructRestriction
RVCE_CS(enc->base.width); // encImageWidth
RVCE_CS(enc->base.height); // encImageHeight
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(0x00000000); // encRefPic(Addr|Array)Mode, encPicStructRestriction, disableRDO
RVCE_END();
}
@ -320,12 +320,12 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(0x00000000); // endOfSequence
RVCE_CS(0x00000000); // endOfStream
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode
RVCE_CS(0x00000000); // encInputPicTileConfig
RVCE_CS(enc->pic.picture_type); // encPicType

10
src/gallium/drivers/radeon/radeon_vce_50.c
View File

@ -127,12 +127,12 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(0x00000000); // endOfSequence
RVCE_CS(0x00000000); // endOfStream
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
if (enc->dual_pipe)
RVCE_CS(0x00000000); // encInputPic(Addr|Array)Mode,encDisable(TwoPipeMode|MBOffloading)
else

16
src/gallium/drivers/radeon/radeon_vce_52.c
View File

@ -177,9 +177,9 @@ static void create(struct rvce_encoder *enc)
RVCE_CS(enc->enc_pic.ec.enc_pic_struct_restriction);
RVCE_CS(enc->base.width); // encImageWidth
RVCE_CS(enc->base.height); // encImageHeight
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
RVCE_CS(align(enc->luma->level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encRefPicLumaPitch
RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encRefPicChromaPitch
RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16) / 8); // encRefYHeightInQw
RVCE_CS(enc->enc_pic.addrmode_arraymode_disrdo_distwoinstants);
RVCE_CS(enc->enc_pic.ec.enc_pre_encode_context_buffer_offset);
@ -240,12 +240,12 @@ static void encode(struct rvce_encoder *enc)
RVCE_CS(enc->enc_pic.eo.end_of_sequence);
RVCE_CS(enc->enc_pic.eo.end_of_stream);
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->luma->level[0].offset); // inputPictureLumaAddressHi/Lo
enc->luma->u.legacy.level[0].offset); // inputPictureLumaAddressHi/Lo
RVCE_READ(enc->handle, RADEON_DOMAIN_VRAM,
enc->chroma->level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
enc->chroma->u.legacy.level[0].offset); // inputPictureChromaAddressHi/Lo
RVCE_CS(align(enc->luma->u.legacy.level[0].nblk_y, 16)); // encInputFrameYPitch
RVCE_CS(enc->luma->u.legacy.level[0].nblk_x * enc->luma->bpe); // encInputPicLumaPitch
RVCE_CS(enc->chroma->u.legacy.level[0].nblk_x * enc->chroma->bpe); // encInputPicChromaPitch
if (enc->dual_pipe)
enc->enc_pic.eo.enc_input_pic_addr_array_disable2pipe_disablemboffload = 0x00000000;
else

14
src/gallium/drivers/radeon/radeon_video.c
View File

@ -154,7 +154,7 @@ void rvid_join_surfaces(struct radeon_winsys* ws,
continue;
/* choose the smallest bank w/h for now */
wh = surfaces[i]->bankw * surfaces[i]->bankh;
wh = surfaces[i]->u.legacy.bankw * surfaces[i]->u.legacy.bankh;
if (wh < best_wh) {
best_wh = wh;
best_tiling = i;
@ -166,15 +166,15 @@ void rvid_join_surfaces(struct radeon_winsys* ws,
continue;
/* copy the tiling parameters */
surfaces[i]->bankw = surfaces[best_tiling]->bankw;
surfaces[i]->bankh = surfaces[best_tiling]->bankh;
surfaces[i]->mtilea = surfaces[best_tiling]->mtilea;
surfaces[i]->tile_split = surfaces[best_tiling]->tile_split;
surfaces[i]->u.legacy.bankw = surfaces[best_tiling]->u.legacy.bankw;
surfaces[i]->u.legacy.bankh = surfaces[best_tiling]->u.legacy.bankh;
surfaces[i]->u.legacy.mtilea = surfaces[best_tiling]->u.legacy.mtilea;
surfaces[i]->u.legacy.tile_split = surfaces[best_tiling]->u.legacy.tile_split;
/* adjust the texture layer offsets */
off = align(off, surfaces[i]->surf_alignment);
for (j = 0; j < ARRAY_SIZE(surfaces[i]->level); ++j)
surfaces[i]->level[j].offset += off;
for (j = 0; j < ARRAY_SIZE(surfaces[i]->u.legacy.level); ++j)
surfaces[i]->u.legacy.level[j].offset += off;
off += surfaces[i]->surf_size;
}

59
src/gallium/drivers/radeon/radeon_winsys.h
View File

@ -289,7 +289,7 @@ enum radeon_micro_mode {
#define RADEON_SURF_IMPORTED (1 << 24)
#define RADEON_SURF_OPTIMIZE_FOR_SPACE (1 << 25)
struct radeon_surf_level {
struct legacy_surf_level {
uint64_t offset;
uint64_t slice_size;
uint64_t dcc_offset;
@ -299,6 +299,30 @@ struct radeon_surf_level {
enum radeon_surf_mode mode;
};
struct legacy_surf_layout {
unsigned bankw:4; /* max 8 */
unsigned bankh:4; /* max 8 */
unsigned mtilea:4; /* max 8 */
unsigned tile_split:13; /* max 4K */
unsigned stencil_tile_split:13; /* max 4K */
unsigned pipe_config:5; /* max 17 */
unsigned num_banks:5; /* max 16 */
unsigned macro_tile_index:4; /* max 15 */
/* Whether the depth miptree or stencil miptree as used by the DB are
* adjusted from their TC compatible form to ensure depth/stencil
* compatibility. If either is true, the corresponding plane cannot be
* sampled from.
*/
unsigned depth_adjusted:1;
unsigned stencil_adjusted:1;
struct legacy_surf_level level[RADEON_SURF_MAX_LEVELS];
struct legacy_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
};
struct radeon_surf {
/* Format properties. */
unsigned blk_w:4;
@ -310,6 +334,8 @@ struct radeon_surf {
*/
unsigned num_dcc_levels:4;
unsigned is_linear:1;
/* Displayable, thin, depth, rotated. AKA D,S,Z,R swizzle modes. */
unsigned micro_tile_mode:3;
uint32_t flags;
/* These are return values. Some of them can be set by the caller, but
@ -324,29 +350,14 @@ struct radeon_surf {
uint32_t dcc_alignment;
uint32_t htile_alignment;
/* This applies to EG and later. */
unsigned bankw:4; /* max 8 */
unsigned bankh:4; /* max 8 */
unsigned mtilea:4; /* max 8 */
unsigned tile_split:13; /* max 4K */
unsigned stencil_tile_split:13; /* max 4K */
unsigned pipe_config:5; /* max 17 */
unsigned num_banks:5; /* max 16 */
unsigned macro_tile_index:4; /* max 15 */
unsigned micro_tile_mode:3; /* displayable, thin, depth, rotated */
/* Whether the depth miptree or stencil miptree as used by the DB are
* adjusted from their TC compatible form to ensure depth/stencil
* compatibility. If either is true, the corresponding plane cannot be
* sampled from.
*/
unsigned depth_adjusted:1;
unsigned stencil_adjusted:1;
struct radeon_surf_level level[RADEON_SURF_MAX_LEVELS];
struct radeon_surf_level stencil_level[RADEON_SURF_MAX_LEVELS];
uint8_t tiling_index[RADEON_SURF_MAX_LEVELS];
uint8_t stencil_tiling_index[RADEON_SURF_MAX_LEVELS];
union {
/* R600-VI return values.
*
* Some of them can be set by the caller if certain parameters are
* desirable. The allocator will try to obey them.
*/
struct legacy_surf_layout legacy;
} u;
};
struct radeon_bo_list_item {

40
src/gallium/drivers/radeonsi/cik_sdma.c
View File

@ -120,8 +120,8 @@ static unsigned encode_tile_info(struct si_context *sctx,
bool set_bpp)
{
struct radeon_info *info = &sctx->screen->b.info;
unsigned tile_index = tex->surface.tiling_index[level];
unsigned macro_tile_index = tex->surface.macro_tile_index;
unsigned tile_index = tex->surface.u.legacy.tiling_index[level];
unsigned macro_tile_index = tex->surface.u.legacy.macro_tile_index;
unsigned tile_mode = info->si_tile_mode_array[tile_index];
unsigned macro_tile_mode = info->cik_macrotile_mode_array[macro_tile_index];
@ -129,7 +129,7 @@ static unsigned encode_tile_info(struct si_context *sctx,
(G_009910_ARRAY_MODE(tile_mode) << 3) |
(G_009910_MICRO_TILE_MODE_NEW(tile_mode) << 8) |
/* Non-depth modes don't have TILE_SPLIT set. */
((util_logbase2(tex->surface.tile_split >> 6)) << 11) |
((util_logbase2(tex->surface.u.legacy.tile_split >> 6)) << 11) |
(G_009990_BANK_WIDTH(macro_tile_mode) << 15) |
(G_009990_BANK_HEIGHT(macro_tile_mode) << 18) |
(G_009990_NUM_BANKS(macro_tile_mode) << 21) |
@ -150,21 +150,21 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned bpp = rdst->surface.bpe;
uint64_t dst_address = rdst->resource.gpu_address +
rdst->surface.level[dst_level].offset;
rdst->surface.u.legacy.level[dst_level].offset;
uint64_t src_address = rsrc->resource.gpu_address +
rsrc->surface.level[src_level].offset;
unsigned dst_mode = rdst->surface.level[dst_level].mode;
unsigned src_mode = rsrc->surface.level[src_level].mode;
unsigned dst_tile_index = rdst->surface.tiling_index[dst_level];
unsigned src_tile_index = rsrc->surface.tiling_index[src_level];
rsrc->surface.u.legacy.level[src_level].offset;
unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
unsigned src_mode = rsrc->surface.u.legacy.level[src_level].mode;
unsigned dst_tile_index = rdst->surface.u.legacy.tiling_index[dst_level];
unsigned src_tile_index = rsrc->surface.u.legacy.tiling_index[src_level];
unsigned dst_tile_mode = info->si_tile_mode_array[dst_tile_index];
unsigned src_tile_mode = info->si_tile_mode_array[src_tile_index];
unsigned dst_micro_mode = G_009910_MICRO_TILE_MODE_NEW(dst_tile_mode);
unsigned src_micro_mode = G_009910_MICRO_TILE_MODE_NEW(src_tile_mode);
unsigned dst_pitch = rdst->surface.level[dst_level].nblk_x;
unsigned src_pitch = rsrc->surface.level[src_level].nblk_x;
uint64_t dst_slice_pitch = rdst->surface.level[dst_level].slice_size / bpp;
uint64_t src_slice_pitch = rsrc->surface.level[src_level].slice_size / bpp;
unsigned dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x;
unsigned src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x;
uint64_t dst_slice_pitch = rdst->surface.u.legacy.level[dst_level].slice_size / bpp;
uint64_t src_slice_pitch = rsrc->surface.u.legacy.level[src_level].slice_size / bpp;
unsigned dst_width = minify_as_blocks(rdst->resource.b.b.width0,
dst_level, rdst->surface.blk_w);
unsigned src_width = minify_as_blocks(rsrc->resource.b.b.width0,
@ -182,10 +182,10 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
assert(src_level <= src->last_level);
assert(dst_level <= dst->last_level);
assert(rdst->surface.level[dst_level].offset +
assert(rdst->surface.u.legacy.level[dst_level].offset +
dst_slice_pitch * bpp * (dstz + src_box->depth) <=
rdst->resource.buf->size);
assert(rsrc->surface.level[src_level].offset +
assert(rsrc->surface.u.legacy.level[src_level].offset +
src_slice_pitch * bpp * (srcz + src_box->depth) <=
rsrc->resource.buf->size);
@ -350,14 +350,14 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
* starts reading from an address preceding linear_address!!!
*/
start_linear_address =
linear->surface.level[linear_level].offset +
linear->surface.u.legacy.level[linear_level].offset +
bpp * (linear_z * linear_slice_pitch +
linear_y * linear_pitch +
linear_x);
start_linear_address -= (int)(bpp * (tiled_x % granularity));
end_linear_address =
linear->surface.level[linear_level].offset +
linear->surface.u.legacy.level[linear_level].offset +
bpp * ((linear_z + copy_depth - 1) * linear_slice_pitch +
(linear_y + copy_height - 1) * linear_pitch +
(linear_x + copy_width));
@ -379,7 +379,7 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
copy_width_aligned % xalign == 0 &&
tiled_micro_mode != V_009910_ADDR_SURF_ROTATED_MICRO_TILING &&
/* check if everything fits into the bitfields */
tiled->surface.tile_split <= 4096 &&
tiled->surface.u.legacy.tile_split <= 4096 &&
pitch_tile_max < (1 << 11) &&
slice_tile_max < (1 << 22) &&
linear_pitch <= (1 << 14) &&
@ -423,8 +423,8 @@ static bool cik_sdma_copy_texture(struct si_context *sctx,
/* check if these fit into the bitfields */
src_address % 256 == 0 &&
dst_address % 256 == 0 &&
rsrc->surface.tile_split <= 4096 &&
rdst->surface.tile_split <= 4096 &&
rsrc->surface.u.legacy.tile_split <= 4096 &&
rdst->surface.u.legacy.tile_split <= 4096 &&
dstx % 8 == 0 &&
dsty % 8 == 0 &&
srcx % 8 == 0 &&

4
src/gallium/drivers/radeonsi/si_descriptors.c
View File

@ -377,7 +377,7 @@ static void si_set_buf_desc_address(struct r600_resource *buf,
* \param state descriptor to update
*/
void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
const struct radeon_surf_level *base_level_info,
const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
uint32_t *state)
@ -746,7 +746,7 @@ static void si_set_shader_image(struct si_context *ctx,
view->u.tex.last_layer,
width, height, depth,
desc, NULL);
si_set_mutable_tex_desc_fields(tex, &tex->surface.level[level],
si_set_mutable_tex_desc_fields(tex, &tex->surface.u.legacy.level[level],
level, level,
util_format_get_blockwidth(view->format),
false, desc);

42
src/gallium/drivers/radeonsi/si_dma.c
View File

@ -135,14 +135,14 @@ static void si_dma_copy_tile(struct si_context *ctx,
struct radeon_winsys_cs *cs = ctx->b.dma.cs;
struct r600_texture *rsrc = (struct r600_texture*)src;
struct r600_texture *rdst = (struct r600_texture*)dst;
unsigned dst_mode = rdst->surface.level[dst_level].mode;
unsigned dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
bool detile = dst_mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
struct r600_texture *rlinear = detile ? rdst : rsrc;
struct r600_texture *rtiled = detile ? rsrc : rdst;
unsigned linear_lvl = detile ? dst_level : src_level;
unsigned tiled_lvl = detile ? src_level : dst_level;
struct radeon_info *info = &ctx->screen->b.info;
unsigned index = rtiled->surface.tiling_index[tiled_lvl];
unsigned index = rtiled->surface.u.legacy.tiling_index[tiled_lvl];
unsigned tile_mode = info->si_tile_mode_array[index];
unsigned array_mode, lbpp, pitch_tile_max, slice_tile_max, size;
unsigned ncopy, height, cheight, i;
@ -151,7 +151,7 @@ static void si_dma_copy_tile(struct si_context *ctx,
uint64_t base, addr;
unsigned pipe_config;
assert(dst_mode != rsrc->surface.level[src_level].mode);
assert(dst_mode != rsrc->surface.u.legacy.level[src_level].mode);
sub_cmd = SI_DMA_COPY_TILED;
lbpp = util_logbase2(bpp);
@ -167,23 +167,23 @@ static void si_dma_copy_tile(struct si_context *ctx,
assert(!util_format_is_depth_and_stencil(rtiled->resource.b.b.format));
array_mode = G_009910_ARRAY_MODE(tile_mode);
slice_tile_max = (rtiled->surface.level[tiled_lvl].nblk_x *
rtiled->surface.level[tiled_lvl].nblk_y) / (8*8) - 1;
slice_tile_max = (rtiled->surface.u.legacy.level[tiled_lvl].nblk_x *
rtiled->surface.u.legacy.level[tiled_lvl].nblk_y) / (8*8) - 1;
/* linear height must be the same as the slice tile max height, it's ok even
* if the linear destination/source have smaller heigh as the size of the
* dma packet will be using the copy_height which is always smaller or equal
* to the linear height
*/
height = rtiled->surface.level[tiled_lvl].nblk_y;
base = rtiled->surface.level[tiled_lvl].offset;
addr = rlinear->surface.level[linear_lvl].offset;
addr += rlinear->surface.level[linear_lvl].slice_size * linear_z;
height = rtiled->surface.u.legacy.level[tiled_lvl].nblk_y;
base = rtiled->surface.u.legacy.level[tiled_lvl].offset;
addr = rlinear->surface.u.legacy.level[linear_lvl].offset;
addr += rlinear->surface.u.legacy.level[linear_lvl].slice_size * linear_z;
addr += linear_y * pitch + linear_x * bpp;
bank_h = G_009910_BANK_HEIGHT(tile_mode);
bank_w = G_009910_BANK_WIDTH(tile_mode);
mt_aspect = G_009910_MACRO_TILE_ASPECT(tile_mode);
/* Non-depth modes don't have TILE_SPLIT set. */
tile_split = util_logbase2(rtiled->surface.tile_split >> 6);
tile_split = util_logbase2(rtiled->surface.u.legacy.tile_split >> 6);
nbanks = G_009910_NUM_BANKS(tile_mode);
base += rtiled->resource.gpu_address;
addr += rlinear->resource.gpu_address;
@ -268,20 +268,20 @@ static void si_dma_copy(struct pipe_context *ctx,
dst_y = util_format_get_nblocksy(src->format, dst_y);
bpp = rdst->surface.bpe;
dst_pitch = rdst->surface.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.level[src_level].nblk_x * rsrc->surface.bpe;
dst_pitch = rdst->surface.u.legacy.level[dst_level].nblk_x * rdst->surface.bpe;
src_pitch = rsrc->surface.u.legacy.level[src_level].nblk_x * rsrc->surface.bpe;
src_w = u_minify(rsrc->resource.b.b.width0, src_level);
dst_w = u_minify(rdst->resource.b.b.width0, dst_level);
dst_mode = rdst->surface.level[dst_level].mode;
src_mode = rsrc->surface.level[src_level].mode;
dst_mode = rdst->surface.u.legacy.level[dst_level].mode;
src_mode = rsrc->surface.u.legacy.level[src_level].mode;
if (src_pitch != dst_pitch || src_box->x || dst_x || src_w != dst_w ||
src_box->width != src_w ||
src_box->height != u_minify(rsrc->resource.b.b.height0, src_level) ||
src_box->height != u_minify(rdst->resource.b.b.height0, dst_level) ||
rsrc->surface.level[src_level].nblk_y !=
rdst->surface.level[dst_level].nblk_y) {
rsrc->surface.u.legacy.level[src_level].nblk_y !=
rdst->surface.u.legacy.level[dst_level].nblk_y) {
/* FIXME si can do partial blit */
goto fallback;
}
@ -300,14 +300,14 @@ static void si_dma_copy(struct pipe_context *ctx,
* dst_x/y == 0
* dst_pitch == src_pitch
*/
src_offset= rsrc->surface.level[src_level].offset;
src_offset += rsrc->surface.level[src_level].slice_size * src_box->z;
src_offset= rsrc->surface.u.legacy.level[src_level].offset;
src_offset += rsrc->surface.u.legacy.level[src_level].slice_size * src_box->z;
src_offset += src_y * src_pitch + src_x * bpp;
dst_offset = rdst->surface.level[dst_level].offset;
dst_offset += rdst->surface.level[dst_level].slice_size * dst_z;
dst_offset = rdst->surface.u.legacy.level[dst_level].offset;
dst_offset += rdst->surface.u.legacy.level[dst_level].slice_size * dst_z;
dst_offset += dst_y * dst_pitch + dst_x * bpp;
si_dma_copy_buffer(sctx, dst, src, dst_offset, src_offset,
rsrc->surface.level[src_level].slice_size);
rsrc->surface.u.legacy.level[src_level].slice_size);
} else {
si_dma_copy_tile(sctx, dst, dst_level, dst_x, dst_y, dst_z,
src, src_level, src_x, src_y, src_box->z,

2
src/gallium/drivers/radeonsi/si_pipe.h
View File

@ -123,7 +123,7 @@ struct si_sampler_view {
* [4..7] = buffer descriptor */
uint32_t state[8];
uint32_t fmask_state[8];
const struct radeon_surf_level *base_level_info;
const struct legacy_surf_level *base_level_info;
unsigned base_level;
unsigned block_width;
bool is_stencil_sampler;

30
src/gallium/drivers/radeonsi/si_state.c
View File

@ -2204,7 +2204,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
/* This must be set for fast clear to work without FMASK. */
if (!rtex->fmask.size && sctx->b.chip_class == SI) {
unsigned bankh = util_logbase2(rtex->surface.bankh);
unsigned bankh = util_logbase2(rtex->surface.u.legacy.bankh);
surf->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
}
@ -2219,7 +2219,7 @@ static void si_init_depth_surface(struct si_context *sctx,
{
struct r600_texture *rtex = (struct r600_texture*)surf->base.texture;
unsigned level = surf->base.u.tex.level;
struct radeon_surf_level *levelinfo = &rtex->surface.level[level];
struct legacy_surf_level *levelinfo = &rtex->surface.u.legacy.level[level];
unsigned format, stencil_format;
uint32_t z_info, s_info;
@ -2239,9 +2239,9 @@ static void si_init_depth_surface(struct si_context *sctx,
assert(levelinfo->nblk_x % 8 == 0 && levelinfo->nblk_y % 8 == 0);
surf->db_depth_base = (rtex->resource.gpu_address +
rtex->surface.level[level].offset) >> 8;
rtex->surface.u.legacy.level[level].offset) >> 8;
surf->db_stencil_base = (rtex->resource.gpu_address +
rtex->surface.stencil_level[level].offset) >> 8;
rtex->surface.u.legacy.stencil_level[level].offset) >> 8;
z_info = S_028040_FORMAT(format) |
S_028040_NUM_SAMPLES(util_logbase2(rtex->resource.b.b.nr_samples));
@ -2250,9 +2250,9 @@ static void si_init_depth_surface(struct si_context *sctx,
if (sctx->b.chip_class >= CIK) {
struct radeon_info *info = &sctx->screen->b.info;
unsigned index = rtex->surface.tiling_index[level];
unsigned stencil_index = rtex->surface.stencil_tiling_index[level];
unsigned macro_index = rtex->surface.macro_tile_index;
unsigned index = rtex->surface.u.legacy.tiling_index[level];
unsigned stencil_index = rtex->surface.u.legacy.stencil_tiling_index[level];
unsigned macro_index = rtex->surface.u.legacy.macro_tile_index;
unsigned tile_mode = info->si_tile_mode_array[index];
unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
@ -2506,7 +2506,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
/* Colorbuffers. */
for (i = 0; i < nr_cbufs; i++) {
const struct radeon_surf_level *level_info;
const struct legacy_surf_level *level_info;
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
unsigned cb_color_base, cb_color_fmask, cb_color_attrib;
unsigned cb_color_pitch, cb_color_slice, cb_color_fmask_slice;
@ -2522,7 +2522,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
}
tex = (struct r600_texture *)cb->base.texture;
level_info = &tex->surface.level[cb->base.u.tex.level];
level_info = &tex->surface.u.legacy.level[cb->base.u.tex.level];
radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
&tex->resource, RADEON_USAGE_READWRITE,
tex->resource.b.b.nr_samples > 1 ?
@ -2599,7 +2599,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct r600_atom
if (sctx->b.chip_class >= VI) /* R_028C94_CB_COLOR0_DCC_BASE */
radeon_emit(cs, ((!tex->dcc_separate_buffer ? tex->resource.gpu_address : 0) +
tex->dcc_offset +
tex->surface.level[cb->base.u.tex.level].dcc_offset) >> 8);
tex->surface.u.legacy.level[cb->base.u.tex.level].dcc_offset) >> 8);
}
for (; i < 8 ; i++)
if (sctx->framebuffer.dirty_cbufs & (1 << i))
@ -3036,7 +3036,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
unsigned height, depth, width;
unsigned last_layer = state->u.tex.last_layer;
enum pipe_format pipe_format;
const struct radeon_surf_level *surflevel;
const struct legacy_surf_level *surflevel;
if (!view)
return NULL;
@ -3120,7 +3120,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
tmp = tmp->flushed_depth_texture;
}
surflevel = tmp->surface.level;
surflevel = tmp->surface.u.legacy.level;
if (tmp->db_compatible) {
if (!view->is_stencil_sampler)
@ -3141,7 +3141,7 @@ si_create_sampler_view_custom(struct pipe_context *ctx,
case PIPE_FORMAT_S8X24_UINT:
case PIPE_FORMAT_X32_S8X24_UINT:
pipe_format = PIPE_FORMAT_S8_UINT;
surflevel = tmp->surface.stencil_level;
surflevel = tmp->surface.u.legacy.stencil_level;
break;
default:;
}
@ -3785,7 +3785,7 @@ static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
res->width0, res->height0, res->depth0,
desc, NULL);
si_set_mutable_tex_desc_fields(rtex, &rtex->surface.level[0], 0, 0,
si_set_mutable_tex_desc_fields(rtex, &rtex->surface.u.legacy.level[0], 0, 0,
rtex->surface.blk_w, false, desc);
/* Clear the base address and set the relative DCC offset. */
@ -3798,7 +3798,7 @@ static void si_query_opaque_metadata(struct r600_common_screen *rscreen,
/* Dwords [10:..] contain the mipmap level offsets. */
for (i = 0; i <= res->last_level; i++)
md->metadata[10+i] = rtex->surface.level[i].offset >> 8;
md->metadata[10+i] = rtex->surface.u.legacy.level[i].offset >> 8;
md->size_metadata = (11 + res->last_level) * 4;
}

6
src/gallium/drivers/radeonsi/si_state.h
View File

@ -283,7 +283,7 @@ struct si_buffer_resources {
void si_ce_reinitialize_all_descriptors(struct si_context *sctx);
void si_ce_enable_loads(struct radeon_winsys_cs *ib);
void si_set_mutable_tex_desc_fields(struct r600_texture *tex,
const struct radeon_surf_level *base_level_info,
const struct legacy_surf_level *base_level_info,
unsigned base_level, unsigned first_level,
unsigned block_width, bool is_stencil,
uint32_t *state);
@ -366,9 +366,9 @@ static inline unsigned
si_tile_mode_index(struct r600_texture *rtex, unsigned level, bool stencil)
{
if (stencil)
return rtex->surface.stencil_tiling_index[level];
return rtex->surface.u.legacy.stencil_tiling_index[level];
else
return rtex->surface.tiling_index[level];
return rtex->surface.u.legacy.tiling_index[level];
}
#endif

57
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View File

@ -153,7 +153,7 @@ static int compute_level(struct amdgpu_winsys *ws,
ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
{
struct radeon_surf_level *surf_level;
struct legacy_surf_level *surf_level;
ADDR_E_RETURNCODE ret;
AddrSurfInfoIn->mipLevel = level;
@ -171,9 +171,9 @@ static int compute_level(struct amdgpu_winsys *ws,
/* Set the base level pitch. This is needed for calculation
* of non-zero levels. */
if (is_stencil)
AddrSurfInfoIn->basePitch = surf->stencil_level[0].nblk_x;
AddrSurfInfoIn->basePitch = surf->u.legacy.stencil_level[0].nblk_x;
else
AddrSurfInfoIn->basePitch = surf->level[0].nblk_x;
AddrSurfInfoIn->basePitch = surf->u.legacy.level[0].nblk_x;
/* Convert blocks to pixels for compressed formats. */
if (compressed)
@ -187,7 +187,7 @@ static int compute_level(struct amdgpu_winsys *ws,
return ret;
}
surf_level = is_stencil ? &surf->stencil_level[level] : &surf->level[level];
surf_level = is_stencil ? &surf->u.legacy.stencil_level[level] : &surf->u.legacy.level[level];
surf_level->offset = align64(surf->surf_size, AddrSurfInfoOut->baseAlign);
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
surf_level->nblk_x = AddrSurfInfoOut->pitch;
@ -208,9 +208,9 @@ static int compute_level(struct amdgpu_winsys *ws,
}
if (is_stencil)
surf->stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
surf->u.legacy.stencil_tiling_index[level] = AddrSurfInfoOut->tileIndex;
else
surf->tiling_index[level] = AddrSurfInfoOut->tileIndex;
surf->u.legacy.tiling_index[level] = AddrSurfInfoOut->tileIndex;
surf->surf_size = surf_level->offset + AddrSurfInfoOut->surfSize;
@ -274,7 +274,7 @@ static int compute_level(struct amdgpu_winsys *ws,
static void set_micro_tile_mode(struct radeon_surf *surf,
struct radeon_info *info)
{
uint32_t tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
uint32_t tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
@ -287,7 +287,7 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
unsigned index, tileb;
tileb = 8 * 8 * surf->bpe;
tileb = MIN2(surf->tile_split, tileb);
tileb = MIN2(surf->u.legacy.tile_split, tileb);
for (index = 0; tileb > 64; index++)
tileb >>= 1;
@ -434,17 +434,18 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
/* Set preferred macrotile parameters. This is usually required
* for shared resources. This is for 2D tiling only. */
if (AddrSurfInfoIn.tileMode >= ADDR_TM_2D_TILED_THIN1 &&
surf->bankw && surf->bankh && surf->mtilea && surf->tile_split) {
surf->u.legacy.bankw && surf->u.legacy.bankh &&
surf->u.legacy.mtilea && surf->u.legacy.tile_split) {
assert(!(flags & RADEON_SURF_FMASK));
/* If any of these parameters are incorrect, the calculation
* will fail. */
AddrTileInfoIn.banks = surf->num_banks;
AddrTileInfoIn.bankWidth = surf->bankw;
AddrTileInfoIn.bankHeight = surf->bankh;
AddrTileInfoIn.macroAspectRatio = surf->mtilea;
AddrTileInfoIn.tileSplitBytes = surf->tile_split;
AddrTileInfoIn.pipeConfig = surf->pipe_config + 1; /* +1 compared to GB_TILE_MODE */
AddrTileInfoIn.banks = surf->u.legacy.num_banks;
AddrTileInfoIn.bankWidth = surf->u.legacy.bankw;
AddrTileInfoIn.bankHeight = surf->u.legacy.bankh;
AddrTileInfoIn.macroAspectRatio = surf->u.legacy.mtilea;
AddrTileInfoIn.tileSplitBytes = surf->u.legacy.tile_split;
AddrTileInfoIn.pipeConfig = surf->u.legacy.pipe_config + 1; /* +1 compared to GB_TILE_MODE */
AddrSurfInfoIn.flags.opt4Space = 0;
AddrSurfInfoIn.pTileInfo = &AddrTileInfoIn;
@ -504,19 +505,19 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (level == 0) {
surf->surf_alignment = AddrSurfInfoOut.baseAlign;
surf->pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
surf->u.legacy.pipe_config = AddrSurfInfoOut.pTileInfo->pipeConfig - 1;
set_micro_tile_mode(surf, &ws->info);
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
surf->bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
surf->bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
surf->mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
surf->tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
surf->num_banks = AddrSurfInfoOut.pTileInfo->banks;
surf->macro_tile_index = AddrSurfInfoOut.macroModeIndex;
surf->u.legacy.bankw = AddrSurfInfoOut.pTileInfo->bankWidth;
surf->u.legacy.bankh = AddrSurfInfoOut.pTileInfo->bankHeight;
surf->u.legacy.mtilea = AddrSurfInfoOut.pTileInfo->macroAspectRatio;
surf->u.legacy.tile_split = AddrSurfInfoOut.pTileInfo->tileSplitBytes;
surf->u.legacy.num_banks = AddrSurfInfoOut.pTileInfo->banks;
surf->u.legacy.macro_tile_index = AddrSurfInfoOut.macroModeIndex;
} else {
surf->macro_tile_index = 0;
surf->u.legacy.macro_tile_index = 0;
}
}
}
@ -528,7 +529,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
AddrSurfInfoIn.flags.stencil = 1;
AddrSurfInfoIn.flags.tcCompatible = 0;
/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
AddrTileInfoIn.tileSplitBytes = surf->u.legacy.stencil_tile_split;
for (level = 0; level <= tex->last_level; level++) {
r = compute_level(ws, tex, surf, true, level, compressed,
@ -538,13 +539,13 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
return r;
/* DB uses the depth pitch for both stencil and depth. */
if (surf->stencil_level[level].nblk_x != surf->level[level].nblk_x)
surf->stencil_adjusted = true;
if (surf->u.legacy.stencil_level[level].nblk_x != surf->u.legacy.level[level].nblk_x)
surf->u.legacy.stencil_adjusted = true;
if (level == 0) {
/* For 2D modes only. */
if (AddrSurfInfoOut.tileMode >= ADDR_TM_2D_TILED_THIN1) {
surf->stencil_tile_split =
surf->u.legacy.stencil_tile_split =
AddrSurfInfoOut.pTileInfo->tileSplitBytes;
}
}
@ -567,7 +568,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
if (surf->htile_size && tex->last_level)
surf->htile_size *= 2;
surf->is_linear = surf->level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
surf->is_linear = surf->u.legacy.level[0].mode == RADEON_SURF_MODE_LINEAR_ALIGNED;
return 0;
}

46
src/gallium/winsys/radeon/drm/radeon_drm_surface.c
View File

@ -36,7 +36,7 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
unsigned index, tileb;
tileb = 8 * 8 * surf->bpe;
tileb = MIN2(surf->tile_split, tileb);
tileb = MIN2(surf->u.legacy.tile_split, tileb);
for (index = 0; tileb > 64; index++)
tileb >>= 1;
@ -58,7 +58,7 @@ static void set_micro_tile_mode(struct radeon_surf *surf,
return;
}
tile_mode = info->si_tile_mode_array[surf->tiling_index[0]];
tile_mode = info->si_tile_mode_array[surf->u.legacy.tiling_index[0]];
if (info->chip_class >= CIK)
surf->micro_tile_mode = G_009910_MICRO_TILE_MODE_NEW(tile_mode);
@ -67,7 +67,7 @@ static void set_micro_tile_mode(struct radeon_surf *surf,
}
static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
const struct radeon_surf_level *level_ws,
const struct legacy_surf_level *level_ws,
unsigned bpe)
{
level_drm->offset = level_ws->offset;
@ -78,7 +78,7 @@ static void surf_level_winsys_to_drm(struct radeon_surface_level *level_drm,
level_drm->mode = level_ws->mode;
}
static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws,
static void surf_level_drm_to_winsys(struct legacy_surf_level *level_ws,
const struct radeon_surface_level *level_drm,
unsigned bpe)
{
@ -151,26 +151,26 @@ static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
surf_drm->bo_size = surf_ws->surf_size;
surf_drm->bo_alignment = surf_ws->surf_alignment;
surf_drm->bankw = surf_ws->bankw;
surf_drm->bankh = surf_ws->bankh;
surf_drm->mtilea = surf_ws->mtilea;
surf_drm->tile_split = surf_ws->tile_split;
surf_drm->bankw = surf_ws->u.legacy.bankw;
surf_drm->bankh = surf_ws->u.legacy.bankh;
surf_drm->mtilea = surf_ws->u.legacy.mtilea;
surf_drm->tile_split = surf_ws->u.legacy.tile_split;
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->level[i],
surf_level_winsys_to_drm(&surf_drm->level[i], &surf_ws->u.legacy.level[i],
bpe * surf_drm->nsamples);
surf_drm->tiling_index[i] = surf_ws->tiling_index[i];
surf_drm->tiling_index[i] = surf_ws->u.legacy.tiling_index[i];
}
if (flags & RADEON_SURF_SBUFFER) {
surf_drm->stencil_tile_split = surf_ws->stencil_tile_split;
surf_drm->stencil_tile_split = surf_ws->u.legacy.stencil_tile_split;
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_winsys_to_drm(&surf_drm->stencil_level[i],
&surf_ws->stencil_level[i],
&surf_ws->u.legacy.stencil_level[i],
surf_drm->nsamples);
surf_drm->stencil_tiling_index[i] = surf_ws->stencil_tiling_index[i];
surf_drm->stencil_tiling_index[i] = surf_ws->u.legacy.stencil_tiling_index[i];
}
}
}
@ -192,27 +192,27 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
surf_ws->surf_size = surf_drm->bo_size;
surf_ws->surf_alignment = surf_drm->bo_alignment;
surf_ws->bankw = surf_drm->bankw;
surf_ws->bankh = surf_drm->bankh;
surf_ws->mtilea = surf_drm->mtilea;
surf_ws->tile_split = surf_drm->tile_split;
surf_ws->u.legacy.bankw = surf_drm->bankw;
surf_ws->u.legacy.bankh = surf_drm->bankh;
surf_ws->u.legacy.mtilea = surf_drm->mtilea;
surf_ws->u.legacy.tile_split = surf_drm->tile_split;
surf_ws->macro_tile_index = cik_get_macro_tile_index(surf_ws);
surf_ws->u.legacy.macro_tile_index = cik_get_macro_tile_index(surf_ws);
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_drm_to_winsys(&surf_ws->level[i], &surf_drm->level[i],
surf_level_drm_to_winsys(&surf_ws->u.legacy.level[i], &surf_drm->level[i],
surf_drm->bpe * surf_drm->nsamples);
surf_ws->tiling_index[i] = surf_drm->tiling_index[i];
surf_ws->u.legacy.tiling_index[i] = surf_drm->tiling_index[i];
}
if (surf_ws->flags & RADEON_SURF_SBUFFER) {
surf_ws->stencil_tile_split = surf_drm->stencil_tile_split;
surf_ws->u.legacy.stencil_tile_split = surf_drm->stencil_tile_split;
for (i = 0; i <= surf_drm->last_level; i++) {
surf_level_drm_to_winsys(&surf_ws->stencil_level[i],
surf_level_drm_to_winsys(&surf_ws->u.legacy.stencil_level[i],
&surf_drm->stencil_level[i],
surf_drm->nsamples);
surf_ws->stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
surf_ws->u.legacy.stencil_tiling_index[i] = surf_drm->stencil_tiling_index[i];
}
}