gallium/radeon: pass pipe_resource and other params to surface_init directly
This removes input-only parameters from the radeon_surf structure. Some of the translation logic from pipe_resource to radeon_surf is moved to winsys/radeon. Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
parent
8b94976df9
commit
e9590d9092
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@ -203,65 +203,25 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
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const struct util_format_description *desc =
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util_format_description(ptex->format);
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bool is_depth, is_stencil;
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int r, i;
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int r;
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unsigned i, bpe, flags = 0;
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is_depth = util_format_has_depth(desc);
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is_stencil = util_format_has_stencil(desc);
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surface->npix_x = ptex->width0;
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surface->npix_y = ptex->height0;
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surface->npix_z = ptex->depth0;
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surface->blk_w = util_format_get_blockwidth(ptex->format);
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surface->blk_h = util_format_get_blockheight(ptex->format);
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surface->blk_d = 1;
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surface->array_size = 1;
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surface->last_level = ptex->last_level;
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if (rscreen->chip_class >= EVERGREEN && !is_flushed_depth &&
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ptex->format == PIPE_FORMAT_Z32_FLOAT_S8X24_UINT) {
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surface->bpe = 4; /* stencil is allocated separately on evergreen */
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bpe = 4; /* stencil is allocated separately on evergreen */
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} else {
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surface->bpe = util_format_get_blocksize(ptex->format);
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bpe = util_format_get_blocksize(ptex->format);
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/* align byte per element on dword */
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if (surface->bpe == 3) {
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surface->bpe = 4;
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if (bpe == 3) {
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bpe = 4;
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}
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}
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surface->nsamples = ptex->nr_samples ? ptex->nr_samples : 1;
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surface->flags = RADEON_SURF_SET(array_mode, MODE);
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switch (ptex->target) {
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case PIPE_TEXTURE_1D:
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
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break;
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case PIPE_TEXTURE_RECT:
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case PIPE_TEXTURE_2D:
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
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break;
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case PIPE_TEXTURE_3D:
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
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break;
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case PIPE_TEXTURE_1D_ARRAY:
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
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surface->array_size = ptex->array_size;
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break;
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case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
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assert(ptex->array_size % 6 == 0);
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case PIPE_TEXTURE_2D_ARRAY:
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
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surface->array_size = ptex->array_size;
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break;
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case PIPE_TEXTURE_CUBE:
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surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
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break;
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case PIPE_BUFFER:
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default:
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return -EINVAL;
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}
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if (!is_flushed_depth && is_depth) {
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surface->flags |= RADEON_SURF_ZBUFFER;
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flags |= RADEON_SURF_ZBUFFER;
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if (tc_compatible_htile &&
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array_mode == RADEON_SURF_MODE_2D) {
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@ -269,24 +229,24 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
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* Promote Z16 to Z32. DB->CB copies will convert
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* the format for transfers.
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*/
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surface->bpe = 4;
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surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
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bpe = 4;
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flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
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}
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if (is_stencil) {
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surface->flags |= RADEON_SURF_SBUFFER |
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RADEON_SURF_HAS_SBUFFER_MIPTREE;
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flags |= RADEON_SURF_SBUFFER |
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RADEON_SURF_HAS_SBUFFER_MIPTREE;
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}
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}
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if (rscreen->chip_class >= SI) {
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surface->flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
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flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
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}
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if (rscreen->chip_class >= VI &&
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(ptex->flags & R600_RESOURCE_FLAG_DISABLE_DCC ||
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ptex->format == PIPE_FORMAT_R9G9B9E5_FLOAT))
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surface->flags |= RADEON_SURF_DISABLE_DCC;
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flags |= RADEON_SURF_DISABLE_DCC;
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if (ptex->bind & PIPE_BIND_SCANOUT || is_scanout) {
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/* This should catch bugs in gallium users setting incorrect flags. */
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@ -294,15 +254,16 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
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ptex->array_size == 1 &&
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ptex->depth0 == 1 &&
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ptex->last_level == 0 &&
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!(surface->flags & RADEON_SURF_Z_OR_SBUFFER));
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!(flags & RADEON_SURF_Z_OR_SBUFFER));
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surface->flags |= RADEON_SURF_SCANOUT;
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flags |= RADEON_SURF_SCANOUT;
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}
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if (is_imported)
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surface->flags |= RADEON_SURF_IMPORTED;
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flags |= RADEON_SURF_IMPORTED;
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r = rscreen->ws->surface_init(rscreen->ws, surface);
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r = rscreen->ws->surface_init(rscreen->ws, ptex, flags, bpe,
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array_mode, surface);
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if (r) {
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return r;
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}
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@ -311,7 +272,7 @@ static int r600_init_surface(struct r600_common_screen *rscreen,
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/* old ddx on evergreen over estimate alignment for 1d, only 1 level
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* for those
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*/
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surface->level[0].nblk_x = pitch_in_bytes_override / surface->bpe;
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surface->level[0].nblk_x = pitch_in_bytes_override / bpe;
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surface->level[0].pitch_bytes = pitch_in_bytes_override;
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surface->level[0].slice_size = pitch_in_bytes_override * surface->level[0].nblk_y;
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}
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@ -629,35 +590,35 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
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struct r600_fmask_info *out)
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{
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/* FMASK is allocated like an ordinary texture. */
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struct radeon_surf fmask = rtex->surface;
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struct pipe_resource templ = rtex->resource.b.b;
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struct radeon_surf fmask = {};
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unsigned flags, bpe;
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memset(out, 0, sizeof(*out));
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fmask.bo_alignment = 0;
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fmask.bo_size = 0;
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fmask.nsamples = 1;
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fmask.flags |= RADEON_SURF_FMASK;
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templ.nr_samples = 1;
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flags = rtex->surface.flags | RADEON_SURF_FMASK;
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/* Force 2D tiling if it wasn't set. This may occur when creating
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* FMASK for MSAA resolve on R6xx. On R6xx, the single-sample
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* destination buffer must have an FMASK too. */
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fmask.flags = RADEON_SURF_CLR(fmask.flags, MODE);
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fmask.flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
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/* Use the same parameters and tile mode. */
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fmask.bankw = rtex->surface.bankw;
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fmask.bankh = rtex->surface.bankh;
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fmask.mtilea = rtex->surface.mtilea;
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fmask.tile_split = rtex->surface.tile_split;
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if (rscreen->chip_class >= SI) {
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fmask.flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
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flags |= RADEON_SURF_HAS_TILE_MODE_INDEX;
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}
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switch (nr_samples) {
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case 2:
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case 4:
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fmask.bpe = 1;
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bpe = 1;
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if (rscreen->chip_class <= CAYMAN) {
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fmask.bankh = 4;
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}
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break;
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case 8:
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fmask.bpe = 4;
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bpe = 4;
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break;
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default:
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R600_ERR("Invalid sample count for FMASK allocation.\n");
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@ -668,10 +629,11 @@ void r600_texture_get_fmask_info(struct r600_common_screen *rscreen,
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* This can be fixed by writing a separate FMASK allocator specifically
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* for R600-R700 asics. */
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if (rscreen->chip_class <= R700) {
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fmask.bpe *= 2;
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bpe *= 2;
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}
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if (rscreen->ws->surface_init(rscreen->ws, &fmask)) {
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if (rscreen->ws->surface_init(rscreen->ws, &templ, flags, bpe,
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RADEON_SURF_MODE_2D, &fmask)) {
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R600_ERR("Got error in surface_init while allocating FMASK.\n");
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return;
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}
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@ -958,13 +920,13 @@ void r600_print_texture_info(struct r600_texture *rtex, FILE *f)
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int i;
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fprintf(f, " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
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"blk_h=%u, blk_d=%u, array_size=%u, last_level=%u, "
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"blk_h=%u, array_size=%u, last_level=%u, "
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"bpe=%u, nsamples=%u, flags=0x%x, %s\n",
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rtex->surface.npix_x, rtex->surface.npix_y,
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rtex->surface.npix_z, rtex->surface.blk_w,
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rtex->surface.blk_h, rtex->surface.blk_d,
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rtex->surface.array_size, rtex->surface.last_level,
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rtex->surface.bpe, rtex->surface.nsamples,
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rtex->resource.b.b.width0, rtex->resource.b.b.height0,
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rtex->resource.b.b.depth0, rtex->surface.blk_w,
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rtex->surface.blk_h,
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rtex->resource.b.b.array_size, rtex->resource.b.b.last_level,
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rtex->surface.bpe, rtex->resource.b.b.nr_samples,
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rtex->surface.flags, util_format_short_name(rtex->resource.b.b.format));
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fprintf(f, " Layout: size=%"PRIu64", alignment=%"PRIu64", bankw=%u, "
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@ -263,16 +263,7 @@ enum radeon_surf_mode {
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RADEON_SURF_MODE_2D = 3,
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};
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#define RADEON_SURF_TYPE_MASK 0xFF
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#define RADEON_SURF_TYPE_SHIFT 0
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#define RADEON_SURF_TYPE_1D 0
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#define RADEON_SURF_TYPE_2D 1
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#define RADEON_SURF_TYPE_3D 2
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#define RADEON_SURF_TYPE_CUBEMAP 3
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#define RADEON_SURF_TYPE_1D_ARRAY 4
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#define RADEON_SURF_TYPE_2D_ARRAY 5
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#define RADEON_SURF_MODE_MASK 0xFF
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#define RADEON_SURF_MODE_SHIFT 8
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/* the first 16 bits are reserved for libdrm_radeon, don't use them */
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#define RADEON_SURF_SCANOUT (1 << 16)
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#define RADEON_SURF_ZBUFFER (1 << 17)
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#define RADEON_SURF_SBUFFER (1 << 18)
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@ -284,10 +275,6 @@ enum radeon_surf_mode {
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#define RADEON_SURF_TC_COMPATIBLE_HTILE (1 << 23)
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#define RADEON_SURF_IMPORTED (1 << 24)
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#define RADEON_SURF_GET(v, field) (((v) >> RADEON_SURF_ ## field ## _SHIFT) & RADEON_SURF_ ## field ## _MASK)
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#define RADEON_SURF_SET(v, field) (((v) & RADEON_SURF_ ## field ## _MASK) << RADEON_SURF_ ## field ## _SHIFT)
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#define RADEON_SURF_CLR(v, field) ((v) & ~(RADEON_SURF_ ## field ## _MASK << RADEON_SURF_ ## field ## _SHIFT))
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struct radeon_surf_level {
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uint64_t offset;
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uint64_t slice_size;
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@ -305,17 +292,10 @@ struct radeon_surf_level {
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};
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struct radeon_surf {
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/* These are inputs to the calculator. */
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uint32_t npix_x;
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uint32_t npix_y;
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uint32_t npix_z;
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/* Format properties. */
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uint32_t blk_w;
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uint32_t blk_h;
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uint32_t blk_d;
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uint32_t array_size;
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uint32_t last_level;
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uint32_t bpe;
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uint32_t nsamples;
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uint32_t flags;
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/* These are return values. Some of them can be set by the caller, but
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@ -743,9 +723,16 @@ struct radeon_winsys {
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* Initialize surface
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*
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* \param ws The winsys this function is called from.
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* \param surf Surface structure ptr
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* \param tex Input texture description
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* \param flags Bitmask of RADEON_SURF_* flags
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* \param bpe Bytes per pixel, it can be different for Z buffers.
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* \param mode Preferred tile mode. (linear, 1D, or 2D)
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* \param surf Output structure
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*/
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int (*surface_init)(struct radeon_winsys *ws,
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const struct pipe_resource *tex,
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unsigned flags, unsigned bpe,
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enum radeon_surf_mode mode,
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struct radeon_surf *surf);
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uint64_t (*query_value)(struct radeon_winsys *ws,
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@ -30,28 +30,22 @@
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*/
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#include "amdgpu_winsys.h"
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#include "util/u_format.h"
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#ifndef CIASICIDGFXENGINE_SOUTHERNISLAND
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#define CIASICIDGFXENGINE_SOUTHERNISLAND 0x0000000A
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#endif
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static int amdgpu_surface_sanity(const struct radeon_surf *surf)
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static int amdgpu_surface_sanity(const struct pipe_resource *tex)
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{
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unsigned type = RADEON_SURF_GET(surf->flags, TYPE);
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if (!(surf->flags & RADEON_SURF_HAS_TILE_MODE_INDEX))
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return -EINVAL;
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/* all dimension must be at least 1 ! */
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if (!surf->npix_x || !surf->npix_y || !surf->npix_z ||
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!surf->array_size)
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if (!tex->width0 || !tex->height0 || !tex->depth0 ||
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!tex->array_size)
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return -EINVAL;
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if (!surf->blk_w || !surf->blk_h || !surf->blk_d)
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return -EINVAL;
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switch (surf->nsamples) {
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switch (tex->nr_samples) {
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case 0:
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case 1:
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case 2:
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case 4:
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@ -61,26 +55,28 @@ static int amdgpu_surface_sanity(const struct radeon_surf *surf)
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return -EINVAL;
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}
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switch (type) {
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case RADEON_SURF_TYPE_1D:
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if (surf->npix_y > 1)
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switch (tex->target) {
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case PIPE_TEXTURE_1D:
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if (tex->height0 > 1)
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return -EINVAL;
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/* fall through */
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case RADEON_SURF_TYPE_2D:
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case RADEON_SURF_TYPE_CUBEMAP:
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if (surf->npix_z > 1 || surf->array_size > 1)
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case PIPE_TEXTURE_2D:
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case PIPE_TEXTURE_RECT:
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if (tex->depth0 > 1 || tex->array_size > 1)
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return -EINVAL;
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break;
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case RADEON_SURF_TYPE_3D:
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if (surf->array_size > 1)
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case PIPE_TEXTURE_3D:
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if (tex->array_size > 1)
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return -EINVAL;
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break;
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case RADEON_SURF_TYPE_1D_ARRAY:
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if (surf->npix_y > 1)
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case PIPE_TEXTURE_1D_ARRAY:
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if (tex->height0 > 1)
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return -EINVAL;
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/* fall through */
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case RADEON_SURF_TYPE_2D_ARRAY:
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if (surf->npix_z > 1)
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case PIPE_TEXTURE_CUBE:
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case PIPE_TEXTURE_2D_ARRAY:
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case PIPE_TEXTURE_CUBE_ARRAY:
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if (tex->depth0 > 1)
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return -EINVAL;
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break;
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default:
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@ -148,8 +144,9 @@ ADDR_HANDLE amdgpu_addr_create(struct amdgpu_winsys *ws)
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}
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static int compute_level(struct amdgpu_winsys *ws,
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const struct pipe_resource *tex,
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struct radeon_surf *surf, bool is_stencil,
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unsigned level, unsigned type, bool compressed,
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unsigned level, bool compressed,
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ADDR_COMPUTE_SURFACE_INFO_INPUT *AddrSurfInfoIn,
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ADDR_COMPUTE_SURFACE_INFO_OUTPUT *AddrSurfInfoOut,
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ADDR_COMPUTE_DCCINFO_INPUT *AddrDccIn,
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@ -161,15 +158,15 @@ static int compute_level(struct amdgpu_winsys *ws,
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ADDR_E_RETURNCODE ret;
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AddrSurfInfoIn->mipLevel = level;
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AddrSurfInfoIn->width = u_minify(surf->npix_x, level);
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AddrSurfInfoIn->height = u_minify(surf->npix_y, level);
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AddrSurfInfoIn->width = u_minify(tex->width0, level);
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AddrSurfInfoIn->height = u_minify(tex->height0, level);
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if (type == RADEON_SURF_TYPE_3D)
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AddrSurfInfoIn->numSlices = u_minify(surf->npix_z, level);
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else if (type == RADEON_SURF_TYPE_CUBEMAP)
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if (tex->target == PIPE_TEXTURE_3D)
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AddrSurfInfoIn->numSlices = u_minify(tex->depth0, level);
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else if (tex->target == PIPE_TEXTURE_CUBE)
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AddrSurfInfoIn->numSlices = 6;
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else
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AddrSurfInfoIn->numSlices = surf->array_size;
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AddrSurfInfoIn->numSlices = tex->array_size;
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if (level > 0) {
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/* Set the base level pitch. This is needed for calculation
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||||
|
@ -195,12 +192,12 @@ static int compute_level(struct amdgpu_winsys *ws,
|
|||
surf_level->offset = align64(surf->bo_size, AddrSurfInfoOut->baseAlign);
|
||||
surf_level->slice_size = AddrSurfInfoOut->sliceSize;
|
||||
surf_level->pitch_bytes = AddrSurfInfoOut->pitch * (is_stencil ? 1 : surf->bpe);
|
||||
surf_level->npix_x = u_minify(surf->npix_x, level);
|
||||
surf_level->npix_y = u_minify(surf->npix_y, level);
|
||||
surf_level->npix_z = u_minify(surf->npix_z, level);
|
||||
surf_level->npix_x = u_minify(tex->width0, level);
|
||||
surf_level->npix_y = u_minify(tex->height0, level);
|
||||
surf_level->npix_z = u_minify(tex->depth0, level);
|
||||
surf_level->nblk_x = AddrSurfInfoOut->pitch;
|
||||
surf_level->nblk_y = AddrSurfInfoOut->height;
|
||||
if (type == RADEON_SURF_TYPE_3D)
|
||||
if (tex->target == PIPE_TEXTURE_3D)
|
||||
surf_level->nblk_z = AddrSurfInfoOut->depth;
|
||||
else
|
||||
surf_level->nblk_z = 1;
|
||||
|
@ -310,10 +307,13 @@ static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
|
|||
}
|
||||
|
||||
static int amdgpu_surface_init(struct radeon_winsys *rws,
|
||||
const struct pipe_resource *tex,
|
||||
unsigned flags, unsigned bpe,
|
||||
enum radeon_surf_mode mode,
|
||||
struct radeon_surf *surf)
|
||||
{
|
||||
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
|
||||
unsigned level, mode, type;
|
||||
unsigned level;
|
||||
bool compressed;
|
||||
ADDR_COMPUTE_SURFACE_INFO_INPUT AddrSurfInfoIn = {0};
|
||||
ADDR_COMPUTE_SURFACE_INFO_OUTPUT AddrSurfInfoOut = {0};
|
||||
|
@ -325,7 +325,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
ADDR_TILEINFO AddrTileInfoOut = {0};
|
||||
int r;
|
||||
|
||||
r = amdgpu_surface_sanity(surf);
|
||||
r = amdgpu_surface_sanity(tex);
|
||||
if (r)
|
||||
return r;
|
||||
|
||||
|
@ -337,17 +337,20 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
AddrHtileOut.size = sizeof(ADDR_COMPUTE_HTILE_INFO_OUTPUT);
|
||||
AddrSurfInfoOut.pTileInfo = &AddrTileInfoOut;
|
||||
|
||||
type = RADEON_SURF_GET(surf->flags, TYPE);
|
||||
mode = RADEON_SURF_GET(surf->flags, MODE);
|
||||
surf->blk_w = util_format_get_blockwidth(tex->format);
|
||||
surf->blk_h = util_format_get_blockheight(tex->format);
|
||||
surf->bpe = bpe;
|
||||
surf->flags = flags;
|
||||
|
||||
compressed = surf->blk_w == 4 && surf->blk_h == 4;
|
||||
|
||||
/* MSAA and FMASK require 2D tiling. */
|
||||
if (surf->nsamples > 1 ||
|
||||
(surf->flags & RADEON_SURF_FMASK))
|
||||
if (tex->nr_samples > 1 ||
|
||||
(flags & RADEON_SURF_FMASK))
|
||||
mode = RADEON_SURF_MODE_2D;
|
||||
|
||||
/* DB doesn't support linear layouts. */
|
||||
if (surf->flags & (RADEON_SURF_Z_OR_SBUFFER) &&
|
||||
if (flags & (RADEON_SURF_Z_OR_SBUFFER) &&
|
||||
mode < RADEON_SURF_MODE_1D)
|
||||
mode = RADEON_SURF_MODE_1D;
|
||||
|
||||
|
@ -369,7 +372,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
/* The format must be set correctly for the allocation of compressed
|
||||
* textures to work. In other cases, setting the bpp is sufficient. */
|
||||
if (compressed) {
|
||||
switch (surf->bpe) {
|
||||
switch (bpe) {
|
||||
case 8:
|
||||
AddrSurfInfoIn.format = ADDR_FMT_BC1;
|
||||
break;
|
||||
|
@ -381,26 +384,27 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
}
|
||||
}
|
||||
else {
|
||||
AddrDccIn.bpp = AddrSurfInfoIn.bpp = surf->bpe * 8;
|
||||
AddrDccIn.bpp = AddrSurfInfoIn.bpp = bpe * 8;
|
||||
}
|
||||
|
||||
AddrDccIn.numSamples = AddrSurfInfoIn.numSamples = surf->nsamples;
|
||||
AddrDccIn.numSamples = AddrSurfInfoIn.numSamples =
|
||||
tex->nr_samples ? tex->nr_samples : 1;
|
||||
AddrSurfInfoIn.tileIndex = -1;
|
||||
|
||||
/* Set the micro tile type. */
|
||||
if (surf->flags & RADEON_SURF_SCANOUT)
|
||||
if (flags & RADEON_SURF_SCANOUT)
|
||||
AddrSurfInfoIn.tileType = ADDR_DISPLAYABLE;
|
||||
else if (surf->flags & RADEON_SURF_Z_OR_SBUFFER)
|
||||
else if (flags & RADEON_SURF_Z_OR_SBUFFER)
|
||||
AddrSurfInfoIn.tileType = ADDR_DEPTH_SAMPLE_ORDER;
|
||||
else
|
||||
AddrSurfInfoIn.tileType = ADDR_NON_DISPLAYABLE;
|
||||
|
||||
AddrSurfInfoIn.flags.color = !(surf->flags & RADEON_SURF_Z_OR_SBUFFER);
|
||||
AddrSurfInfoIn.flags.depth = (surf->flags & RADEON_SURF_ZBUFFER) != 0;
|
||||
AddrSurfInfoIn.flags.cube = type == RADEON_SURF_TYPE_CUBEMAP;
|
||||
AddrSurfInfoIn.flags.display = (surf->flags & RADEON_SURF_SCANOUT) != 0;
|
||||
AddrSurfInfoIn.flags.pow2Pad = surf->last_level > 0;
|
||||
AddrSurfInfoIn.flags.tcCompatible = (surf->flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
|
||||
AddrSurfInfoIn.flags.color = !(flags & RADEON_SURF_Z_OR_SBUFFER);
|
||||
AddrSurfInfoIn.flags.depth = (flags & RADEON_SURF_ZBUFFER) != 0;
|
||||
AddrSurfInfoIn.flags.cube = tex->target == PIPE_TEXTURE_CUBE;
|
||||
AddrSurfInfoIn.flags.display = (flags & RADEON_SURF_SCANOUT) != 0;
|
||||
AddrSurfInfoIn.flags.pow2Pad = tex->last_level > 0;
|
||||
AddrSurfInfoIn.flags.tcCompatible = (flags & RADEON_SURF_TC_COMPATIBLE_HTILE) != 0;
|
||||
|
||||
/* Only degrade the tile mode for space if TC-compatible HTILE hasn't been
|
||||
* requested, because TC-compatible HTILE requires 2D tiling.
|
||||
|
@ -414,13 +418,13 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
* driver team).
|
||||
*/
|
||||
AddrSurfInfoIn.flags.dccCompatible = ws->info.chip_class >= VI &&
|
||||
!(surf->flags & RADEON_SURF_Z_OR_SBUFFER) &&
|
||||
!(surf->flags & RADEON_SURF_DISABLE_DCC) &&
|
||||
!(flags & RADEON_SURF_Z_OR_SBUFFER) &&
|
||||
!(flags & RADEON_SURF_DISABLE_DCC) &&
|
||||
!compressed && AddrDccIn.numSamples <= 1 &&
|
||||
((surf->array_size == 1 && surf->npix_z == 1) ||
|
||||
surf->last_level == 0);
|
||||
((tex->array_size == 1 && tex->depth0 == 1) ||
|
||||
tex->last_level == 0);
|
||||
|
||||
AddrSurfInfoIn.flags.noStencil = (surf->flags & RADEON_SURF_SBUFFER) == 0;
|
||||
AddrSurfInfoIn.flags.noStencil = (flags & RADEON_SURF_SBUFFER) == 0;
|
||||
AddrSurfInfoIn.flags.compressZ = AddrSurfInfoIn.flags.depth;
|
||||
|
||||
/* noStencil = 0 can result in a depth part that is incompatible with
|
||||
|
@ -430,7 +434,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
* TODO: update addrlib to a newer version, remove this, and
|
||||
* use flags.matchStencilTileCfg = 1 as an alternative fix.
|
||||
*/
|
||||
if (surf->last_level > 0)
|
||||
if (tex->last_level > 0)
|
||||
AddrSurfInfoIn.flags.noStencil = 1;
|
||||
|
||||
/* Set preferred macrotile parameters. This is usually required
|
||||
|
@ -456,21 +460,21 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
* For now, just figure it out here.
|
||||
* Note that only 2D_TILE_THIN1 is handled here.
|
||||
*/
|
||||
assert(!(surf->flags & RADEON_SURF_Z_OR_SBUFFER));
|
||||
assert(!(flags & RADEON_SURF_Z_OR_SBUFFER));
|
||||
assert(AddrSurfInfoIn.tileMode == ADDR_TM_2D_TILED_THIN1);
|
||||
|
||||
if (ws->info.chip_class == SI) {
|
||||
if (AddrSurfInfoIn.tileType == ADDR_DISPLAYABLE) {
|
||||
if (surf->bpe == 2)
|
||||
if (bpe == 2)
|
||||
AddrSurfInfoIn.tileIndex = 11; /* 16bpp */
|
||||
else
|
||||
AddrSurfInfoIn.tileIndex = 12; /* 32bpp */
|
||||
} else {
|
||||
if (surf->bpe == 1)
|
||||
if (bpe == 1)
|
||||
AddrSurfInfoIn.tileIndex = 14; /* 8bpp */
|
||||
else if (surf->bpe == 2)
|
||||
else if (bpe == 2)
|
||||
AddrSurfInfoIn.tileIndex = 15; /* 16bpp */
|
||||
else if (surf->bpe == 4)
|
||||
else if (bpe == 4)
|
||||
AddrSurfInfoIn.tileIndex = 16; /* 32bpp */
|
||||
else
|
||||
AddrSurfInfoIn.tileIndex = 17; /* 64bpp (and 128bpp) */
|
||||
|
@ -494,8 +498,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
surf->htile_alignment = 1;
|
||||
|
||||
/* Calculate texture layout information. */
|
||||
for (level = 0; level <= surf->last_level; level++) {
|
||||
r = compute_level(ws, surf, false, level, type, compressed,
|
||||
for (level = 0; level <= tex->last_level; level++) {
|
||||
r = compute_level(ws, tex, surf, false, level, compressed,
|
||||
&AddrSurfInfoIn, &AddrSurfInfoOut,
|
||||
&AddrDccIn, &AddrDccOut, &AddrHtileIn, &AddrHtileOut);
|
||||
if (r)
|
||||
|
@ -521,7 +525,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
}
|
||||
|
||||
/* Calculate texture layout information for stencil. */
|
||||
if (surf->flags & RADEON_SURF_SBUFFER) {
|
||||
if (flags & RADEON_SURF_SBUFFER) {
|
||||
AddrSurfInfoIn.bpp = 8;
|
||||
AddrSurfInfoIn.flags.depth = 0;
|
||||
AddrSurfInfoIn.flags.stencil = 1;
|
||||
|
@ -529,8 +533,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
/* This will be ignored if AddrSurfInfoIn.pTileInfo is NULL. */
|
||||
AddrTileInfoIn.tileSplitBytes = surf->stencil_tile_split;
|
||||
|
||||
for (level = 0; level <= surf->last_level; level++) {
|
||||
r = compute_level(ws, surf, true, level, type, compressed,
|
||||
for (level = 0; level <= tex->last_level; level++) {
|
||||
r = compute_level(ws, tex, surf, true, level, compressed,
|
||||
&AddrSurfInfoIn, &AddrSurfInfoOut, &AddrDccIn, &AddrDccOut,
|
||||
NULL, NULL);
|
||||
if (r)
|
||||
|
@ -554,7 +558,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
* This is what addrlib does, but calling addrlib would be a lot more
|
||||
* complicated.
|
||||
*/
|
||||
if (surf->dcc_size && surf->last_level > 0) {
|
||||
if (surf->dcc_size && tex->last_level > 0) {
|
||||
surf->dcc_size = align64(surf->bo_size >> 8,
|
||||
ws->info.pipe_interleave_bytes *
|
||||
ws->info.num_tile_pipes);
|
||||
|
@ -563,7 +567,7 @@ static int amdgpu_surface_init(struct radeon_winsys *rws,
|
|||
/* Make sure HTILE covers the whole miptree, because the shader reads
|
||||
* TC-compatible HTILE even for levels where it's disabled by DB.
|
||||
*/
|
||||
if (surf->htile_size && surf->last_level)
|
||||
if (surf->htile_size && tex->last_level)
|
||||
surf->htile_size *= 2;
|
||||
|
||||
return 0;
|
||||
|
|
|
@ -28,7 +28,7 @@
|
|||
*/
|
||||
|
||||
#include "radeon_drm_winsys.h"
|
||||
|
||||
#include "util/u_format.h"
|
||||
#include <radeon_surface.h>
|
||||
|
||||
static unsigned cik_get_macro_tile_index(struct radeon_surf *surf)
|
||||
|
@ -97,23 +97,60 @@ static void surf_level_drm_to_winsys(struct radeon_surf_level *level_ws,
|
|||
}
|
||||
|
||||
static void surf_winsys_to_drm(struct radeon_surface *surf_drm,
|
||||
const struct pipe_resource *tex,
|
||||
unsigned flags, unsigned bpe,
|
||||
enum radeon_surf_mode mode,
|
||||
const struct radeon_surf *surf_ws)
|
||||
{
|
||||
int i;
|
||||
|
||||
memset(surf_drm, 0, sizeof(*surf_drm));
|
||||
|
||||
surf_drm->npix_x = surf_ws->npix_x;
|
||||
surf_drm->npix_y = surf_ws->npix_y;
|
||||
surf_drm->npix_z = surf_ws->npix_z;
|
||||
surf_drm->blk_w = surf_ws->blk_w;
|
||||
surf_drm->blk_h = surf_ws->blk_h;
|
||||
surf_drm->blk_d = surf_ws->blk_d;
|
||||
surf_drm->array_size = surf_ws->array_size;
|
||||
surf_drm->last_level = surf_ws->last_level;
|
||||
surf_drm->bpe = surf_ws->bpe;
|
||||
surf_drm->nsamples = surf_ws->nsamples;
|
||||
surf_drm->flags = surf_ws->flags;
|
||||
surf_drm->npix_x = tex->width0;
|
||||
surf_drm->npix_y = tex->height0;
|
||||
surf_drm->npix_z = tex->depth0;
|
||||
surf_drm->blk_w = util_format_get_blockwidth(tex->format);
|
||||
surf_drm->blk_h = util_format_get_blockheight(tex->format);
|
||||
surf_drm->blk_d = 1;
|
||||
surf_drm->array_size = 1;
|
||||
surf_drm->last_level = tex->last_level;
|
||||
surf_drm->bpe = bpe;
|
||||
surf_drm->nsamples = tex->nr_samples ? tex->nr_samples : 1;
|
||||
|
||||
surf_drm->flags = flags;
|
||||
surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, TYPE);
|
||||
surf_drm->flags = RADEON_SURF_CLR(surf_drm->flags, MODE);
|
||||
surf_drm->flags |= RADEON_SURF_SET(mode, MODE);
|
||||
|
||||
switch (tex->target) {
|
||||
case PIPE_TEXTURE_1D:
|
||||
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
|
||||
break;
|
||||
case PIPE_TEXTURE_RECT:
|
||||
case PIPE_TEXTURE_2D:
|
||||
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
|
||||
break;
|
||||
case PIPE_TEXTURE_3D:
|
||||
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
|
||||
break;
|
||||
case PIPE_TEXTURE_1D_ARRAY:
|
||||
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
|
||||
surf_drm->array_size = tex->array_size;
|
||||
break;
|
||||
case PIPE_TEXTURE_CUBE_ARRAY: /* cube array layout like 2d array */
|
||||
assert(tex->array_size % 6 == 0);
|
||||
/* fall through */
|
||||
case PIPE_TEXTURE_2D_ARRAY:
|
||||
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
|
||||
surf_drm->array_size = tex->array_size;
|
||||
break;
|
||||
case PIPE_TEXTURE_CUBE:
|
||||
surf_drm->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_CUBEMAP, TYPE);
|
||||
break;
|
||||
case PIPE_BUFFER:
|
||||
default:
|
||||
assert(0);
|
||||
}
|
||||
|
||||
surf_drm->bo_size = surf_ws->bo_size;
|
||||
surf_drm->bo_alignment = surf_ws->bo_alignment;
|
||||
|
@ -142,16 +179,9 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
|
|||
|
||||
memset(surf_ws, 0, sizeof(*surf_ws));
|
||||
|
||||
surf_ws->npix_x = surf_drm->npix_x;
|
||||
surf_ws->npix_y = surf_drm->npix_y;
|
||||
surf_ws->npix_z = surf_drm->npix_z;
|
||||
surf_ws->blk_w = surf_drm->blk_w;
|
||||
surf_ws->blk_h = surf_drm->blk_h;
|
||||
surf_ws->blk_d = surf_drm->blk_d;
|
||||
surf_ws->array_size = surf_drm->array_size;
|
||||
surf_ws->last_level = surf_drm->last_level;
|
||||
surf_ws->bpe = surf_drm->bpe;
|
||||
surf_ws->nsamples = surf_drm->nsamples;
|
||||
surf_ws->flags = surf_drm->flags;
|
||||
|
||||
surf_ws->bo_size = surf_drm->bo_size;
|
||||
|
@ -178,13 +208,16 @@ static void surf_drm_to_winsys(struct radeon_drm_winsys *ws,
|
|||
}
|
||||
|
||||
static int radeon_winsys_surface_init(struct radeon_winsys *rws,
|
||||
const struct pipe_resource *tex,
|
||||
unsigned flags, unsigned bpe,
|
||||
enum radeon_surf_mode mode,
|
||||
struct radeon_surf *surf_ws)
|
||||
{
|
||||
struct radeon_drm_winsys *ws = (struct radeon_drm_winsys*)rws;
|
||||
struct radeon_surface surf_drm;
|
||||
int r;
|
||||
|
||||
surf_winsys_to_drm(&surf_drm, surf_ws);
|
||||
surf_winsys_to_drm(&surf_drm, tex, flags, bpe, mode, surf_ws);
|
||||
|
||||
if (!(surf_ws->flags & RADEON_SURF_IMPORTED)) {
|
||||
r = radeon_surface_best(ws->surf_man, &surf_drm);
|
||||
|
|
Loading…
Reference in New Issue