2016-10-07 00:16:09 +01:00
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/*
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* Copyright © 2016 Dave Airlie
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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2021-04-10 02:24:05 +01:00
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#include "nir/nir_builder.h"
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2016-10-07 00:16:09 +01:00
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "sid.h"
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#include "vk_format.h"
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2021-04-10 02:24:05 +01:00
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static nir_ssa_def *
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radv_meta_build_resolve_srgb_conversion(nir_builder *b, nir_ssa_def *input)
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2017-08-06 00:56:17 +01:00
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{
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2021-04-10 02:24:05 +01:00
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unsigned i;
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nir_ssa_def *cmp[3];
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for (i = 0; i < 3; i++)
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cmp[i] = nir_flt(b, nir_channel(b, input, i), nir_imm_int(b, 0x3b4d2e1c));
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nir_ssa_def *ltvals[3];
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for (i = 0; i < 3; i++)
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ltvals[i] = nir_fmul(b, nir_channel(b, input, i), nir_imm_float(b, 12.92));
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nir_ssa_def *gtvals[3];
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for (i = 0; i < 3; i++) {
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gtvals[i] = nir_fpow(b, nir_channel(b, input, i), nir_imm_float(b, 1.0 / 2.4));
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gtvals[i] = nir_fmul(b, gtvals[i], nir_imm_float(b, 1.055));
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gtvals[i] = nir_fsub(b, gtvals[i], nir_imm_float(b, 0.055));
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}
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nir_ssa_def *comp[4];
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for (i = 0; i < 3; i++)
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comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
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comp[3] = nir_channels(b, input, 1 << 3);
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return nir_vec(b, comp, 4);
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2017-08-06 00:56:17 +01:00
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}
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2016-10-07 00:16:09 +01:00
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static nir_shader *
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2017-04-20 04:42:26 +01:00
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build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
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2016-10-07 00:16:09 +01:00
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{
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2021-04-10 02:24:05 +01:00
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const struct glsl_type *sampler_type =
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glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, false, GLSL_TYPE_FLOAT);
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const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, false, GLSL_TYPE_FLOAT);
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2022-03-30 11:52:58 +01:00
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nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs-%d-%s", samples,
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2021-12-06 18:21:11 +00:00
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is_integer ? "int" : (is_srgb ? "srgb" : "float"));
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2021-05-05 20:24:44 +01:00
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b.shader->info.workgroup_size[0] = 8;
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b.shader->info.workgroup_size[1] = 8;
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2021-04-10 02:24:05 +01:00
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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2021-10-15 18:58:22 +01:00
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img");
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2021-04-10 02:24:05 +01:00
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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2021-08-26 08:02:07 +01:00
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nir_ssa_def *global_id = get_global_ids(&b, 2);
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2021-04-10 02:24:05 +01:00
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2022-04-25 07:40:28 +01:00
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nir_ssa_def *src_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 0), .range = 8);
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2021-04-10 02:24:05 +01:00
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nir_ssa_def *dst_offset = nir_load_push_constant(&b, 2, 32, nir_imm_int(&b, 8), .range = 16);
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2021-08-26 08:02:07 +01:00
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nir_ssa_def *src_coord = nir_iadd(&b, global_id, src_offset);
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nir_ssa_def *dst_coord = nir_iadd(&b, global_id, dst_offset);
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2021-04-10 02:24:05 +01:00
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nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
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2021-08-26 08:02:07 +01:00
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radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img, color, src_coord);
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2021-04-10 02:24:05 +01:00
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nir_ssa_def *outval = nir_load_var(&b, color);
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if (is_srgb)
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outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
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2021-08-26 08:02:07 +01:00
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nir_ssa_def *img_coord = nir_vec4(&b, nir_channel(&b, dst_coord, 0),
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nir_channel(&b, dst_coord, 1),
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nir_ssa_undef(&b, 1, 32),
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nir_ssa_undef(&b, 1, 32));
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, img_coord,
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2021-07-30 13:25:26 +01:00
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nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0),
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.image_dim = GLSL_SAMPLER_DIM_2D);
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2021-04-10 02:24:05 +01:00
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return b.shader;
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2016-10-07 00:16:09 +01:00
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}
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2019-05-22 08:42:12 +01:00
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enum {
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2021-04-10 02:24:05 +01:00
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DEPTH_RESOLVE,
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STENCIL_RESOLVE,
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2019-05-22 08:42:12 +01:00
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};
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static const char *
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2019-10-15 08:20:48 +01:00
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get_resolve_mode_str(VkResolveModeFlagBits resolve_mode)
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2019-05-22 08:42:12 +01:00
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{
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2021-04-10 02:24:05 +01:00
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switch (resolve_mode) {
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2022-03-30 09:28:56 +01:00
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case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
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2021-04-10 02:24:05 +01:00
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return "zero";
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2022-03-30 09:28:56 +01:00
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case VK_RESOLVE_MODE_AVERAGE_BIT:
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2021-04-10 02:24:05 +01:00
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return "average";
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2022-03-30 09:28:56 +01:00
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case VK_RESOLVE_MODE_MIN_BIT:
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2021-04-10 02:24:05 +01:00
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return "min";
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2022-03-30 09:28:56 +01:00
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case VK_RESOLVE_MODE_MAX_BIT:
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2021-04-10 02:24:05 +01:00
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return "max";
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default:
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unreachable("invalid resolve mode");
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}
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2019-05-22 08:42:12 +01:00
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}
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static nir_shader *
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2021-04-10 02:24:05 +01:00
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build_depth_stencil_resolve_compute_shader(struct radv_device *dev, int samples, int index,
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VkResolveModeFlagBits resolve_mode)
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2019-05-22 08:42:12 +01:00
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{
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2021-04-10 02:24:05 +01:00
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const struct glsl_type *sampler_type =
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glsl_sampler_type(GLSL_SAMPLER_DIM_MS, false, true, GLSL_TYPE_FLOAT);
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const struct glsl_type *img_type = glsl_image_type(GLSL_SAMPLER_DIM_2D, true, GLSL_TYPE_FLOAT);
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2022-03-30 11:52:58 +01:00
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nir_builder b = radv_meta_init_shader(dev, MESA_SHADER_COMPUTE, "meta_resolve_cs_%s-%s-%d",
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2021-12-06 18:21:11 +00:00
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index == DEPTH_RESOLVE ? "depth" : "stencil",
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get_resolve_mode_str(resolve_mode), samples);
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2021-05-05 20:24:44 +01:00
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b.shader->info.workgroup_size[0] = 8;
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b.shader->info.workgroup_size[1] = 8;
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2021-04-10 02:24:05 +01:00
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform, sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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2021-10-15 18:58:22 +01:00
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_image, img_type, "out_img");
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2021-04-10 02:24:05 +01:00
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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2021-08-26 08:02:07 +01:00
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nir_ssa_def *img_coord = get_global_ids(&b, 3);
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2021-04-10 02:24:05 +01:00
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nir_ssa_def *input_img_deref = &nir_build_deref_var(&b, input_img)->dest.ssa;
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nir_alu_type type = index == DEPTH_RESOLVE ? nir_type_float32 : nir_type_uint32;
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nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
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tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex->op = nir_texop_txf_ms;
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tex->src[0].src_type = nir_tex_src_coord;
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tex->src[0].src = nir_src_for_ssa(img_coord);
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tex->src[1].src_type = nir_tex_src_ms_index;
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tex->src[1].src = nir_src_for_ssa(nir_imm_int(&b, 0));
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tex->src[2].src_type = nir_tex_src_texture_deref;
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tex->src[2].src = nir_src_for_ssa(input_img_deref);
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tex->dest_type = type;
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tex->is_array = true;
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tex->coord_components = 3;
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nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex->instr);
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nir_ssa_def *outval = &tex->dest.ssa;
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2022-03-30 09:28:56 +01:00
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if (resolve_mode != VK_RESOLVE_MODE_SAMPLE_ZERO_BIT) {
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2021-04-10 02:24:05 +01:00
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for (int i = 1; i < samples; i++) {
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nir_tex_instr *tex_add = nir_tex_instr_create(b.shader, 3);
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tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
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tex_add->op = nir_texop_txf_ms;
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tex_add->src[0].src_type = nir_tex_src_coord;
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tex_add->src[0].src = nir_src_for_ssa(img_coord);
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tex_add->src[1].src_type = nir_tex_src_ms_index;
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tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(&b, i));
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tex_add->src[2].src_type = nir_tex_src_texture_deref;
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tex_add->src[2].src = nir_src_for_ssa(input_img_deref);
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tex_add->dest_type = type;
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tex_add->is_array = true;
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tex_add->coord_components = 3;
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nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
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nir_builder_instr_insert(&b, &tex_add->instr);
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switch (resolve_mode) {
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2022-03-30 09:28:56 +01:00
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case VK_RESOLVE_MODE_AVERAGE_BIT:
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2021-04-10 02:24:05 +01:00
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assert(index == DEPTH_RESOLVE);
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outval = nir_fadd(&b, outval, &tex_add->dest.ssa);
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break;
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2022-03-30 09:28:56 +01:00
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case VK_RESOLVE_MODE_MIN_BIT:
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2021-04-10 02:24:05 +01:00
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if (index == DEPTH_RESOLVE)
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outval = nir_fmin(&b, outval, &tex_add->dest.ssa);
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else
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outval = nir_umin(&b, outval, &tex_add->dest.ssa);
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break;
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2022-03-30 09:28:56 +01:00
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case VK_RESOLVE_MODE_MAX_BIT:
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2021-04-10 02:24:05 +01:00
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if (index == DEPTH_RESOLVE)
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outval = nir_fmax(&b, outval, &tex_add->dest.ssa);
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else
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outval = nir_umax(&b, outval, &tex_add->dest.ssa);
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break;
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default:
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unreachable("invalid resolve mode");
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}
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}
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2022-03-30 09:28:56 +01:00
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if (resolve_mode == VK_RESOLVE_MODE_AVERAGE_BIT)
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2021-04-10 02:24:05 +01:00
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outval = nir_fdiv(&b, outval, nir_imm_float(&b, samples));
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}
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nir_ssa_def *coord = nir_vec4(&b, nir_channel(&b, img_coord, 0), nir_channel(&b, img_coord, 1),
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2021-08-26 10:32:10 +01:00
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nir_channel(&b, img_coord, 2), nir_ssa_undef(&b, 1, 32));
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2021-04-10 02:24:05 +01:00
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nir_image_deref_store(&b, &nir_build_deref_var(&b, output_img)->dest.ssa, coord,
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2021-07-30 13:25:26 +01:00
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nir_ssa_undef(&b, 1, 32), outval, nir_imm_int(&b, 0),
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.image_dim = GLSL_SAMPLER_DIM_2D, .image_array = true);
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2021-04-10 02:24:05 +01:00
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return b.shader;
|
2019-05-22 08:42:12 +01:00
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}
|
2016-10-07 00:16:09 +01:00
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static VkResult
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create_layout(struct radv_device *device)
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{
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2021-04-10 02:24:05 +01:00
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VkResult result;
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/*
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* two descriptors one for the image being sampled
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* one for the buffer being written.
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*/
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]){
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{.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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{.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL},
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}};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_compute.ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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|
VkPipelineLayoutCreateInfo pl_create_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
|
|
|
|
.setLayoutCount = 1,
|
|
|
|
.pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
|
|
|
|
.pushConstantRangeCount = 1,
|
|
|
|
.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
|
|
|
|
&device->meta_state.alloc,
|
|
|
|
&device->meta_state.resolve_compute.p_layout);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
return VK_SUCCESS;
|
2016-10-07 00:16:09 +01:00
|
|
|
fail:
|
2021-04-10 02:24:05 +01:00
|
|
|
return result;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
static VkResult
|
2021-04-10 02:24:05 +01:00
|
|
|
create_resolve_pipeline(struct radv_device *device, int samples, bool is_integer, bool is_srgb,
|
|
|
|
VkPipeline *pipeline)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
VkResult result;
|
|
|
|
|
|
|
|
mtx_lock(&device->meta_state.mtx);
|
|
|
|
if (*pipeline) {
|
|
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
nir_shader *cs = build_resolve_compute_shader(device, is_integer, is_srgb, samples);
|
|
|
|
|
|
|
|
/* compute shader */
|
|
|
|
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
|
|
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.module = vk_shader_module_handle_from_nir(cs),
|
|
|
|
.pName = "main",
|
|
|
|
.pSpecializationInfo = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
VkComputePipelineCreateInfo vk_pipeline_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
|
|
|
.stage = pipeline_shader_stage,
|
|
|
|
.flags = 0,
|
|
|
|
.layout = device->meta_state.resolve_compute.p_layout,
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
|
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
|
|
|
|
&vk_pipeline_info, NULL, pipeline);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
ralloc_free(cs);
|
|
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
|
|
return VK_SUCCESS;
|
2016-10-07 00:16:09 +01:00
|
|
|
fail:
|
2021-04-10 02:24:05 +01:00
|
|
|
ralloc_free(cs);
|
|
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
|
|
return result;
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2019-05-22 08:42:12 +01:00
|
|
|
static VkResult
|
2021-04-10 02:24:05 +01:00
|
|
|
create_depth_stencil_resolve_pipeline(struct radv_device *device, int samples, int index,
|
|
|
|
VkResolveModeFlagBits resolve_mode, VkPipeline *pipeline)
|
2019-05-22 08:42:12 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
VkResult result;
|
|
|
|
|
|
|
|
mtx_lock(&device->meta_state.mtx);
|
|
|
|
if (*pipeline) {
|
|
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
|
|
return VK_SUCCESS;
|
|
|
|
}
|
|
|
|
|
|
|
|
nir_shader *cs =
|
|
|
|
build_depth_stencil_resolve_compute_shader(device, samples, index, resolve_mode);
|
|
|
|
|
|
|
|
/* compute shader */
|
|
|
|
VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
|
|
|
|
.stage = VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
.module = vk_shader_module_handle_from_nir(cs),
|
|
|
|
.pName = "main",
|
|
|
|
.pSpecializationInfo = NULL,
|
|
|
|
};
|
|
|
|
|
|
|
|
VkComputePipelineCreateInfo vk_pipeline_info = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
|
|
|
|
.stage = pipeline_shader_stage,
|
|
|
|
.flags = 0,
|
|
|
|
.layout = device->meta_state.resolve_compute.p_layout,
|
|
|
|
};
|
|
|
|
|
|
|
|
result = radv_CreateComputePipelines(radv_device_to_handle(device),
|
|
|
|
radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
|
|
|
|
&vk_pipeline_info, NULL, pipeline);
|
|
|
|
if (result != VK_SUCCESS)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
ralloc_free(cs);
|
|
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
|
|
return VK_SUCCESS;
|
2019-05-22 08:42:12 +01:00
|
|
|
fail:
|
2021-04-10 02:24:05 +01:00
|
|
|
ralloc_free(cs);
|
|
|
|
mtx_unlock(&device->meta_state.mtx);
|
|
|
|
return result;
|
2019-05-22 08:42:12 +01:00
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
VkResult
|
2018-08-13 23:07:57 +01:00
|
|
|
radv_device_init_meta_resolve_compute_state(struct radv_device *device, bool on_demand)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
VkResult res;
|
|
|
|
|
|
|
|
res = create_layout(device);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
if (on_demand)
|
|
|
|
return VK_SUCCESS;
|
|
|
|
|
|
|
|
for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
|
|
|
|
uint32_t samples = 1 << i;
|
|
|
|
|
|
|
|
res = create_resolve_pipeline(device, samples, false, false,
|
|
|
|
&state->resolve_compute.rc[i].pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
res = create_resolve_pipeline(device, samples, true, false,
|
|
|
|
&state->resolve_compute.rc[i].i_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
res = create_resolve_pipeline(device, samples, false, true,
|
|
|
|
&state->resolve_compute.rc[i].srgb_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
res = create_depth_stencil_resolve_pipeline(
|
2022-03-30 09:28:56 +01:00
|
|
|
device, samples, DEPTH_RESOLVE, VK_RESOLVE_MODE_AVERAGE_BIT,
|
2021-04-10 02:24:05 +01:00
|
|
|
&state->resolve_compute.depth[i].average_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, samples, DEPTH_RESOLVE,
|
2022-03-30 09:28:56 +01:00
|
|
|
VK_RESOLVE_MODE_MAX_BIT,
|
2021-04-10 02:24:05 +01:00
|
|
|
&state->resolve_compute.depth[i].max_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, samples, DEPTH_RESOLVE,
|
2022-03-30 09:28:56 +01:00
|
|
|
VK_RESOLVE_MODE_MIN_BIT,
|
2021-04-10 02:24:05 +01:00
|
|
|
&state->resolve_compute.depth[i].min_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, samples, STENCIL_RESOLVE,
|
2022-03-30 09:28:56 +01:00
|
|
|
VK_RESOLVE_MODE_MAX_BIT,
|
2021-04-10 02:24:05 +01:00
|
|
|
&state->resolve_compute.stencil[i].max_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, samples, STENCIL_RESOLVE,
|
2022-03-30 09:28:56 +01:00
|
|
|
VK_RESOLVE_MODE_MIN_BIT,
|
2021-04-10 02:24:05 +01:00
|
|
|
&state->resolve_compute.stencil[i].min_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
|
2022-03-30 09:28:56 +01:00
|
|
|
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT,
|
2021-04-10 02:24:05 +01:00
|
|
|
&state->resolve_compute.depth_zero_pipeline);
|
|
|
|
if (res != VK_SUCCESS)
|
2022-07-20 13:49:38 +01:00
|
|
|
return res;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
2022-07-20 13:49:38 +01:00
|
|
|
return create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
|
|
|
|
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT,
|
|
|
|
&state->resolve_compute.stencil_zero_pipeline);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
void
|
|
|
|
radv_device_finish_meta_resolve_compute_state(struct radv_device *device)
|
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device), state->resolve_compute.rc[i].pipeline,
|
|
|
|
&state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device), state->resolve_compute.rc[i].i_pipeline,
|
|
|
|
&state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->resolve_compute.rc[i].srgb_pipeline, &state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->resolve_compute.depth[i].average_pipeline, &state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->resolve_compute.depth[i].max_pipeline, &state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->resolve_compute.depth[i].min_pipeline, &state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->resolve_compute.stencil[i].max_pipeline, &state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device),
|
|
|
|
state->resolve_compute.stencil[i].min_pipeline, &state->alloc);
|
|
|
|
}
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device), state->resolve_compute.depth_zero_pipeline,
|
|
|
|
&state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyPipeline(radv_device_to_handle(device), state->resolve_compute.stencil_zero_pipeline,
|
|
|
|
&state->alloc);
|
|
|
|
|
|
|
|
radv_DestroyDescriptorSetLayout(radv_device_to_handle(device), state->resolve_compute.ds_layout,
|
|
|
|
&state->alloc);
|
|
|
|
radv_DestroyPipelineLayout(radv_device_to_handle(device), state->resolve_compute.p_layout,
|
|
|
|
&state->alloc);
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
|
2019-05-27 16:42:36 +01:00
|
|
|
static VkPipeline *
|
2021-04-10 02:24:05 +01:00
|
|
|
radv_get_resolve_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview)
|
2019-05-27 16:42:36 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_device *device = cmd_buffer->device;
|
|
|
|
struct radv_meta_state *state = &device->meta_state;
|
|
|
|
uint32_t samples = src_iview->image->info.samples;
|
|
|
|
uint32_t samples_log2 = ffs(samples) - 1;
|
|
|
|
VkPipeline *pipeline;
|
|
|
|
|
2022-03-25 21:14:19 +00:00
|
|
|
if (vk_format_is_int(src_iview->vk.format))
|
2021-04-10 02:24:05 +01:00
|
|
|
pipeline = &state->resolve_compute.rc[samples_log2].i_pipeline;
|
2022-03-25 21:14:19 +00:00
|
|
|
else if (vk_format_is_srgb(src_iview->vk.format))
|
2021-04-10 02:24:05 +01:00
|
|
|
pipeline = &state->resolve_compute.rc[samples_log2].srgb_pipeline;
|
|
|
|
else
|
|
|
|
pipeline = &state->resolve_compute.rc[samples_log2].pipeline;
|
|
|
|
|
|
|
|
if (!*pipeline) {
|
|
|
|
VkResult ret;
|
|
|
|
|
2022-03-25 21:14:19 +00:00
|
|
|
ret = create_resolve_pipeline(device, samples, vk_format_is_int(src_iview->vk.format),
|
|
|
|
vk_format_is_srgb(src_iview->vk.format), pipeline);
|
2021-04-10 02:24:05 +01:00
|
|
|
if (ret != VK_SUCCESS) {
|
|
|
|
cmd_buffer->record_result = ret;
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return pipeline;
|
2019-05-27 16:42:36 +01:00
|
|
|
}
|
|
|
|
|
2017-05-04 04:01:35 +01:00
|
|
|
static void
|
2021-04-10 02:24:05 +01:00
|
|
|
emit_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview,
|
|
|
|
struct radv_image_view *dest_iview, const VkOffset2D *src_offset,
|
|
|
|
const VkOffset2D *dest_offset, const VkExtent2D *resolve_extent)
|
2017-05-04 04:01:35 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_device *device = cmd_buffer->device;
|
|
|
|
VkPipeline *pipeline;
|
|
|
|
|
|
|
|
radv_meta_push_descriptor_set(
|
|
|
|
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.resolve_compute.p_layout,
|
|
|
|
0, /* set */
|
|
|
|
2, /* descriptorWriteCount */
|
|
|
|
(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 0,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
|
|
.pImageInfo =
|
|
|
|
(VkDescriptorImageInfo[]){
|
|
|
|
{.sampler = VK_NULL_HANDLE,
|
|
|
|
.imageView = radv_image_view_to_handle(src_iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL},
|
|
|
|
}},
|
|
|
|
{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 1,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.pImageInfo = (VkDescriptorImageInfo[]){
|
|
|
|
{
|
2017-05-04 04:01:35 +01:00
|
|
|
.sampler = VK_NULL_HANDLE,
|
2021-04-10 02:24:05 +01:00
|
|
|
.imageView = radv_image_view_to_handle(dest_iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}}});
|
|
|
|
|
|
|
|
pipeline = radv_get_resolve_pipeline(cmd_buffer, src_iview);
|
|
|
|
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
|
|
*pipeline);
|
|
|
|
|
|
|
|
unsigned push_constants[4] = {
|
|
|
|
src_offset->x,
|
|
|
|
src_offset->y,
|
|
|
|
dest_offset->x,
|
|
|
|
dest_offset->y,
|
|
|
|
};
|
|
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
device->meta_state.resolve_compute.p_layout, VK_SHADER_STAGE_COMPUTE_BIT,
|
|
|
|
0, 16, push_constants);
|
|
|
|
radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height, 1);
|
2017-05-04 04:01:35 +01:00
|
|
|
}
|
|
|
|
|
2019-05-22 08:42:12 +01:00
|
|
|
static void
|
2021-04-10 02:24:05 +01:00
|
|
|
emit_depth_stencil_resolve(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *src_iview,
|
|
|
|
struct radv_image_view *dest_iview, const VkExtent3D *resolve_extent,
|
|
|
|
VkImageAspectFlags aspects, VkResolveModeFlagBits resolve_mode)
|
2019-05-22 08:42:12 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_device *device = cmd_buffer->device;
|
|
|
|
const uint32_t samples = src_iview->image->info.samples;
|
|
|
|
const uint32_t samples_log2 = ffs(samples) - 1;
|
|
|
|
VkPipeline *pipeline;
|
|
|
|
|
|
|
|
radv_meta_push_descriptor_set(
|
|
|
|
cmd_buffer, VK_PIPELINE_BIND_POINT_COMPUTE, device->meta_state.resolve_compute.p_layout,
|
|
|
|
0, /* set */
|
|
|
|
2, /* descriptorWriteCount */
|
|
|
|
(VkWriteDescriptorSet[]){{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 0,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
|
|
|
|
.pImageInfo =
|
|
|
|
(VkDescriptorImageInfo[]){
|
|
|
|
{.sampler = VK_NULL_HANDLE,
|
|
|
|
.imageView = radv_image_view_to_handle(src_iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL},
|
|
|
|
}},
|
|
|
|
{.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
|
|
|
|
.dstBinding = 1,
|
|
|
|
.dstArrayElement = 0,
|
|
|
|
.descriptorCount = 1,
|
|
|
|
.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
|
|
|
|
.pImageInfo = (VkDescriptorImageInfo[]){
|
|
|
|
{
|
2019-05-22 08:42:12 +01:00
|
|
|
.sampler = VK_NULL_HANDLE,
|
2021-04-10 02:24:05 +01:00
|
|
|
.imageView = radv_image_view_to_handle(dest_iview),
|
|
|
|
.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
|
|
|
|
},
|
|
|
|
}}});
|
|
|
|
|
|
|
|
switch (resolve_mode) {
|
2022-03-30 09:28:56 +01:00
|
|
|
case VK_RESOLVE_MODE_SAMPLE_ZERO_BIT:
|
2021-04-10 02:24:05 +01:00
|
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
|
|
pipeline = &device->meta_state.resolve_compute.depth_zero_pipeline;
|
|
|
|
else
|
|
|
|
pipeline = &device->meta_state.resolve_compute.stencil_zero_pipeline;
|
|
|
|
break;
|
2022-03-30 09:28:56 +01:00
|
|
|
case VK_RESOLVE_MODE_AVERAGE_BIT:
|
2021-04-10 02:24:05 +01:00
|
|
|
assert(aspects == VK_IMAGE_ASPECT_DEPTH_BIT);
|
|
|
|
pipeline = &device->meta_state.resolve_compute.depth[samples_log2].average_pipeline;
|
|
|
|
break;
|
2022-03-30 09:28:56 +01:00
|
|
|
case VK_RESOLVE_MODE_MIN_BIT:
|
2021-04-10 02:24:05 +01:00
|
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
|
|
pipeline = &device->meta_state.resolve_compute.depth[samples_log2].min_pipeline;
|
|
|
|
else
|
|
|
|
pipeline = &device->meta_state.resolve_compute.stencil[samples_log2].min_pipeline;
|
|
|
|
break;
|
2022-03-30 09:28:56 +01:00
|
|
|
case VK_RESOLVE_MODE_MAX_BIT:
|
2021-04-10 02:24:05 +01:00
|
|
|
if (aspects == VK_IMAGE_ASPECT_DEPTH_BIT)
|
|
|
|
pipeline = &device->meta_state.resolve_compute.depth[samples_log2].max_pipeline;
|
|
|
|
else
|
|
|
|
pipeline = &device->meta_state.resolve_compute.stencil[samples_log2].max_pipeline;
|
|
|
|
break;
|
|
|
|
default:
|
|
|
|
unreachable("invalid resolve mode");
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!*pipeline) {
|
|
|
|
int index = aspects == VK_IMAGE_ASPECT_DEPTH_BIT ? DEPTH_RESOLVE : STENCIL_RESOLVE;
|
|
|
|
VkResult ret;
|
|
|
|
|
|
|
|
ret = create_depth_stencil_resolve_pipeline(device, samples, index, resolve_mode, pipeline);
|
|
|
|
if (ret != VK_SUCCESS) {
|
|
|
|
cmd_buffer->record_result = ret;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
|
|
|
|
*pipeline);
|
|
|
|
|
|
|
|
radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height,
|
|
|
|
resolve_extent->depth);
|
2019-05-22 08:42:12 +01:00
|
|
|
}
|
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
void
|
|
|
|
radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *src_image,
|
|
|
|
VkFormat src_format, VkImageLayout src_image_layout,
|
|
|
|
struct radv_image *dest_image, VkFormat dest_format,
|
2022-03-30 09:28:56 +01:00
|
|
|
VkImageLayout dest_image_layout, const VkImageResolve2 *region)
|
2016-10-07 00:16:09 +01:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_meta_saved_state saved_state;
|
|
|
|
|
|
|
|
radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout, region);
|
|
|
|
|
|
|
|
/* For partial resolves, DCC should be decompressed before resolving
|
|
|
|
* because the metadata is re-initialized to the uncompressed after.
|
|
|
|
*/
|
radv: abstract queue family away from queue family index.
If we introduce another queue type (video decode) we can have a
disconnect between the RADV_QUEUE_ enum and the API queue_family_index.
currently the driver has
GENERAL, COMPUTE, TRANSFER which would end up at QFI 0, 1, <nothing>
since we don't create transfer.
Now if I add VDEC we get
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, 1, <nothing>, 2
or if you do nocompute
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, <nothing>, <nothing>, 1
This means we have to add a remapping table between the API qfi
and the internal qf.
This patches tries to do that, in theory right now it just adds
overhead, but I'd like to exercise these paths.
v2: add radv_queue_ring abstraction, and pass physical device in,
as it makes adding uvd later easier.
v3: rename, and drop one direction as unneeded now, drop queue_family_index
from cmd_buffers.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13687>
2021-11-05 06:03:24 +00:00
|
|
|
uint32_t queue_mask = radv_image_queue_family_mask(dest_image, cmd_buffer->qf,
|
|
|
|
cmd_buffer->qf);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
2021-05-06 13:38:56 +01:00
|
|
|
if (!radv_image_use_dcc_image_stores(cmd_buffer->device, dest_image) &&
|
|
|
|
radv_layout_dcc_compressed(cmd_buffer->device, dest_image, region->dstSubresource.mipLevel,
|
2021-05-06 11:20:37 +01:00
|
|
|
dest_image_layout, false, queue_mask) &&
|
2021-04-10 02:24:05 +01:00
|
|
|
(region->dstOffset.x || region->dstOffset.y || region->dstOffset.z ||
|
|
|
|
region->extent.width != dest_image->info.width ||
|
|
|
|
region->extent.height != dest_image->info.height ||
|
|
|
|
region->extent.depth != dest_image->info.depth)) {
|
|
|
|
radv_decompress_dcc(cmd_buffer, dest_image,
|
|
|
|
&(VkImageSubresourceRange){
|
|
|
|
.aspectMask = region->dstSubresource.aspectMask,
|
|
|
|
.baseMipLevel = region->dstSubresource.mipLevel,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = region->dstSubresource.baseArrayLayer,
|
|
|
|
.layerCount = region->dstSubresource.layerCount,
|
|
|
|
});
|
|
|
|
}
|
|
|
|
|
|
|
|
radv_meta_save(
|
|
|
|
&saved_state, cmd_buffer,
|
|
|
|
RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_CONSTANTS | RADV_META_SAVE_DESCRIPTORS);
|
|
|
|
|
|
|
|
assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
|
|
|
|
assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
|
|
|
|
assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
|
|
|
|
|
|
|
|
const uint32_t src_base_layer =
|
|
|
|
radv_meta_get_iview_layer(src_image, ®ion->srcSubresource, ®ion->srcOffset);
|
|
|
|
|
|
|
|
const uint32_t dest_base_layer =
|
|
|
|
radv_meta_get_iview_layer(dest_image, ®ion->dstSubresource, ®ion->dstOffset);
|
|
|
|
|
2022-06-05 04:33:37 +01:00
|
|
|
const struct VkExtent3D extent = vk_image_sanitize_extent(&src_image->vk, region->extent);
|
|
|
|
const struct VkOffset3D srcOffset = vk_image_sanitize_offset(&src_image->vk, region->srcOffset);
|
|
|
|
const struct VkOffset3D dstOffset = vk_image_sanitize_offset(&dest_image->vk, region->dstOffset);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
for (uint32_t layer = 0; layer < region->srcSubresource.layerCount; ++layer) {
|
|
|
|
|
|
|
|
struct radv_image_view src_iview;
|
|
|
|
radv_image_view_init(&src_iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo){
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(src_image),
|
|
|
|
.viewType = radv_meta_get_view_type(src_image),
|
|
|
|
.format = src_format,
|
|
|
|
.subresourceRange =
|
|
|
|
{
|
|
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
|
|
.baseMipLevel = region->srcSubresource.mipLevel,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = src_base_layer + layer,
|
|
|
|
.layerCount = 1,
|
|
|
|
},
|
|
|
|
},
|
2022-05-03 07:51:31 +01:00
|
|
|
0, NULL);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
struct radv_image_view dest_iview;
|
|
|
|
radv_image_view_init(&dest_iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo){
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(dest_image),
|
|
|
|
.viewType = radv_meta_get_view_type(dest_image),
|
|
|
|
.format = vk_to_non_srgb_format(dest_format),
|
|
|
|
.subresourceRange =
|
|
|
|
{
|
|
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
|
|
.baseMipLevel = region->dstSubresource.mipLevel,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = dest_base_layer + layer,
|
|
|
|
.layerCount = 1,
|
|
|
|
},
|
|
|
|
},
|
2022-05-03 07:51:31 +01:00
|
|
|
0, NULL);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
emit_resolve(cmd_buffer, &src_iview, &dest_iview, &(VkOffset2D){srcOffset.x, srcOffset.y},
|
|
|
|
&(VkOffset2D){dstOffset.x, dstOffset.y},
|
|
|
|
&(VkExtent2D){extent.width, extent.height});
|
2021-09-29 08:46:46 +01:00
|
|
|
|
|
|
|
radv_image_view_finish(&src_iview);
|
|
|
|
radv_image_view_finish(&dest_iview);
|
2021-04-10 02:24:05 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
|
|
|
|
|
|
|
if (!radv_image_use_dcc_image_stores(cmd_buffer->device, dest_image) &&
|
2021-05-06 11:20:37 +01:00
|
|
|
radv_layout_dcc_compressed(cmd_buffer->device, dest_image, region->dstSubresource.mipLevel,
|
|
|
|
dest_image_layout, false, queue_mask)) {
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE;
|
|
|
|
|
|
|
|
VkImageSubresourceRange range = {
|
|
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
|
|
.baseMipLevel = region->dstSubresource.mipLevel,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = dest_base_layer,
|
|
|
|
.layerCount = region->dstSubresource.layerCount,
|
|
|
|
};
|
|
|
|
|
|
|
|
cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dest_image, &range, 0xffffffff);
|
|
|
|
}
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
2017-05-04 04:02:08 +01:00
|
|
|
|
|
|
|
/**
|
|
|
|
* Emit any needed resolves for the current subpass.
|
|
|
|
*/
|
|
|
|
void
|
|
|
|
radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
|
|
|
|
{
|
2022-03-28 14:54:12 +01:00
|
|
|
struct vk_framebuffer *fb = cmd_buffer->state.framebuffer;
|
2021-04-10 02:24:05 +01:00
|
|
|
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
|
|
|
|
struct radv_subpass_barrier barrier;
|
|
|
|
uint32_t layer_count = fb->layers;
|
|
|
|
|
|
|
|
if (subpass->view_mask)
|
|
|
|
layer_count = util_last_bit(subpass->view_mask);
|
|
|
|
|
|
|
|
/* Resolves happen before the end-of-subpass barriers get executed, so
|
|
|
|
* we have to make the attachment shader-readable.
|
|
|
|
*/
|
2022-03-30 09:28:56 +01:00
|
|
|
barrier.src_stage_mask = VK_PIPELINE_STAGE_2_COLOR_ATTACHMENT_OUTPUT_BIT;
|
|
|
|
barrier.src_access_mask = VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT;
|
|
|
|
barrier.dst_access_mask = VK_ACCESS_2_SHADER_READ_BIT | VK_ACCESS_2_SHADER_WRITE_BIT;
|
2021-11-08 08:03:19 +00:00
|
|
|
radv_emit_subpass_barrier(cmd_buffer, &barrier);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
for (uint32_t i = 0; i < subpass->color_count; ++i) {
|
|
|
|
struct radv_subpass_attachment src_att = subpass->color_attachments[i];
|
|
|
|
struct radv_subpass_attachment dst_att = subpass->resolve_attachments[i];
|
|
|
|
|
|
|
|
if (dst_att.attachment == VK_ATTACHMENT_UNUSED)
|
|
|
|
continue;
|
|
|
|
|
|
|
|
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
|
|
|
|
struct radv_image_view *dst_iview = cmd_buffer->state.attachments[dst_att.attachment].iview;
|
|
|
|
|
2022-03-30 09:28:56 +01:00
|
|
|
VkImageResolve2 region = {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2,
|
2021-04-10 02:24:05 +01:00
|
|
|
.extent = (VkExtent3D){fb->width, fb->height, 1},
|
|
|
|
.srcSubresource =
|
|
|
|
(VkImageSubresourceLayers){
|
|
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
2022-03-25 21:14:19 +00:00
|
|
|
.mipLevel = src_iview->vk.base_mip_level,
|
|
|
|
.baseArrayLayer = src_iview->vk.base_array_layer,
|
2021-04-10 02:24:05 +01:00
|
|
|
.layerCount = layer_count,
|
|
|
|
},
|
|
|
|
.dstSubresource =
|
|
|
|
(VkImageSubresourceLayers){
|
|
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
2022-03-25 21:14:19 +00:00
|
|
|
.mipLevel = dst_iview->vk.base_mip_level,
|
|
|
|
.baseArrayLayer = dst_iview->vk.base_array_layer,
|
2021-04-10 02:24:05 +01:00
|
|
|
.layerCount = layer_count,
|
|
|
|
},
|
|
|
|
.srcOffset = (VkOffset3D){0, 0, 0},
|
|
|
|
.dstOffset = (VkOffset3D){0, 0, 0},
|
|
|
|
};
|
|
|
|
|
2022-03-25 21:14:19 +00:00
|
|
|
radv_meta_resolve_compute_image(cmd_buffer, src_iview->image, src_iview->vk.format,
|
|
|
|
src_att.layout, dst_iview->image, dst_iview->vk.format,
|
2021-04-10 02:24:05 +01:00
|
|
|
dst_att.layout, ®ion);
|
|
|
|
}
|
|
|
|
|
|
|
|
cmd_buffer->state.flush_bits |=
|
|
|
|
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
|
2022-03-30 09:28:56 +01:00
|
|
|
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
|
2017-05-04 04:02:08 +01:00
|
|
|
}
|
2019-05-22 08:42:12 +01:00
|
|
|
|
|
|
|
void
|
|
|
|
radv_depth_stencil_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer,
|
2021-04-10 02:24:05 +01:00
|
|
|
VkImageAspectFlags aspects,
|
|
|
|
VkResolveModeFlagBits resolve_mode)
|
2019-05-22 08:42:12 +01:00
|
|
|
{
|
2022-03-28 14:54:12 +01:00
|
|
|
struct vk_framebuffer *fb = cmd_buffer->state.framebuffer;
|
2021-04-10 02:24:05 +01:00
|
|
|
const struct radv_subpass *subpass = cmd_buffer->state.subpass;
|
|
|
|
struct radv_meta_saved_state saved_state;
|
|
|
|
uint32_t layer_count = fb->layers;
|
|
|
|
|
|
|
|
if (subpass->view_mask)
|
|
|
|
layer_count = util_last_bit(subpass->view_mask);
|
|
|
|
|
|
|
|
/* Resolves happen before the end-of-subpass barriers get executed, so
|
|
|
|
* we have to make the attachment shader-readable.
|
|
|
|
*/
|
|
|
|
cmd_buffer->state.flush_bits |=
|
2022-03-30 09:28:56 +01:00
|
|
|
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT, NULL) |
|
|
|
|
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT, NULL) |
|
|
|
|
radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
struct radv_subpass_attachment src_att = *subpass->depth_stencil_attachment;
|
|
|
|
struct radv_image_view *src_iview = cmd_buffer->state.attachments[src_att.attachment].iview;
|
|
|
|
struct radv_image *src_image = src_iview->image;
|
|
|
|
|
2022-03-30 09:28:56 +01:00
|
|
|
VkImageResolve2 region = {0};
|
|
|
|
region.sType = VK_STRUCTURE_TYPE_IMAGE_RESOLVE_2;
|
2021-04-10 02:24:05 +01:00
|
|
|
region.srcSubresource.aspectMask = aspects;
|
|
|
|
region.srcSubresource.mipLevel = 0;
|
2022-03-25 21:14:19 +00:00
|
|
|
region.srcSubresource.baseArrayLayer = src_iview->vk.base_array_layer;
|
2021-04-10 02:24:05 +01:00
|
|
|
region.srcSubresource.layerCount = layer_count;
|
|
|
|
|
|
|
|
radv_decompress_resolve_src(cmd_buffer, src_image, src_att.layout, ®ion);
|
|
|
|
|
|
|
|
radv_meta_save(&saved_state, cmd_buffer,
|
|
|
|
RADV_META_SAVE_COMPUTE_PIPELINE | RADV_META_SAVE_DESCRIPTORS);
|
|
|
|
|
|
|
|
struct radv_subpass_attachment dest_att = *subpass->ds_resolve_attachment;
|
|
|
|
struct radv_image_view *dst_iview = cmd_buffer->state.attachments[dest_att.attachment].iview;
|
|
|
|
struct radv_image *dst_image = dst_iview->image;
|
|
|
|
|
|
|
|
struct radv_image_view tsrc_iview;
|
|
|
|
radv_image_view_init(&tsrc_iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo){
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(src_image),
|
|
|
|
.viewType = radv_meta_get_view_type(src_image),
|
2022-03-25 21:14:19 +00:00
|
|
|
.format = src_iview->vk.format,
|
2021-04-10 02:24:05 +01:00
|
|
|
.subresourceRange =
|
|
|
|
{
|
|
|
|
.aspectMask = aspects,
|
2022-03-25 21:14:19 +00:00
|
|
|
.baseMipLevel = src_iview->vk.base_mip_level,
|
2021-04-10 02:24:05 +01:00
|
|
|
.levelCount = 1,
|
2022-03-25 21:14:19 +00:00
|
|
|
.baseArrayLayer = src_iview->vk.base_array_layer,
|
2021-04-10 02:24:05 +01:00
|
|
|
.layerCount = layer_count,
|
|
|
|
},
|
|
|
|
},
|
2022-05-03 07:51:31 +01:00
|
|
|
0, NULL);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
struct radv_image_view tdst_iview;
|
|
|
|
radv_image_view_init(&tdst_iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo){
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(dst_image),
|
|
|
|
.viewType = radv_meta_get_view_type(dst_image),
|
2022-03-25 21:14:19 +00:00
|
|
|
.format = dst_iview->vk.format,
|
2021-04-10 02:24:05 +01:00
|
|
|
.subresourceRange =
|
|
|
|
{
|
|
|
|
.aspectMask = aspects,
|
2022-03-25 21:14:19 +00:00
|
|
|
.baseMipLevel = dst_iview->vk.base_mip_level,
|
2021-04-10 02:24:05 +01:00
|
|
|
.levelCount = 1,
|
2022-03-25 21:14:19 +00:00
|
|
|
.baseArrayLayer = dst_iview->vk.base_array_layer,
|
2021-04-10 02:24:05 +01:00
|
|
|
.layerCount = layer_count,
|
|
|
|
},
|
|
|
|
},
|
2022-05-03 07:51:31 +01:00
|
|
|
0, NULL);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
emit_depth_stencil_resolve(cmd_buffer, &tsrc_iview, &tdst_iview,
|
|
|
|
&(VkExtent3D){fb->width, fb->height, layer_count}, aspects,
|
|
|
|
resolve_mode);
|
|
|
|
|
|
|
|
cmd_buffer->state.flush_bits |=
|
|
|
|
RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_INV_VCACHE |
|
2022-03-30 09:28:56 +01:00
|
|
|
radv_src_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_WRITE_BIT, NULL);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
VkImageLayout layout = cmd_buffer->state.attachments[dest_att.attachment].current_layout;
|
radv: abstract queue family away from queue family index.
If we introduce another queue type (video decode) we can have a
disconnect between the RADV_QUEUE_ enum and the API queue_family_index.
currently the driver has
GENERAL, COMPUTE, TRANSFER which would end up at QFI 0, 1, <nothing>
since we don't create transfer.
Now if I add VDEC we get
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, 1, <nothing>, 2
or if you do nocompute
GENERAL, COMPUTE, TRANSFER, VDEC at QFI 0, <nothing>, <nothing>, 1
This means we have to add a remapping table between the API qfi
and the internal qf.
This patches tries to do that, in theory right now it just adds
overhead, but I'd like to exercise these paths.
v2: add radv_queue_ring abstraction, and pass physical device in,
as it makes adding uvd later easier.
v3: rename, and drop one direction as unneeded now, drop queue_family_index
from cmd_buffers.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13687>
2021-11-05 06:03:24 +00:00
|
|
|
uint32_t queue_mask = radv_image_queue_family_mask(dst_image, cmd_buffer->qf,
|
|
|
|
cmd_buffer->qf);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
if (radv_layout_is_htile_compressed(cmd_buffer->device, dst_image, layout, false, queue_mask)) {
|
|
|
|
VkImageSubresourceRange range = {0};
|
|
|
|
range.aspectMask = aspects;
|
2022-03-25 21:14:19 +00:00
|
|
|
range.baseMipLevel = dst_iview->vk.base_mip_level;
|
2021-04-10 02:24:05 +01:00
|
|
|
range.levelCount = 1;
|
2022-03-25 21:14:19 +00:00
|
|
|
range.baseArrayLayer = dst_iview->vk.base_array_layer;
|
2021-04-10 02:24:05 +01:00
|
|
|
range.layerCount = layer_count;
|
|
|
|
|
|
|
|
uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, dst_image);
|
|
|
|
|
|
|
|
cmd_buffer->state.flush_bits |= radv_clear_htile(cmd_buffer, dst_image, &range, htile_value);
|
|
|
|
}
|
|
|
|
|
2021-09-29 08:46:46 +01:00
|
|
|
radv_image_view_finish(&tsrc_iview);
|
|
|
|
radv_image_view_finish(&tdst_iview);
|
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
radv_meta_restore(&saved_state, cmd_buffer);
|
2019-05-22 08:42:12 +01:00
|
|
|
}
|