2016-10-07 00:16:09 +01:00
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/*
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* Copyright © 2016 Dave Airlie
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include <assert.h>
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#include <stdbool.h>
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#include "radv_meta.h"
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#include "radv_private.h"
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#include "nir/nir_builder.h"
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#include "sid.h"
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#include "vk_format.h"
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static nir_shader *
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2017-04-20 04:42:26 +01:00
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build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
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2016-10-07 00:16:09 +01:00
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{
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nir_builder b;
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char name[64];
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const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
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false,
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false,
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GLSL_TYPE_FLOAT);
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const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
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false,
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false,
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GLSL_TYPE_FLOAT);
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2017-04-20 04:42:26 +01:00
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snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
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2016-10-07 00:16:09 +01:00
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nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
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2016-10-13 01:41:23 +01:00
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b.shader->info->name = ralloc_strdup(b.shader, name);
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b.shader->info->cs.local_size[0] = 16;
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b.shader->info->cs.local_size[1] = 16;
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b.shader->info->cs.local_size[2] = 1;
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2016-10-07 00:16:09 +01:00
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nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
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sampler_type, "s_tex");
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input_img->data.descriptor_set = 0;
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input_img->data.binding = 0;
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nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
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img_type, "out_img");
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output_img->data.descriptor_set = 0;
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output_img->data.binding = 1;
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nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
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nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
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nir_ssa_def *block_size = nir_imm_ivec4(&b,
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2016-10-13 01:41:23 +01:00
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b.shader->info->cs.local_size[0],
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b.shader->info->cs.local_size[1],
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b.shader->info->cs.local_size[2], 0);
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2016-10-07 00:16:09 +01:00
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nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
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nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
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src_offset->num_components = 2;
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nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
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nir_builder_instr_insert(&b, &src_offset->instr);
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nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
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dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
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dst_offset->num_components = 2;
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nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
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nir_builder_instr_insert(&b, &dst_offset->instr);
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2017-03-08 22:26:13 +00:00
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nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
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2017-05-03 04:23:04 +01:00
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nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
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2016-10-07 00:16:09 +01:00
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2017-05-03 04:23:04 +01:00
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radv_meta_build_resolve_shader_core(&b, is_integer, is_srgb, samples,
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input_img, color, img_coord);
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2017-04-20 04:42:26 +01:00
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2017-05-03 04:23:04 +01:00
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nir_ssa_def *outval = nir_load_var(&b, color);
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2016-10-07 00:16:09 +01:00
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nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
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nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_store);
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store->src[0] = nir_src_for_ssa(coord);
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store->src[1] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
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2017-05-03 04:23:04 +01:00
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store->src[2] = nir_src_for_ssa(outval);
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2016-10-07 00:16:09 +01:00
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store->variables[0] = nir_deref_var_create(store, output_img);
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nir_builder_instr_insert(&b, &store->instr);
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return b.shader;
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}
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static VkResult
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create_layout(struct radv_device *device)
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{
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VkResult result;
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/*
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* two descriptors one for the image being sampled
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* one for the buffer being written.
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*/
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VkDescriptorSetLayoutCreateInfo ds_create_info = {
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.sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
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2017-04-13 23:26:59 +01:00
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.flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
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2016-10-07 00:16:09 +01:00
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.bindingCount = 2,
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.pBindings = (VkDescriptorSetLayoutBinding[]) {
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{
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.binding = 0,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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{
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.binding = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.descriptorCount = 1,
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.stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
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.pImmutableSamplers = NULL
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},
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}
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};
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result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
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&ds_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_compute.ds_layout);
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if (result != VK_SUCCESS)
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goto fail;
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VkPipelineLayoutCreateInfo pl_create_info = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
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.setLayoutCount = 1,
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.pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
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.pushConstantRangeCount = 1,
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.pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
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};
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result = radv_CreatePipelineLayout(radv_device_to_handle(device),
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&pl_create_info,
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&device->meta_state.alloc,
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&device->meta_state.resolve_compute.p_layout);
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if (result != VK_SUCCESS)
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goto fail;
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return VK_SUCCESS;
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fail:
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return result;
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}
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static VkResult
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create_resolve_pipeline(struct radv_device *device,
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int samples,
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bool is_integer,
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2017-04-20 04:42:26 +01:00
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bool is_srgb,
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2016-10-07 00:16:09 +01:00
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VkPipeline *pipeline)
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{
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VkResult result;
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struct radv_shader_module cs = { .nir = NULL };
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2017-04-20 04:42:26 +01:00
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cs.nir = build_resolve_compute_shader(device, is_integer, is_srgb, samples);
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2016-10-07 00:16:09 +01:00
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/* compute shader */
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VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
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.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
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.stage = VK_SHADER_STAGE_COMPUTE_BIT,
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.module = radv_shader_module_to_handle(&cs),
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.pName = "main",
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.pSpecializationInfo = NULL,
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};
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VkComputePipelineCreateInfo vk_pipeline_info = {
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.sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
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.stage = pipeline_shader_stage,
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.flags = 0,
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.layout = device->meta_state.resolve_compute.p_layout,
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};
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result = radv_CreateComputePipelines(radv_device_to_handle(device),
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radv_pipeline_cache_to_handle(&device->meta_state.cache),
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1, &vk_pipeline_info, NULL,
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pipeline);
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if (result != VK_SUCCESS)
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goto fail;
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ralloc_free(cs.nir);
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return VK_SUCCESS;
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fail:
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ralloc_free(cs.nir);
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return result;
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}
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VkResult
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radv_device_init_meta_resolve_compute_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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VkResult res;
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memset(&device->meta_state.resolve_compute, 0, sizeof(device->meta_state.resolve_compute));
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res = create_layout(device);
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if (res != VK_SUCCESS)
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return res;
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
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uint32_t samples = 1 << i;
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2017-04-20 04:42:26 +01:00
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res = create_resolve_pipeline(device, samples, false, false,
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2016-10-07 00:16:09 +01:00
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&state->resolve_compute.rc[i].pipeline);
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2017-04-20 04:42:26 +01:00
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res = create_resolve_pipeline(device, samples, true, false,
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2016-10-07 00:16:09 +01:00
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&state->resolve_compute.rc[i].i_pipeline);
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2017-04-20 04:42:26 +01:00
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res = create_resolve_pipeline(device, samples, false, true,
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&state->resolve_compute.rc[i].srgb_pipeline);
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2016-10-07 00:16:09 +01:00
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}
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return res;
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}
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void
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radv_device_finish_meta_resolve_compute_state(struct radv_device *device)
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{
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struct radv_meta_state *state = &device->meta_state;
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for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->resolve_compute.rc[i].pipeline,
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&state->alloc);
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->resolve_compute.rc[i].i_pipeline,
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&state->alloc);
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2017-04-20 04:42:26 +01:00
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radv_DestroyPipeline(radv_device_to_handle(device),
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state->resolve_compute.rc[i].srgb_pipeline,
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&state->alloc);
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2016-10-07 00:16:09 +01:00
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}
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radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
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state->resolve_compute.ds_layout,
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&state->alloc);
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radv_DestroyPipelineLayout(radv_device_to_handle(device),
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state->resolve_compute.p_layout,
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&state->alloc);
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}
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2017-05-04 04:01:35 +01:00
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static void
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emit_resolve(struct radv_cmd_buffer *cmd_buffer,
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struct radv_image_view *src_iview,
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struct radv_image_view *dest_iview,
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const VkOffset2D *src_offset,
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const VkOffset2D *dest_offset,
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const VkExtent2D *resolve_extent)
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{
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struct radv_device *device = cmd_buffer->device;
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const uint32_t samples = src_iview->image->info.samples;
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const uint32_t samples_log2 = ffs(samples) - 1;
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radv_meta_push_descriptor_set(cmd_buffer,
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VK_PIPELINE_BIND_POINT_COMPUTE,
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device->meta_state.resolve_compute.p_layout,
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0, /* set */
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2, /* descriptorWriteCount */
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(VkWriteDescriptorSet[]) {
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 0,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
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.pImageInfo = (VkDescriptorImageInfo[]) {
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{
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.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(src_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL },
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}
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},
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{
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.sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
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.dstBinding = 1,
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.dstArrayElement = 0,
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.descriptorCount = 1,
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.descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
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.pImageInfo = (VkDescriptorImageInfo[]) {
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{
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.sampler = VK_NULL_HANDLE,
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.imageView = radv_image_view_to_handle(dest_iview),
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.imageLayout = VK_IMAGE_LAYOUT_GENERAL,
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},
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}
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}
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});
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VkPipeline pipeline;
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if (vk_format_is_int(src_iview->image->vk_format))
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pipeline = device->meta_state.resolve_compute.rc[samples_log2].i_pipeline;
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else if (vk_format_is_srgb(src_iview->image->vk_format))
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pipeline = device->meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
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else
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pipeline = device->meta_state.resolve_compute.rc[samples_log2].pipeline;
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if (cmd_buffer->state.compute_pipeline != radv_pipeline_from_handle(pipeline)) {
|
|
|
|
radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
VK_PIPELINE_BIND_POINT_COMPUTE, pipeline);
|
|
|
|
}
|
|
|
|
|
|
|
|
unsigned push_constants[4] = {
|
|
|
|
src_offset->x,
|
|
|
|
src_offset->y,
|
|
|
|
dest_offset->x,
|
|
|
|
dest_offset->y,
|
|
|
|
};
|
|
|
|
radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
|
|
|
|
device->meta_state.resolve_compute.p_layout,
|
|
|
|
VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
|
|
|
|
push_constants);
|
|
|
|
radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height, 1);
|
|
|
|
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
|
|
|
|
struct radv_image *src_image,
|
|
|
|
VkImageLayout src_image_layout,
|
|
|
|
struct radv_image *dest_image,
|
|
|
|
VkImageLayout dest_image_layout,
|
|
|
|
uint32_t region_count,
|
|
|
|
const VkImageResolve *regions)
|
|
|
|
{
|
|
|
|
struct radv_meta_saved_compute_state saved_state;
|
2017-03-06 23:31:48 +00:00
|
|
|
|
|
|
|
for (uint32_t r = 0; r < region_count; ++r) {
|
|
|
|
const VkImageResolve *region = ®ions[r];
|
|
|
|
const uint32_t src_base_layer =
|
|
|
|
radv_meta_get_iview_layer(src_image, ®ion->srcSubresource,
|
|
|
|
®ion->srcOffset);
|
|
|
|
VkImageSubresourceRange range;
|
|
|
|
range.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT;
|
|
|
|
range.baseMipLevel = region->srcSubresource.mipLevel;
|
|
|
|
range.levelCount = 1;
|
|
|
|
range.baseArrayLayer = src_base_layer;
|
|
|
|
range.layerCount = region->srcSubresource.layerCount;
|
|
|
|
radv_fast_clear_flush_image_inplace(cmd_buffer, src_image, &range);
|
|
|
|
}
|
|
|
|
|
2016-10-07 00:16:09 +01:00
|
|
|
radv_meta_save_compute(&saved_state, cmd_buffer, 16);
|
|
|
|
|
|
|
|
for (uint32_t r = 0; r < region_count; ++r) {
|
|
|
|
const VkImageResolve *region = ®ions[r];
|
|
|
|
|
|
|
|
assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
|
|
|
|
assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
|
|
|
|
assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
|
|
|
|
|
|
|
|
const uint32_t src_base_layer =
|
|
|
|
radv_meta_get_iview_layer(src_image, ®ion->srcSubresource,
|
|
|
|
®ion->srcOffset);
|
|
|
|
|
|
|
|
const uint32_t dest_base_layer =
|
|
|
|
radv_meta_get_iview_layer(dest_image, ®ion->dstSubresource,
|
|
|
|
®ion->dstOffset);
|
|
|
|
|
|
|
|
const struct VkExtent3D extent =
|
|
|
|
radv_sanitize_image_extent(src_image->type, region->extent);
|
|
|
|
const struct VkOffset3D srcOffset =
|
|
|
|
radv_sanitize_image_offset(src_image->type, region->srcOffset);
|
|
|
|
const struct VkOffset3D dstOffset =
|
|
|
|
radv_sanitize_image_offset(dest_image->type, region->dstOffset);
|
|
|
|
|
|
|
|
for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
|
|
|
|
++layer) {
|
|
|
|
|
|
|
|
struct radv_image_view src_iview;
|
|
|
|
radv_image_view_init(&src_iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo) {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(src_image),
|
|
|
|
.viewType = radv_meta_get_view_type(src_image),
|
|
|
|
.format = src_image->vk_format,
|
|
|
|
.subresourceRange = {
|
|
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
|
|
.baseMipLevel = region->srcSubresource.mipLevel,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = src_base_layer + layer,
|
|
|
|
.layerCount = 1,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
cmd_buffer, VK_IMAGE_USAGE_SAMPLED_BIT);
|
|
|
|
|
|
|
|
struct radv_image_view dest_iview;
|
|
|
|
radv_image_view_init(&dest_iview, cmd_buffer->device,
|
|
|
|
&(VkImageViewCreateInfo) {
|
|
|
|
.sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
|
|
|
|
.image = radv_image_to_handle(dest_image),
|
|
|
|
.viewType = radv_meta_get_view_type(dest_image),
|
|
|
|
.format = dest_image->vk_format,
|
|
|
|
.subresourceRange = {
|
|
|
|
.aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
|
|
|
|
.baseMipLevel = region->dstSubresource.mipLevel,
|
|
|
|
.levelCount = 1,
|
|
|
|
.baseArrayLayer = dest_base_layer + layer,
|
|
|
|
.layerCount = 1,
|
|
|
|
},
|
|
|
|
},
|
|
|
|
cmd_buffer, VK_IMAGE_USAGE_STORAGE_BIT);
|
|
|
|
|
2017-05-04 04:01:35 +01:00
|
|
|
emit_resolve(cmd_buffer,
|
|
|
|
&src_iview,
|
|
|
|
&dest_iview,
|
|
|
|
&(VkOffset2D) {srcOffset.x, srcOffset.y },
|
|
|
|
&(VkOffset2D) {dstOffset.x, dstOffset.y },
|
|
|
|
&(VkExtent2D) {extent.width, extent.height });
|
2016-10-07 00:16:09 +01:00
|
|
|
}
|
|
|
|
}
|
|
|
|
radv_meta_restore_compute(&saved_state, cmd_buffer, 16);
|
|
|
|
}
|