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radv: Simplify the meta init fail path 

Move most of the the cleanup into radv_device_init_meta.

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17652>
This commit is contained in:
Konstantin Seurer 2022-07-20 14:49:38 +02:00 committed by Marge Bot
parent b06e5535c0
commit 1a95d43e55
17 changed files with 90 additions and 173 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/amd/vulkan/radv_acceleration_structure.c
View File

@ -1924,7 +1924,6 @@ create_build_pipeline(struct radv_device *device, nir_shader *shader, unsigned p
VkResult result = radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
&device->meta_state.alloc, layout);
if (result != VK_SUCCESS) {
radv_device_finish_accel_struct_build_state(device);
ralloc_free(shader);
return result;
}
@ -1949,7 +1948,6 @@ create_build_pipeline(struct radv_device *device, nir_shader *shader, unsigned p
&pipeline_info, &device->meta_state.alloc, pipeline);
if (result != VK_SUCCESS) {
radv_device_finish_accel_struct_build_state(device);
ralloc_free(shader);
return result;
}

11
src/amd/vulkan/radv_device_generated_commands.c
View File

@ -956,7 +956,7 @@ radv_device_init_dgc_prepare_state(struct radv_device *device)
&device->meta_state.alloc,
&device->meta_state.dgc_prepare.ds_layout);
if (result != VK_SUCCESS)
goto fail;
goto cleanup;
const VkPipelineLayoutCreateInfo leaf_pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
@ -971,7 +971,7 @@ radv_device_init_dgc_prepare_state(struct radv_device *device)
&device->meta_state.alloc,
&device->meta_state.dgc_prepare.p_layout);
if (result != VK_SUCCESS)
goto fail;
goto cleanup;
VkPipelineShaderStageCreateInfo shader_stage = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
@ -992,12 +992,9 @@ radv_device_init_dgc_prepare_state(struct radv_device *device)
radv_device_to_handle(device), radv_pipeline_cache_to_handle(&device->meta_state.cache), 1,
&pipeline_info, &device->meta_state.alloc, &device->meta_state.dgc_prepare.pipeline);
if (result != VK_SUCCESS)
goto fail;
goto cleanup;
ralloc_free(cs);
return VK_SUCCESS;
fail:
radv_device_finish_dgc_prepare_state(device);
cleanup:
ralloc_free(cs);
return result;
}

32
src/amd/vulkan/radv_meta.c
View File

@ -641,36 +641,38 @@ radv_device_init_meta(struct radv_device *device)
return VK_SUCCESS;
fail_dgc:
radv_device_finish_meta_etc_decode_state(device);
radv_device_finish_dgc_prepare_state(device);
fail_etc_decode:
radv_device_finish_meta_fmask_copy_state(device);
radv_device_finish_meta_etc_decode_state(device);
fail_fmask_copy:
radv_device_finish_accel_struct_build_state(device);
radv_device_finish_meta_fmask_copy_state(device);
fail_accel_struct_build:
radv_device_finish_meta_fmask_expand_state(device);
radv_device_finish_accel_struct_build_state(device);
fail_fmask_expand:
radv_device_finish_meta_resolve_fragment_state(device);
radv_device_finish_meta_fmask_expand_state(device);
fail_resolve_fragment:
radv_device_finish_meta_resolve_compute_state(device);
radv_device_finish_meta_resolve_fragment_state(device);
fail_resolve_compute:
radv_device_finish_meta_fast_clear_flush_state(device);
radv_device_finish_meta_resolve_compute_state(device);
fail_fast_clear:
radv_device_finish_meta_query_state(device);
radv_device_finish_meta_fast_clear_flush_state(device);
fail_query:
radv_device_finish_meta_buffer_state(device);
radv_device_finish_meta_query_state(device);
fail_buffer:
radv_device_finish_meta_depth_decomp_state(device);
radv_device_finish_meta_buffer_state(device);
fail_depth_decomp:
radv_device_finish_meta_bufimage_state(device);
radv_device_finish_meta_depth_decomp_state(device);
fail_bufimage:
radv_device_finish_meta_blit2d_state(device);
radv_device_finish_meta_bufimage_state(device);
fail_blit2d:
radv_device_finish_meta_blit_state(device);
radv_device_finish_meta_blit2d_state(device);
fail_blit:
radv_device_finish_meta_resolve_state(device);
radv_device_finish_meta_blit_state(device);
fail_resolve:
radv_device_finish_meta_clear_state(device);
radv_device_finish_meta_resolve_state(device);
fail_clear:
radv_device_finish_meta_clear_state(device);
mtx_destroy(&device->meta_state.mtx);
radv_pipeline_cache_finish(&device->meta_state.cache);
return result;

15
src/amd/vulkan/radv_meta_blit.c
View File

@ -932,7 +932,7 @@ radv_device_init_meta_blit_state(struct radv_device *device, bool on_demand)
radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_layout_info,
&device->meta_state.alloc, &device->meta_state.blit.ds_layout);
if (result != VK_SUCCESS)
goto fail;
return result;
const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
@ -947,20 +947,15 @@ radv_device_init_meta_blit_state(struct radv_device *device, bool on_demand)
&device->meta_state.alloc,
&device->meta_state.blit.pipeline_layout);
if (result != VK_SUCCESS)
goto fail;
return result;
result = radv_device_init_meta_blit_color(device, on_demand);
if (result != VK_SUCCESS)
goto fail;
return result;
result = radv_device_init_meta_blit_depth(device, on_demand);
if (result != VK_SUCCESS)
goto fail;
return result;
result = radv_device_init_meta_blit_stencil(device, on_demand);
fail:
if (result != VK_SUCCESS)
radv_device_finish_meta_blit_state(device);
return result;
return radv_device_init_meta_blit_stencil(device, on_demand);
}

12
src/amd/vulkan/radv_meta_blit2d.c
View File

@ -1131,7 +1131,7 @@ radv_device_init_meta_blit2d_state(struct radv_device *device, bool on_demand)
result = meta_blit2d_create_pipe_layout(device, src, log2_samples);
if (result != VK_SUCCESS)
goto fail;
return result;
if (on_demand)
continue;
@ -1140,22 +1140,18 @@ radv_device_init_meta_blit2d_state(struct radv_device *device, bool on_demand)
result = blit2d_init_color_pipeline(device, src, radv_fs_key_format_exemplars[j],
log2_samples);
if (result != VK_SUCCESS)
goto fail;
return result;
}
result = blit2d_init_depth_only_pipeline(device, src, log2_samples);
if (result != VK_SUCCESS)
goto fail;
return result;
result = blit2d_init_stencil_only_pipeline(device, src, log2_samples);
if (result != VK_SUCCESS)
goto fail;
return result;
}
}
return VK_SUCCESS;
fail:
radv_device_finish_meta_blit2d_state(device);
return result;
}

1
src/amd/vulkan/radv_meta_buffer.c
View File

@ -148,7 +148,6 @@ radv_device_init_meta_buffer_state(struct radv_device *device)
ralloc_free(copy_cs);
return VK_SUCCESS;
fail:
radv_device_finish_meta_buffer_state(device);
ralloc_free(fill_cs);
ralloc_free(copy_cs);
return result;

29
src/amd/vulkan/radv_meta_bufimage.c
View File

@ -1174,48 +1174,33 @@ radv_device_init_meta_bufimage_state(struct radv_device *device)
result = radv_device_init_meta_itob_state(device);
if (result != VK_SUCCESS)
goto fail_itob;
return result;
result = radv_device_init_meta_btoi_state(device);
if (result != VK_SUCCESS)
goto fail_btoi;
return result;
result = radv_device_init_meta_btoi_r32g32b32_state(device);
if (result != VK_SUCCESS)
goto fail_btoi_r32g32b32;
return result;
result = radv_device_init_meta_itoi_state(device);
if (result != VK_SUCCESS)
goto fail_itoi;
return result;
result = radv_device_init_meta_itoi_r32g32b32_state(device);
if (result != VK_SUCCESS)
goto fail_itoi_r32g32b32;
return result;
result = radv_device_init_meta_cleari_state(device);
if (result != VK_SUCCESS)
goto fail_cleari;
return result;
result = radv_device_init_meta_cleari_r32g32b32_state(device);
if (result != VK_SUCCESS)
goto fail_cleari_r32g32b32;
return result;
return VK_SUCCESS;
fail_cleari_r32g32b32:
radv_device_finish_meta_cleari_r32g32b32_state(device);
fail_cleari:
radv_device_finish_meta_cleari_state(device);
fail_itoi_r32g32b32:
radv_device_finish_meta_itoi_r32g32b32_state(device);
fail_itoi:
radv_device_finish_meta_itoi_state(device);
fail_btoi_r32g32b32:
radv_device_finish_meta_btoi_r32g32b32_state(device);
fail_btoi:
radv_device_finish_meta_btoi_state(device);
fail_itob:
radv_device_finish_meta_itob_state(device);
return result;
}
static void

30
src/amd/vulkan/radv_meta_clear.c
View File

@ -991,8 +991,6 @@ init_meta_clear_htile_mask_state(struct radv_device *device)
radv_pipeline_cache_to_handle(&state->cache), 1,
&pipeline_info, NULL, &state->clear_htile_mask_pipeline);
ralloc_free(cs);
return result;
fail:
ralloc_free(cs);
return result;
@ -1146,7 +1144,7 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
&device->meta_state.alloc,
&device->meta_state.clear_color_p_layout);
if (res != VK_SUCCESS)
goto fail;
return res;
VkPipelineLayoutCreateInfo pl_depth_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
@ -1159,7 +1157,7 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
&device->meta_state.alloc,
&device->meta_state.clear_depth_p_layout);
if (res != VK_SUCCESS)
goto fail;
return res;
VkPipelineLayoutCreateInfo pl_depth_unrestricted_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
@ -1172,15 +1170,15 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
&pl_depth_unrestricted_create_info, &device->meta_state.alloc,
&device->meta_state.clear_depth_unrestricted_p_layout);
if (res != VK_SUCCESS)
goto fail;
return res;
res = init_meta_clear_htile_mask_state(device);
if (res != VK_SUCCESS)
goto fail;
return res;
res = init_meta_clear_dcc_comp_to_single_state(device);
if (res != VK_SUCCESS)
goto fail;
return res;
if (on_demand)
return VK_SUCCESS;
@ -1197,7 +1195,7 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
res = create_color_pipeline(device, samples, 0, format,
&state->color_clear[i][0].color_pipelines[fs_key]);
if (res != VK_SUCCESS)
goto fail;
return res;
}
}
for (uint32_t i = 0; i < ARRAY_SIZE(state->ds_clear); ++i) {
@ -1207,42 +1205,38 @@ radv_device_init_meta_clear_state(struct radv_device *device, bool on_demand)
res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, samples, j, false,
&state->ds_clear[i].depth_only_pipeline[j]);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, false,
&state->ds_clear[i].stencil_only_pipeline[j]);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depthstencil_pipeline(
device, VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, false,
&state->ds_clear[i].depthstencil_pipeline[j]);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, samples, j, true,
&state->ds_clear[i].depth_only_unrestricted_pipeline[j]);
if (res != VK_SUCCESS)
goto fail;
return res;
res =
create_depthstencil_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, true,
&state->ds_clear[i].stencil_only_unrestricted_pipeline[j]);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depthstencil_pipeline(
device, VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT, samples, j, true,
&state->ds_clear[i].depthstencil_unrestricted_pipeline[j]);
if (res != VK_SUCCESS)
goto fail;
return res;
}
}
return VK_SUCCESS;
fail:
radv_device_finish_meta_clear_state(device);
return res;
}
static uint32_t

2
src/amd/vulkan/radv_meta_dcc_retile.c
View File

@ -173,8 +173,6 @@ radv_device_init_meta_dcc_retile_state(struct radv_device *device, struct radeon
goto cleanup;
cleanup:
if (result != VK_SUCCESS)
radv_device_finish_meta_dcc_retile_state(device);
ralloc_free(cs);
return result;
}

16
src/amd/vulkan/radv_meta_decompress.c
View File

@ -335,7 +335,7 @@ radv_device_init_meta_depth_decomp_state(struct radv_device *device, bool on_dem
res = create_pipeline_layout(device, &state->depth_decomp[i].p_layout);
if (res != VK_SUCCESS)
goto fail;
return res;
if (on_demand)
continue;
@ -343,23 +343,15 @@ radv_device_init_meta_depth_decomp_state(struct radv_device *device, bool on_dem
res = create_pipeline(device, samples, state->depth_decomp[i].p_layout, DEPTH_DECOMPRESS,
&state->depth_decomp[i].decompress_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_pipeline(device, samples, state->depth_decomp[i].p_layout, DEPTH_RESUMMARIZE,
&state->depth_decomp[i].resummarize_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
}
res = create_expand_depth_stencil_compute(device);
if (res != VK_SUCCESS)
goto fail;
return VK_SUCCESS;
fail:
radv_device_finish_meta_depth_decomp_state(device);
return res;
return create_expand_depth_stencil_compute(device);
}
static VkPipeline *

11
src/amd/vulkan/radv_meta_etc_decode.c
View File

@ -620,19 +620,12 @@ radv_device_init_meta_etc_decode_state(struct radv_device *device, bool on_deman
res = create_layout(device);
if (res != VK_SUCCESS)
goto fail;
return res;
if (on_demand)
return VK_SUCCESS;
res = create_decode_pipeline(device, &state->etc_decode.pipeline);
if (res != VK_SUCCESS)
goto fail;
return VK_SUCCESS;
fail:
radv_device_finish_meta_etc_decode_state(device);
return res;
return create_decode_pipeline(device, &state->etc_decode.pipeline);
}
void

15
src/amd/vulkan/radv_meta_fast_clear.c
View File

@ -381,8 +381,6 @@ create_pipeline(struct radv_device *device, VkShaderModule vs_module_h, VkPipeli
if (result != VK_SUCCESS)
goto cleanup;
goto cleanup;
cleanup:
ralloc_free(fs_module);
return result;
@ -427,26 +425,21 @@ radv_device_init_meta_fast_clear_flush_state_internal(struct radv_device *device
if (!vs_module) {
/* XXX: Need more accurate error */
res = VK_ERROR_OUT_OF_HOST_MEMORY;
goto fail;
goto cleanup;
}
res = create_pipeline_layout(device, &device->meta_state.fast_clear_flush.p_layout);
if (res != VK_SUCCESS)
goto fail;
goto cleanup;
VkShaderModule vs_module_h = vk_shader_module_handle_from_nir(vs_module);
res = create_pipeline(device, vs_module_h, device->meta_state.fast_clear_flush.p_layout);
if (res != VK_SUCCESS)
goto fail;
goto cleanup;
res = create_dcc_compress_compute(device);
if (res != VK_SUCCESS)
goto fail;
goto cleanup;
fail:
radv_device_finish_meta_fast_clear_flush_state(device);
goto cleanup;
cleanup:
ralloc_free(vs_module);

9
src/amd/vulkan/radv_meta_fmask_copy.c
View File

@ -195,7 +195,7 @@ radv_device_init_meta_fmask_copy_state(struct radv_device *device)
&device->meta_state.alloc,
&device->meta_state.fmask_copy.ds_layout);
if (result != VK_SUCCESS)
goto fail;
return result;
VkPipelineLayoutCreateInfo pl_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
@ -209,19 +209,16 @@ radv_device_init_meta_fmask_copy_state(struct radv_device *device)
radv_CreatePipelineLayout(radv_device_to_handle(device), &pl_create_info,
&device->meta_state.alloc, &device->meta_state.fmask_copy.p_layout);
if (result != VK_SUCCESS)
goto fail;
return result;
for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) {
uint32_t samples = 1 << i;
result = create_fmask_copy_pipeline(device, samples, &device->meta_state.fmask_copy.pipeline[i]);
if (result != VK_SUCCESS)
goto fail;
return result;
}
return VK_SUCCESS;
fail:
radv_device_finish_meta_fmask_copy_state(device);
return result;
}
static void

9
src/amd/vulkan/radv_meta_fmask_expand.c
View File

@ -239,7 +239,7 @@ radv_device_init_meta_fmask_expand_state(struct radv_device *device)
result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device), &ds_create_info,
&state->alloc, &state->fmask_expand.ds_layout);
if (result != VK_SUCCESS)
goto fail;
return result;
VkPipelineLayoutCreateInfo color_create_info = {
.sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
@ -252,17 +252,14 @@ radv_device_init_meta_fmask_expand_state(struct radv_device *device)
result = radv_CreatePipelineLayout(radv_device_to_handle(device), &color_create_info,
&state->alloc, &state->fmask_expand.p_layout);
if (result != VK_SUCCESS)
goto fail;
return result;
for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; i++) {
uint32_t samples = 1 << i;
result = create_fmask_expand_pipeline(device, samples, &state->fmask_expand.pipeline[i]);
if (result != VK_SUCCESS)
goto fail;
return result;
}
return VK_SUCCESS;
fail:
radv_device_finish_meta_fmask_expand_state(device);
return result;
}

9
src/amd/vulkan/radv_meta_resolve.c
View File

@ -210,7 +210,7 @@ radv_device_init_meta_resolve_state(struct radv_device *device, bool on_demand)
if (!vs_module) {
/* XXX: Need more accurate error */
res = VK_ERROR_OUT_OF_HOST_MEMORY;
goto fail;
goto cleanup;
}
for (uint32_t i = 0; i < NUM_META_FS_KEYS; ++i) {
@ -220,14 +220,9 @@ radv_device_init_meta_resolve_state(struct radv_device *device, bool on_demand)
VkShaderModule vs_module_h = vk_shader_module_handle_from_nir(vs_module);
res = create_pipeline(device, vs_module_h, format, &state->resolve.pipeline[fs_key]);
if (res != VK_SUCCESS)
goto fail;
goto cleanup;
}
goto cleanup;
fail:
radv_device_finish_meta_resolve_state(device);
cleanup:
ralloc_free(vs_module);

33
src/amd/vulkan/radv_meta_resolve_cs.c
View File

@ -373,7 +373,7 @@ radv_device_init_meta_resolve_compute_state(struct radv_device *device, bool on_
res = create_layout(device);
if (res != VK_SUCCESS)
goto fail;
return res;
if (on_demand)
return VK_SUCCESS;
@ -384,65 +384,58 @@ radv_device_init_meta_resolve_compute_state(struct radv_device *device, bool on_
res = create_resolve_pipeline(device, samples, false, false,
&state->resolve_compute.rc[i].pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_resolve_pipeline(device, samples, true, false,
&state->resolve_compute.rc[i].i_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_resolve_pipeline(device, samples, false, true,
&state->resolve_compute.rc[i].srgb_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(
device, samples, DEPTH_RESOLVE, VK_RESOLVE_MODE_AVERAGE_BIT,
&state->resolve_compute.depth[i].average_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, samples, DEPTH_RESOLVE,
VK_RESOLVE_MODE_MAX_BIT,
&state->resolve_compute.depth[i].max_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, samples, DEPTH_RESOLVE,
VK_RESOLVE_MODE_MIN_BIT,
&state->resolve_compute.depth[i].min_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, samples, STENCIL_RESOLVE,
VK_RESOLVE_MODE_MAX_BIT,
&state->resolve_compute.stencil[i].max_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, samples, STENCIL_RESOLVE,
VK_RESOLVE_MODE_MIN_BIT,
&state->resolve_compute.stencil[i].min_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
}
res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT,
&state->resolve_compute.depth_zero_pipeline);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT,
&state->resolve_compute.stencil_zero_pipeline);
if (res != VK_SUCCESS)
goto fail;
return VK_SUCCESS;
fail:
radv_device_finish_meta_resolve_compute_state(device);
return res;
return create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT,
&state->resolve_compute.stencil_zero_pipeline);
}
void

27
src/amd/vulkan/radv_meta_resolve_fs.c
View File

@ -523,7 +523,7 @@ radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on
res = create_layout(device);
if (res != VK_SUCCESS)
goto fail;
return res;
if (on_demand)
return VK_SUCCESS;
@ -532,49 +532,42 @@ radv_device_init_meta_resolve_fragment_state(struct radv_device *device, bool on
for (unsigned j = 0; j < NUM_META_FS_KEYS; ++j) {
res = create_resolve_pipeline(device, i, radv_fs_key_format_exemplars[j]);
if (res != VK_SUCCESS)
goto fail;
return res;
}
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
VK_RESOLVE_MODE_AVERAGE_BIT);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
VK_RESOLVE_MODE_MIN_BIT);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, i, DEPTH_RESOLVE,
VK_RESOLVE_MODE_MAX_BIT);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
VK_RESOLVE_MODE_MIN_BIT);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, i, STENCIL_RESOLVE,
VK_RESOLVE_MODE_MAX_BIT);
if (res != VK_SUCCESS)
goto fail;
return res;
}
res = create_depth_stencil_resolve_pipeline(device, 0, DEPTH_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT);
if (res != VK_SUCCESS)
goto fail;
return res;
res = create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT);
if (res != VK_SUCCESS)
goto fail;
return VK_SUCCESS;
fail:
radv_device_finish_meta_resolve_fragment_state(device);
return res;
return create_depth_stencil_resolve_pipeline(device, 0, STENCIL_RESOLVE,
VK_RESOLVE_MODE_SAMPLE_ZERO_BIT);
}
void