2015-10-15 00:39:58 +01:00
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "anv_nir.h"
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2015-12-11 00:58:24 +00:00
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#include "program/prog_parameter.h"
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2016-02-05 23:03:04 +00:00
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#include "nir/nir_builder.h"
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2018-08-16 22:23:10 +01:00
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#include "compiler/brw_nir.h"
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2015-10-15 00:39:58 +01:00
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struct apply_pipeline_layout_state {
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2018-11-19 20:28:39 +00:00
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const struct anv_physical_device *pdevice;
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2015-10-15 00:39:58 +01:00
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nir_shader *shader;
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nir_builder builder;
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2016-05-19 05:41:05 +01:00
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struct anv_pipeline_layout *layout;
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bool add_bounds_checks;
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2018-06-29 06:44:24 +01:00
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bool uses_constants;
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uint8_t constants_offset;
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2016-02-03 20:14:28 +00:00
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struct {
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2018-11-19 20:28:39 +00:00
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bool desc_buffer_used;
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uint8_t desc_offset;
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2016-02-03 20:14:28 +00:00
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BITSET_WORD *used;
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uint8_t *surface_offsets;
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uint8_t *sampler_offsets;
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} set[MAX_SETS];
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2015-10-15 00:39:58 +01:00
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};
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2016-02-03 20:14:28 +00:00
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static void
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add_binding(struct apply_pipeline_layout_state *state,
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uint32_t set, uint32_t binding)
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2015-10-15 00:39:58 +01:00
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{
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2018-11-19 20:28:39 +00:00
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->layout->set[set].layout->binding[binding];
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2016-02-03 20:14:28 +00:00
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BITSET_SET(state->set[set].used, binding);
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2018-11-19 20:28:39 +00:00
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/* Only flag the descriptor buffer as used if there's actually data for
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* this binding. This lets us be lazy and call this function constantly
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* without worrying about unnecessarily enabling the buffer.
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*/
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if (anv_descriptor_size(bind_layout))
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state->set[set].desc_buffer_used = true;
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2015-10-15 00:39:58 +01:00
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}
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2018-03-23 06:25:07 +00:00
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static void
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add_deref_src_binding(struct apply_pipeline_layout_state *state, nir_src src)
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{
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nir_deref_instr *deref = nir_src_as_deref(src);
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2019-02-12 20:02:09 +00:00
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nir_variable *var = nir_deref_instr_get_variable(deref);
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add_binding(state, var->data.descriptor_set, var->data.binding);
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2018-03-23 06:25:07 +00:00
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}
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static void
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add_tex_src_binding(struct apply_pipeline_layout_state *state,
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nir_tex_instr *tex, nir_tex_src_type deref_src_type)
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{
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int deref_src_idx = nir_tex_instr_src_index(tex, deref_src_type);
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if (deref_src_idx < 0)
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return;
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add_deref_src_binding(state, tex->src[deref_src_idx].src);
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}
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2016-04-20 05:19:56 +01:00
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static void
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get_used_bindings_block(nir_block *block,
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struct apply_pipeline_layout_state *state)
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2015-11-18 23:14:05 +00:00
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{
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2016-04-27 02:34:19 +01:00
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nir_foreach_instr_safe(instr, block) {
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2016-02-03 20:14:28 +00:00
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switch (instr->type) {
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_vulkan_resource_index:
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add_binding(state, nir_intrinsic_desc_set(intrin),
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nir_intrinsic_binding(intrin));
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break;
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2018-03-23 06:25:07 +00:00
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case nir_intrinsic_image_deref_load:
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case nir_intrinsic_image_deref_store:
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case nir_intrinsic_image_deref_atomic_add:
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case nir_intrinsic_image_deref_atomic_min:
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case nir_intrinsic_image_deref_atomic_max:
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case nir_intrinsic_image_deref_atomic_and:
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case nir_intrinsic_image_deref_atomic_or:
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case nir_intrinsic_image_deref_atomic_xor:
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case nir_intrinsic_image_deref_atomic_exchange:
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case nir_intrinsic_image_deref_atomic_comp_swap:
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case nir_intrinsic_image_deref_size:
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case nir_intrinsic_image_deref_samples:
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2018-08-16 22:23:10 +01:00
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case nir_intrinsic_image_deref_load_param_intel:
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case nir_intrinsic_image_deref_load_raw_intel:
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case nir_intrinsic_image_deref_store_raw_intel:
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2018-03-23 06:25:07 +00:00
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add_deref_src_binding(state, intrin->src[0]);
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2016-02-03 20:14:28 +00:00
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break;
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2018-06-29 06:44:24 +01:00
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case nir_intrinsic_load_constant:
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state->uses_constants = true;
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break;
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2016-02-03 20:14:28 +00:00
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default:
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break;
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}
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break;
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}
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case nir_instr_type_tex: {
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nir_tex_instr *tex = nir_instr_as_tex(instr);
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2018-03-23 06:25:07 +00:00
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add_tex_src_binding(state, tex, nir_tex_src_texture_deref);
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add_tex_src_binding(state, tex, nir_tex_src_sampler_deref);
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2016-02-03 20:14:28 +00:00
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break;
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}
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default:
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continue;
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}
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}
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2015-11-18 23:14:05 +00:00
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}
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2015-10-27 20:42:51 +00:00
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static void
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lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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2015-10-15 00:39:58 +01:00
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{
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nir_builder *b = &state->builder;
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b->cursor = nir_before_instr(&intrin->instr);
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2016-02-09 23:32:21 +00:00
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uint32_t set = nir_intrinsic_desc_set(intrin);
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uint32_t binding = nir_intrinsic_binding(intrin);
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2015-10-15 00:39:58 +01:00
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2019-02-12 22:56:24 +00:00
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->layout->set[set].layout->binding[binding];
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2016-02-03 20:14:28 +00:00
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uint32_t surface_index = state->set[set].surface_offsets[binding];
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2019-02-12 22:56:24 +00:00
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uint32_t array_size = bind_layout->array_size;
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2015-10-15 00:39:58 +01:00
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2019-01-10 07:47:14 +00:00
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nir_ssa_def *array_index = nir_ssa_for_src(b, intrin->src[0], 1);
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if (nir_src_is_const(intrin->src[0]) || state->add_bounds_checks)
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array_index = nir_umin(b, array_index, nir_imm_int(b, array_size - 1));
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2019-02-12 22:56:24 +00:00
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nir_ssa_def *index;
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if (bind_layout->data & ANV_DESCRIPTOR_INLINE_UNIFORM) {
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/* This is an inline uniform block. Just reference the descriptor set
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* and use the descriptor offset as the base.
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*/
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index = nir_imm_ivec2(b, state->set[set].desc_offset,
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bind_layout->descriptor_offset);
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} else {
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2019-03-09 16:10:37 +00:00
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/* We're using nir_address_format_32bit_index_offset */
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2019-02-12 22:56:24 +00:00
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index = nir_vec2(b, nir_iadd_imm(b, array_index, surface_index),
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nir_imm_int(b, 0));
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}
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2015-10-15 00:39:58 +01:00
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2015-10-27 20:42:51 +00:00
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assert(intrin->dest.is_ssa);
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2019-01-12 16:58:33 +00:00
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(index));
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2015-10-27 20:42:51 +00:00
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nir_instr_remove(&intrin->instr);
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2015-10-15 00:39:58 +01:00
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}
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2017-12-01 01:13:56 +00:00
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static void
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lower_res_reindex_intrinsic(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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{
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nir_builder *b = &state->builder;
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2018-12-14 00:33:46 +00:00
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b->cursor = nir_before_instr(&intrin->instr);
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2017-12-01 01:13:56 +00:00
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/* For us, the resource indices are just indices into the binding table and
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* array elements are sequential. A resource_reindex just turns into an
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* add of the two indices.
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*/
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2018-01-22 22:44:36 +00:00
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assert(intrin->src[0].is_ssa && intrin->src[1].is_ssa);
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2019-01-12 16:58:33 +00:00
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nir_ssa_def *old_index = intrin->src[0].ssa;
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nir_ssa_def *offset = intrin->src[1].ssa;
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nir_ssa_def *new_index =
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nir_vec2(b, nir_iadd(b, nir_channel(b, old_index, 0), offset),
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nir_channel(b, old_index, 1));
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2017-12-01 01:13:56 +00:00
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assert(intrin->dest.is_ssa);
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(new_index));
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nir_instr_remove(&intrin->instr);
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}
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2018-12-15 00:38:08 +00:00
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static void
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lower_load_vulkan_descriptor(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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{
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nir_builder *b = &state->builder;
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b->cursor = nir_before_instr(&intrin->instr);
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2019-03-09 16:10:37 +00:00
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/* We follow the nir_address_format_32bit_index_offset model */
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2018-12-15 00:38:08 +00:00
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assert(intrin->src[0].is_ssa);
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2019-01-12 16:58:33 +00:00
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nir_ssa_def *index = intrin->src[0].ssa;
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2018-12-15 00:38:08 +00:00
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assert(intrin->dest.is_ssa);
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2019-01-12 16:58:33 +00:00
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(index));
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2018-12-15 00:38:08 +00:00
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nir_instr_remove(&intrin->instr);
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}
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2019-01-12 16:58:33 +00:00
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static void
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lower_get_buffer_size(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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{
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nir_builder *b = &state->builder;
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b->cursor = nir_before_instr(&intrin->instr);
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assert(intrin->src[0].is_ssa);
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nir_ssa_def *index = intrin->src[0].ssa;
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2019-03-09 16:10:37 +00:00
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/* We're following the nir_address_format_32bit_index_offset model so the
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2019-01-12 16:58:33 +00:00
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* binding table index is the first component of the address. The
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* back-end wants a scalar binding table index source.
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*/
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nir_instr_rewrite_src(&intrin->instr, &intrin->src[0],
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nir_src_for_ssa(nir_channel(b, index, 0)));
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}
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2018-11-22 00:26:27 +00:00
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static nir_ssa_def *
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build_descriptor_load(nir_deref_instr *deref, unsigned offset,
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unsigned num_components, unsigned bit_size,
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2018-08-16 22:23:10 +01:00
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struct apply_pipeline_layout_state *state)
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{
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nir_variable *var = nir_deref_instr_get_variable(deref);
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unsigned set = var->data.descriptor_set;
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unsigned binding = var->data.binding;
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unsigned array_size =
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state->layout->set[set].layout->binding[binding].array_size;
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2018-11-22 00:26:27 +00:00
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->layout->set[set].layout->binding[binding];
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2018-08-16 22:23:10 +01:00
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nir_builder *b = &state->builder;
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2018-11-22 00:26:27 +00:00
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nir_ssa_def *desc_buffer_index =
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nir_imm_int(b, state->set[set].desc_offset);
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nir_ssa_def *desc_offset =
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nir_imm_int(b, bind_layout->descriptor_offset + offset);
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2018-08-16 22:23:10 +01:00
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if (deref->deref_type != nir_deref_type_var) {
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|
|
assert(deref->deref_type == nir_deref_type_array);
|
2018-11-22 00:26:27 +00:00
|
|
|
|
|
|
|
|
|
const unsigned descriptor_size = anv_descriptor_size(bind_layout);
|
|
|
|
|
nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
|
2018-08-16 22:23:10 +01:00
|
|
|
|
if (state->add_bounds_checks)
|
2018-11-22 00:26:27 +00:00
|
|
|
|
arr_index = nir_umin(b, arr_index, nir_imm_int(b, array_size - 1));
|
|
|
|
|
|
|
|
|
|
desc_offset = nir_iadd(b, desc_offset,
|
|
|
|
|
nir_imul_imm(b, arr_index, descriptor_size));
|
2018-08-16 22:23:10 +01:00
|
|
|
|
}
|
|
|
|
|
|
2018-11-22 00:26:27 +00:00
|
|
|
|
nir_intrinsic_instr *desc_load =
|
|
|
|
|
nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
|
|
|
|
|
desc_load->src[0] = nir_src_for_ssa(desc_buffer_index);
|
|
|
|
|
desc_load->src[1] = nir_src_for_ssa(desc_offset);
|
|
|
|
|
desc_load->num_components = num_components;
|
|
|
|
|
nir_ssa_dest_init(&desc_load->instr, &desc_load->dest,
|
|
|
|
|
num_components, bit_size, NULL);
|
|
|
|
|
nir_builder_instr_insert(b, &desc_load->instr);
|
|
|
|
|
|
|
|
|
|
return &desc_load->dest.ssa;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static void
|
|
|
|
|
lower_image_intrinsic(nir_intrinsic_instr *intrin,
|
|
|
|
|
struct apply_pipeline_layout_state *state)
|
|
|
|
|
{
|
|
|
|
|
nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
|
|
|
|
|
|
|
|
|
|
nir_builder *b = &state->builder;
|
|
|
|
|
b->cursor = nir_before_instr(&intrin->instr);
|
|
|
|
|
|
2018-08-16 22:23:10 +01:00
|
|
|
|
if (intrin->intrinsic == nir_intrinsic_image_deref_load_param_intel) {
|
|
|
|
|
b->cursor = nir_instr_remove(&intrin->instr);
|
|
|
|
|
|
2018-11-22 00:26:27 +00:00
|
|
|
|
const unsigned param = nir_intrinsic_base(intrin);
|
2018-08-16 22:23:10 +01:00
|
|
|
|
|
2018-11-22 00:26:27 +00:00
|
|
|
|
nir_ssa_def *desc =
|
|
|
|
|
build_descriptor_load(deref, param * 16,
|
|
|
|
|
intrin->dest.ssa.num_components,
|
|
|
|
|
intrin->dest.ssa.bit_size, state);
|
2018-08-16 22:23:10 +01:00
|
|
|
|
|
2018-11-22 00:26:27 +00:00
|
|
|
|
nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(desc));
|
2018-08-16 22:23:10 +01:00
|
|
|
|
} else {
|
2018-11-22 00:26:27 +00:00
|
|
|
|
nir_variable *var = nir_deref_instr_get_variable(deref);
|
|
|
|
|
|
|
|
|
|
unsigned set = var->data.descriptor_set;
|
|
|
|
|
unsigned binding = var->data.binding;
|
2018-08-16 22:23:10 +01:00
|
|
|
|
unsigned binding_offset = state->set[set].surface_offsets[binding];
|
2018-11-22 00:26:27 +00:00
|
|
|
|
unsigned array_size =
|
|
|
|
|
state->layout->set[set].layout->binding[binding].array_size;
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *index = NULL;
|
|
|
|
|
if (deref->deref_type != nir_deref_type_var) {
|
|
|
|
|
assert(deref->deref_type == nir_deref_type_array);
|
|
|
|
|
index = nir_ssa_for_src(b, deref->arr.index, 1);
|
|
|
|
|
if (state->add_bounds_checks)
|
|
|
|
|
index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
|
|
|
|
|
} else {
|
|
|
|
|
index = nir_imm_int(b, 0);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
index = nir_iadd_imm(b, index, binding_offset);
|
2019-03-24 19:43:55 +00:00
|
|
|
|
nir_rewrite_image_intrinsic(intrin, index, false);
|
2018-08-16 22:23:10 +01:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-06-29 06:44:24 +01:00
|
|
|
|
static void
|
|
|
|
|
lower_load_constant(nir_intrinsic_instr *intrin,
|
|
|
|
|
struct apply_pipeline_layout_state *state)
|
|
|
|
|
{
|
|
|
|
|
nir_builder *b = &state->builder;
|
|
|
|
|
|
|
|
|
|
b->cursor = nir_before_instr(&intrin->instr);
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *index = nir_imm_int(b, state->constants_offset);
|
|
|
|
|
nir_ssa_def *offset = nir_iadd(b, nir_ssa_for_src(b, intrin->src[0], 1),
|
|
|
|
|
nir_imm_int(b, nir_intrinsic_base(intrin)));
|
|
|
|
|
|
|
|
|
|
nir_intrinsic_instr *load_ubo =
|
|
|
|
|
nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
|
|
|
|
|
load_ubo->num_components = intrin->num_components;
|
|
|
|
|
load_ubo->src[0] = nir_src_for_ssa(index);
|
|
|
|
|
load_ubo->src[1] = nir_src_for_ssa(offset);
|
|
|
|
|
nir_ssa_dest_init(&load_ubo->instr, &load_ubo->dest,
|
|
|
|
|
intrin->dest.ssa.num_components,
|
|
|
|
|
intrin->dest.ssa.bit_size, NULL);
|
|
|
|
|
nir_builder_instr_insert(b, &load_ubo->instr);
|
|
|
|
|
|
|
|
|
|
nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
|
|
|
|
|
nir_src_for_ssa(&load_ubo->dest.ssa));
|
|
|
|
|
nir_instr_remove(&intrin->instr);
|
|
|
|
|
}
|
|
|
|
|
|
2015-10-15 00:39:58 +01:00
|
|
|
|
static void
|
2018-03-23 06:25:07 +00:00
|
|
|
|
lower_tex_deref(nir_tex_instr *tex, nir_tex_src_type deref_src_type,
|
|
|
|
|
unsigned *base_index,
|
2015-11-14 17:00:35 +00:00
|
|
|
|
struct apply_pipeline_layout_state *state)
|
2015-10-15 00:39:58 +01:00
|
|
|
|
{
|
2018-03-23 06:25:07 +00:00
|
|
|
|
int deref_src_idx = nir_tex_instr_src_index(tex, deref_src_type);
|
|
|
|
|
if (deref_src_idx < 0)
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
nir_deref_instr *deref = nir_src_as_deref(tex->src[deref_src_idx].src);
|
|
|
|
|
nir_variable *var = nir_deref_instr_get_variable(deref);
|
|
|
|
|
|
|
|
|
|
unsigned set = var->data.descriptor_set;
|
|
|
|
|
unsigned binding = var->data.binding;
|
|
|
|
|
unsigned array_size =
|
|
|
|
|
state->layout->set[set].layout->binding[binding].array_size;
|
|
|
|
|
|
|
|
|
|
nir_tex_src_type offset_src_type;
|
|
|
|
|
if (deref_src_type == nir_tex_src_texture_deref) {
|
|
|
|
|
offset_src_type = nir_tex_src_texture_offset;
|
|
|
|
|
*base_index = state->set[set].surface_offsets[binding];
|
|
|
|
|
} else {
|
|
|
|
|
assert(deref_src_type == nir_tex_src_sampler_deref);
|
|
|
|
|
offset_src_type = nir_tex_src_sampler_offset;
|
|
|
|
|
*base_index = state->set[set].sampler_offsets[binding];
|
|
|
|
|
}
|
2016-05-19 05:41:05 +01:00
|
|
|
|
|
2018-03-23 06:25:07 +00:00
|
|
|
|
nir_ssa_def *index = NULL;
|
|
|
|
|
if (deref->deref_type != nir_deref_type_var) {
|
|
|
|
|
assert(deref->deref_type == nir_deref_type_array);
|
|
|
|
|
|
2018-10-20 18:25:31 +01:00
|
|
|
|
if (nir_src_is_const(deref->arr.index)) {
|
|
|
|
|
unsigned arr_index = nir_src_as_uint(deref->arr.index);
|
|
|
|
|
*base_index += MIN2(arr_index, array_size - 1);
|
2018-03-23 06:25:07 +00:00
|
|
|
|
} else {
|
|
|
|
|
nir_builder *b = &state->builder;
|
2015-10-15 00:39:58 +01:00
|
|
|
|
|
2017-09-25 18:46:16 +01:00
|
|
|
|
/* From VK_KHR_sampler_ycbcr_conversion:
|
|
|
|
|
*
|
|
|
|
|
* If sampler Y’CBCR conversion is enabled, the combined image
|
|
|
|
|
* sampler must be indexed only by constant integral expressions when
|
|
|
|
|
* aggregated into arrays in shader code, irrespective of the
|
|
|
|
|
* shaderSampledImageArrayDynamicIndexing feature.
|
|
|
|
|
*/
|
2018-03-18 04:37:36 +00:00
|
|
|
|
assert(nir_tex_instr_src_index(tex, nir_tex_src_plane) == -1);
|
2017-09-25 18:46:16 +01:00
|
|
|
|
|
2018-03-23 06:25:07 +00:00
|
|
|
|
index = nir_ssa_for_src(b, deref->arr.index, 1);
|
2016-05-19 05:41:05 +01:00
|
|
|
|
|
|
|
|
|
if (state->add_bounds_checks)
|
|
|
|
|
index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
|
2015-10-15 00:39:58 +01:00
|
|
|
|
}
|
|
|
|
|
}
|
2015-11-14 17:00:35 +00:00
|
|
|
|
|
2018-03-23 06:25:07 +00:00
|
|
|
|
if (index) {
|
|
|
|
|
nir_instr_rewrite_src(&tex->instr, &tex->src[deref_src_idx].src,
|
|
|
|
|
nir_src_for_ssa(index));
|
|
|
|
|
tex->src[deref_src_idx].src_type = offset_src_type;
|
|
|
|
|
} else {
|
|
|
|
|
nir_tex_instr_remove_src(tex, deref_src_idx);
|
|
|
|
|
}
|
2015-11-14 17:00:35 +00:00
|
|
|
|
}
|
|
|
|
|
|
2017-09-25 18:46:16 +01:00
|
|
|
|
static uint32_t
|
2018-03-18 04:37:36 +00:00
|
|
|
|
tex_instr_get_and_remove_plane_src(nir_tex_instr *tex)
|
2017-09-25 18:46:16 +01:00
|
|
|
|
{
|
2018-03-18 04:37:36 +00:00
|
|
|
|
int plane_src_idx = nir_tex_instr_src_index(tex, nir_tex_src_plane);
|
|
|
|
|
if (plane_src_idx < 0)
|
|
|
|
|
return 0;
|
|
|
|
|
|
2018-10-20 18:25:31 +01:00
|
|
|
|
unsigned plane = nir_src_as_uint(tex->src[plane_src_idx].src);
|
2017-09-25 18:46:16 +01:00
|
|
|
|
|
2017-10-16 16:50:44 +01:00
|
|
|
|
nir_tex_instr_remove_src(tex, plane_src_idx);
|
2017-09-25 18:46:16 +01:00
|
|
|
|
|
|
|
|
|
return plane;
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-14 17:00:35 +00:00
|
|
|
|
static void
|
|
|
|
|
lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
|
|
|
|
|
{
|
2016-05-19 05:41:05 +01:00
|
|
|
|
state->builder.cursor = nir_before_instr(&tex->instr);
|
|
|
|
|
|
2018-03-18 04:37:36 +00:00
|
|
|
|
unsigned plane = tex_instr_get_and_remove_plane_src(tex);
|
2017-09-25 18:46:16 +01:00
|
|
|
|
|
2018-03-23 06:25:07 +00:00
|
|
|
|
lower_tex_deref(tex, nir_tex_src_texture_deref,
|
|
|
|
|
&tex->texture_index, state);
|
2017-09-25 18:46:16 +01:00
|
|
|
|
tex->texture_index += plane;
|
2015-11-14 17:00:35 +00:00
|
|
|
|
|
2018-03-23 06:25:07 +00:00
|
|
|
|
lower_tex_deref(tex, nir_tex_src_sampler_deref,
|
|
|
|
|
&tex->sampler_index, state);
|
|
|
|
|
tex->sampler_index += plane;
|
2015-11-14 17:00:35 +00:00
|
|
|
|
|
2016-01-15 02:58:25 +00:00
|
|
|
|
/* The backend only ever uses this to mark used surfaces. We don't care
|
|
|
|
|
* about that little optimization so it just needs to be non-zero.
|
|
|
|
|
*/
|
|
|
|
|
tex->texture_array_size = 1;
|
2015-10-15 00:39:58 +01:00
|
|
|
|
}
|
|
|
|
|
|
2016-04-20 05:19:56 +01:00
|
|
|
|
static void
|
|
|
|
|
apply_pipeline_layout_block(nir_block *block,
|
|
|
|
|
struct apply_pipeline_layout_state *state)
|
2015-10-15 00:39:58 +01:00
|
|
|
|
{
|
2016-04-27 02:34:19 +01:00
|
|
|
|
nir_foreach_instr_safe(instr, block) {
|
2015-10-15 00:39:58 +01:00
|
|
|
|
switch (instr->type) {
|
2015-10-27 20:42:51 +00:00
|
|
|
|
case nir_instr_type_intrinsic: {
|
|
|
|
|
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
|
2017-12-01 01:13:56 +00:00
|
|
|
|
switch (intrin->intrinsic) {
|
|
|
|
|
case nir_intrinsic_vulkan_resource_index:
|
2015-10-27 20:42:51 +00:00
|
|
|
|
lower_res_index_intrinsic(intrin, state);
|
2017-12-01 01:13:56 +00:00
|
|
|
|
break;
|
|
|
|
|
case nir_intrinsic_vulkan_resource_reindex:
|
|
|
|
|
lower_res_reindex_intrinsic(intrin, state);
|
|
|
|
|
break;
|
2018-12-15 00:38:08 +00:00
|
|
|
|
case nir_intrinsic_load_vulkan_descriptor:
|
|
|
|
|
lower_load_vulkan_descriptor(intrin, state);
|
|
|
|
|
break;
|
2019-01-12 16:58:33 +00:00
|
|
|
|
case nir_intrinsic_get_buffer_size:
|
|
|
|
|
lower_get_buffer_size(intrin, state);
|
|
|
|
|
break;
|
2018-08-16 22:23:10 +01:00
|
|
|
|
case nir_intrinsic_image_deref_load:
|
|
|
|
|
case nir_intrinsic_image_deref_store:
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_add:
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_min:
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_max:
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_and:
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_or:
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_xor:
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_exchange:
|
|
|
|
|
case nir_intrinsic_image_deref_atomic_comp_swap:
|
|
|
|
|
case nir_intrinsic_image_deref_size:
|
|
|
|
|
case nir_intrinsic_image_deref_samples:
|
|
|
|
|
case nir_intrinsic_image_deref_load_param_intel:
|
|
|
|
|
case nir_intrinsic_image_deref_load_raw_intel:
|
|
|
|
|
case nir_intrinsic_image_deref_store_raw_intel:
|
|
|
|
|
lower_image_intrinsic(intrin, state);
|
|
|
|
|
break;
|
2018-06-29 06:44:24 +01:00
|
|
|
|
case nir_intrinsic_load_constant:
|
|
|
|
|
lower_load_constant(intrin, state);
|
|
|
|
|
break;
|
2017-12-01 01:13:56 +00:00
|
|
|
|
default:
|
|
|
|
|
break;
|
2015-10-27 20:42:51 +00:00
|
|
|
|
}
|
2015-10-15 00:39:58 +01:00
|
|
|
|
break;
|
2015-10-27 20:42:51 +00:00
|
|
|
|
}
|
2015-10-15 00:39:58 +01:00
|
|
|
|
case nir_instr_type_tex:
|
|
|
|
|
lower_tex(nir_instr_as_tex(instr), state);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-02-03 20:14:28 +00:00
|
|
|
|
void
|
2018-11-21 23:19:37 +00:00
|
|
|
|
anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
|
|
|
|
|
bool robust_buffer_access,
|
2018-01-25 09:25:00 +00:00
|
|
|
|
struct anv_pipeline_layout *layout,
|
2016-02-03 20:14:28 +00:00
|
|
|
|
nir_shader *shader,
|
2016-03-04 20:56:14 +00:00
|
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struct brw_stage_prog_data *prog_data,
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struct anv_pipeline_bind_map *map)
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2015-10-15 00:39:58 +01:00
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{
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struct apply_pipeline_layout_state state = {
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2018-11-19 20:28:39 +00:00
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.pdevice = pdevice,
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2015-10-15 00:39:58 +01:00
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.shader = shader,
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2016-05-19 05:41:05 +01:00
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.layout = layout,
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2018-11-21 23:19:37 +00:00
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.add_bounds_checks = robust_buffer_access,
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2015-10-15 00:39:58 +01:00
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};
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2016-02-03 20:14:28 +00:00
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void *mem_ctx = ralloc_context(NULL);
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for (unsigned s = 0; s < layout->num_sets; s++) {
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const unsigned count = layout->set[s].layout->binding_count;
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const unsigned words = BITSET_WORDS(count);
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state.set[s].used = rzalloc_array(mem_ctx, BITSET_WORD, words);
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state.set[s].surface_offsets = rzalloc_array(mem_ctx, uint8_t, count);
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state.set[s].sampler_offsets = rzalloc_array(mem_ctx, uint8_t, count);
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}
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2016-04-27 04:26:42 +01:00
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nir_foreach_function(function, shader) {
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2016-04-20 05:19:56 +01:00
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if (!function->impl)
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continue;
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nir_foreach_block(block, function->impl)
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get_used_bindings_block(block, &state);
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2016-02-03 20:14:28 +00:00
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}
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2018-11-19 20:28:39 +00:00
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for (unsigned s = 0; s < layout->num_sets; s++) {
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if (state.set[s].desc_buffer_used) {
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map->surface_to_descriptor[map->surface_count] =
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(struct anv_pipeline_binding) {
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.set = ANV_DESCRIPTOR_SET_DESCRIPTORS,
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.binding = s,
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};
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state.set[s].desc_offset = map->surface_count;
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map->surface_count++;
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}
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}
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2018-06-29 06:44:24 +01:00
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if (state.uses_constants) {
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2018-08-07 23:29:43 +01:00
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state.constants_offset = map->surface_count;
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map->surface_to_descriptor[map->surface_count].set =
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2018-06-29 06:44:24 +01:00
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ANV_DESCRIPTOR_SET_SHADER_CONSTANTS;
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2018-08-07 23:29:43 +01:00
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map->surface_count++;
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2018-06-29 06:44:24 +01:00
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}
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2016-02-03 20:14:28 +00:00
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for (uint32_t set = 0; set < layout->num_sets; set++) {
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struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
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BITSET_WORD b, _tmp;
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BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
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set_layout->binding_count) {
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2017-09-25 18:46:16 +01:00
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struct anv_descriptor_set_binding_layout *binding =
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&set_layout->binding[b];
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2016-02-03 20:14:28 +00:00
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2018-11-24 18:42:39 +00:00
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if (binding->array_size == 0)
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continue;
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if (binding->data & ANV_DESCRIPTOR_SURFACE_STATE) {
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2018-08-07 23:29:43 +01:00
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state.set[set].surface_offsets[b] = map->surface_count;
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2017-09-25 18:46:16 +01:00
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struct anv_sampler **samplers = binding->immutable_samplers;
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for (unsigned i = 0; i < binding->array_size; i++) {
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uint8_t planes = samplers ? samplers[i]->n_planes : 1;
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for (uint8_t p = 0; p < planes; p++) {
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2018-08-07 23:29:43 +01:00
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map->surface_to_descriptor[map->surface_count++] =
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(struct anv_pipeline_binding) {
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.set = set,
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.binding = b,
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.index = i,
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.plane = p,
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};
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2017-09-25 18:46:16 +01:00
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}
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2016-02-03 20:14:28 +00:00
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}
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}
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2018-11-24 18:42:39 +00:00
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if (binding->data & ANV_DESCRIPTOR_SAMPLER_STATE) {
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2018-08-07 23:29:43 +01:00
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state.set[set].sampler_offsets[b] = map->sampler_count;
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2017-09-25 18:46:16 +01:00
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struct anv_sampler **samplers = binding->immutable_samplers;
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for (unsigned i = 0; i < binding->array_size; i++) {
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uint8_t planes = samplers ? samplers[i]->n_planes : 1;
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for (uint8_t p = 0; p < planes; p++) {
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2018-08-07 23:29:43 +01:00
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map->sampler_to_descriptor[map->sampler_count++] =
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(struct anv_pipeline_binding) {
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.set = set,
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.binding = b,
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.index = i,
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.plane = p,
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};
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2017-09-25 18:46:16 +01:00
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}
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2016-02-03 20:14:28 +00:00
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}
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}
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}
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}
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2016-11-15 23:21:08 +00:00
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nir_foreach_variable(var, &shader->uniforms) {
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2018-03-01 16:51:58 +00:00
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const struct glsl_type *glsl_type = glsl_without_array(var->type);
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if (!glsl_type_is_image(glsl_type))
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2016-11-15 23:21:08 +00:00
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continue;
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2018-03-01 16:51:58 +00:00
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enum glsl_sampler_dim dim = glsl_get_sampler_dim(glsl_type);
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2016-11-15 23:21:08 +00:00
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const uint32_t set = var->data.descriptor_set;
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const uint32_t binding = var->data.binding;
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const uint32_t array_size =
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layout->set[set].layout->binding[binding].array_size;
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if (!BITSET_TEST(state.set[set].used, binding))
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continue;
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struct anv_pipeline_binding *pipe_binding =
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&map->surface_to_descriptor[state.set[set].surface_offsets[binding]];
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for (unsigned i = 0; i < array_size; i++) {
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assert(pipe_binding[i].set == set);
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assert(pipe_binding[i].binding == binding);
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assert(pipe_binding[i].index == i);
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2017-02-14 10:34:49 +00:00
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if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
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dim == GLSL_SAMPLER_DIM_SUBPASS_MS)
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pipe_binding[i].input_attachment_index = var->data.index + i;
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2018-08-16 21:11:12 +01:00
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pipe_binding[i].write_only =
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(var->data.image.access & ACCESS_NON_READABLE) != 0;
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2016-11-15 23:21:08 +00:00
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}
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}
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2016-04-27 04:26:42 +01:00
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nir_foreach_function(function, shader) {
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2016-04-20 05:19:56 +01:00
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if (!function->impl)
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continue;
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nir_builder_init(&state.builder, function->impl);
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nir_foreach_block(block, function->impl)
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apply_pipeline_layout_block(block, &state);
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nir_metadata_preserve(function->impl, nir_metadata_block_index |
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nir_metadata_dominance);
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2015-10-15 00:39:58 +01:00
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}
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2016-02-18 19:04:53 +00:00
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ralloc_free(mem_ctx);
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2015-10-15 00:39:58 +01:00
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}
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