2015-10-15 00:39:58 +01:00
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "anv_nir.h"
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2015-12-11 00:58:24 +00:00
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#include "program/prog_parameter.h"
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2016-02-05 23:03:04 +00:00
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#include "nir/nir_builder.h"
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2015-10-15 00:39:58 +01:00
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struct apply_pipeline_layout_state {
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nir_shader *shader;
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nir_builder builder;
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2016-05-19 05:41:05 +01:00
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struct anv_pipeline_layout *layout;
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bool add_bounds_checks;
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2016-02-03 20:14:28 +00:00
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struct {
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BITSET_WORD *used;
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uint8_t *surface_offsets;
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uint8_t *sampler_offsets;
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uint8_t *image_offsets;
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} set[MAX_SETS];
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2015-10-15 00:39:58 +01:00
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};
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2016-02-03 20:14:28 +00:00
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static void
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add_binding(struct apply_pipeline_layout_state *state,
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uint32_t set, uint32_t binding)
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2015-10-15 00:39:58 +01:00
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{
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2016-02-03 20:14:28 +00:00
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BITSET_SET(state->set[set].used, binding);
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2015-10-15 00:39:58 +01:00
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}
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2016-02-03 20:14:28 +00:00
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static void
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add_var_binding(struct apply_pipeline_layout_state *state, nir_variable *var)
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2015-11-14 17:00:35 +00:00
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{
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2016-02-03 20:14:28 +00:00
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add_binding(state, var->data.descriptor_set, var->data.binding);
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2015-11-14 17:00:35 +00:00
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}
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2016-04-20 05:19:56 +01:00
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static void
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get_used_bindings_block(nir_block *block,
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struct apply_pipeline_layout_state *state)
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2015-11-18 23:14:05 +00:00
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{
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2016-04-27 02:34:19 +01:00
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nir_foreach_instr_safe(instr, block) {
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2016-02-03 20:14:28 +00:00
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switch (instr->type) {
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_vulkan_resource_index:
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add_binding(state, nir_intrinsic_desc_set(intrin),
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nir_intrinsic_binding(intrin));
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break;
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case nir_intrinsic_image_load:
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case nir_intrinsic_image_store:
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case nir_intrinsic_image_atomic_add:
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case nir_intrinsic_image_atomic_min:
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case nir_intrinsic_image_atomic_max:
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case nir_intrinsic_image_atomic_and:
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case nir_intrinsic_image_atomic_or:
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case nir_intrinsic_image_atomic_xor:
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case nir_intrinsic_image_atomic_exchange:
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case nir_intrinsic_image_atomic_comp_swap:
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case nir_intrinsic_image_size:
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case nir_intrinsic_image_samples:
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add_var_binding(state, intrin->variables[0]->var);
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break;
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default:
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break;
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}
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break;
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}
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case nir_instr_type_tex: {
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nir_tex_instr *tex = nir_instr_as_tex(instr);
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assert(tex->texture);
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add_var_binding(state, tex->texture->var);
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if (tex->sampler)
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add_var_binding(state, tex->sampler->var);
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break;
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}
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default:
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continue;
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}
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}
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2015-11-18 23:14:05 +00:00
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}
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2015-10-27 20:42:51 +00:00
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static void
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lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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2015-10-15 00:39:58 +01:00
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{
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nir_builder *b = &state->builder;
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b->cursor = nir_before_instr(&intrin->instr);
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2016-02-09 23:32:21 +00:00
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uint32_t set = nir_intrinsic_desc_set(intrin);
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uint32_t binding = nir_intrinsic_binding(intrin);
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2015-10-15 00:39:58 +01:00
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2016-02-03 20:14:28 +00:00
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uint32_t surface_index = state->set[set].surface_offsets[binding];
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2016-05-19 05:41:05 +01:00
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uint32_t array_size =
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state->layout->set[set].layout->binding[binding].array_size;
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2015-10-15 00:39:58 +01:00
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2017-12-01 11:18:51 +00:00
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nir_const_value *const_array_index = nir_src_as_const_value(intrin->src[0]);
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2015-10-15 00:39:58 +01:00
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2017-12-01 11:18:51 +00:00
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nir_ssa_def *block_index;
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if (const_array_index) {
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unsigned array_index = const_array_index->u32[0];
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array_index = MIN2(array_index, array_size - 1);
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block_index = nir_imm_int(b, surface_index + array_index);
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} else {
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block_index = nir_ssa_for_src(b, intrin->src[0], 1);
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2016-05-19 05:41:05 +01:00
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2017-12-01 11:18:51 +00:00
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if (state->add_bounds_checks)
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block_index = nir_umin(b, block_index, nir_imm_int(b, array_size - 1));
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block_index = nir_iadd(b, nir_imm_int(b, surface_index), block_index);
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}
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2015-10-15 00:39:58 +01:00
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2015-10-27 20:42:51 +00:00
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assert(intrin->dest.is_ssa);
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(block_index));
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nir_instr_remove(&intrin->instr);
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2015-10-15 00:39:58 +01:00
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}
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2017-12-01 01:13:56 +00:00
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static void
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lower_res_reindex_intrinsic(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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{
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nir_builder *b = &state->builder;
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/* For us, the resource indices are just indices into the binding table and
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* array elements are sequential. A resource_reindex just turns into an
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* add of the two indices.
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*/
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assert(intrin->src[0].is_ssa && intrin->src[0].is_ssa);
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nir_ssa_def *new_index = nir_iadd(b, intrin->src[0].ssa,
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intrin->src[1].ssa);
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assert(intrin->dest.is_ssa);
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(new_index));
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nir_instr_remove(&intrin->instr);
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}
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2015-10-15 00:39:58 +01:00
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static void
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2015-11-14 17:00:35 +00:00
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lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
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2016-05-19 05:41:05 +01:00
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unsigned *const_index, unsigned array_size,
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2017-09-25 18:46:16 +01:00
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nir_tex_src_type src_type, bool allow_indirect,
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2015-11-14 17:00:35 +00:00
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struct apply_pipeline_layout_state *state)
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2015-10-15 00:39:58 +01:00
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{
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2016-05-19 05:41:05 +01:00
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nir_builder *b = &state->builder;
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2015-11-14 17:00:35 +00:00
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if (deref->deref.child) {
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assert(deref->deref.child->deref_type == nir_deref_type_array);
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nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
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2015-10-15 00:39:58 +01:00
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if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
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2017-09-25 18:46:16 +01:00
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/* From VK_KHR_sampler_ycbcr_conversion:
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*
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* If sampler Y’CBCR conversion is enabled, the combined image
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* sampler must be indexed only by constant integral expressions when
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* aggregated into arrays in shader code, irrespective of the
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* shaderSampledImageArrayDynamicIndexing feature.
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*/
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assert(allow_indirect);
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2016-05-19 05:41:05 +01:00
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nir_ssa_def *index =
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nir_iadd(b, nir_imm_int(b, deref_array->base_offset),
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nir_ssa_for_src(b, deref_array->indirect, 1));
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if (state->add_bounds_checks)
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index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
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2017-10-16 16:50:23 +01:00
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nir_tex_instr_add_src(tex, src_type, nir_src_for_ssa(index));
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2016-05-19 05:41:05 +01:00
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} else {
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*const_index += MIN2(deref_array->base_offset, array_size - 1);
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2015-10-15 00:39:58 +01:00
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}
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}
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2015-11-14 17:00:35 +00:00
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}
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static void
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cleanup_tex_deref(nir_tex_instr *tex, nir_deref_var *deref)
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{
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if (deref->deref.child == NULL)
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return;
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nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
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if (deref_array->deref_array_type != nir_deref_array_type_indirect)
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return;
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nir_instr_rewrite_src(&tex->instr, &deref_array->indirect, NIR_SRC_INIT);
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}
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2017-09-25 18:46:16 +01:00
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static bool
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has_tex_src_plane(nir_tex_instr *tex)
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{
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for (unsigned i = 0; i < tex->num_srcs; i++) {
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if (tex->src[i].src_type == nir_tex_src_plane)
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return true;
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}
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return false;
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}
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static uint32_t
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extract_tex_src_plane(nir_tex_instr *tex)
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{
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unsigned plane = 0;
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2017-10-16 16:50:44 +01:00
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int plane_src_idx = -1;
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for (unsigned i = 0; i < tex->num_srcs; i++) {
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2017-09-25 18:46:16 +01:00
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if (tex->src[i].src_type == nir_tex_src_plane) {
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nir_const_value *const_plane =
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nir_src_as_const_value(tex->src[i].src);
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/* Our color conversion lowering pass should only ever insert
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* constants. */
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assert(const_plane);
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plane = const_plane->u32[0];
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2017-10-16 16:50:44 +01:00
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plane_src_idx = i;
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2017-09-25 18:46:16 +01:00
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}
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}
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2017-10-16 16:50:44 +01:00
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assert(plane_src_idx >= 0);
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nir_tex_instr_remove_src(tex, plane_src_idx);
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2017-09-25 18:46:16 +01:00
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return plane;
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}
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2015-11-14 17:00:35 +00:00
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static void
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lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
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{
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/* No one should have come by and lowered it already */
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2016-02-09 20:13:32 +00:00
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assert(tex->texture);
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2015-10-15 00:39:58 +01:00
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2016-05-19 05:41:05 +01:00
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state->builder.cursor = nir_before_instr(&tex->instr);
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2016-02-03 20:14:28 +00:00
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unsigned set = tex->texture->var->data.descriptor_set;
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unsigned binding = tex->texture->var->data.binding;
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2016-05-19 05:41:05 +01:00
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unsigned array_size =
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state->layout->set[set].layout->binding[binding].array_size;
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2017-09-25 18:46:16 +01:00
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bool has_plane = has_tex_src_plane(tex);
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unsigned plane = has_plane ? extract_tex_src_plane(tex) : 0;
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2016-02-03 20:14:28 +00:00
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tex->texture_index = state->set[set].surface_offsets[binding];
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2016-05-19 05:41:05 +01:00
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lower_tex_deref(tex, tex->texture, &tex->texture_index, array_size,
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2017-09-25 18:46:16 +01:00
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nir_tex_src_texture_offset, !has_plane, state);
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tex->texture_index += plane;
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2015-11-14 17:00:35 +00:00
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2016-02-09 20:13:32 +00:00
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if (tex->sampler) {
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2016-02-03 20:14:28 +00:00
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unsigned set = tex->sampler->var->data.descriptor_set;
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unsigned binding = tex->sampler->var->data.binding;
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2016-05-19 05:41:05 +01:00
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unsigned array_size =
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state->layout->set[set].layout->binding[binding].array_size;
|
2016-02-18 21:54:15 +00:00
|
|
|
|
tex->sampler_index = state->set[set].sampler_offsets[binding];
|
2016-05-19 05:41:05 +01:00
|
|
|
|
lower_tex_deref(tex, tex->sampler, &tex->sampler_index, array_size,
|
2017-09-25 18:46:16 +01:00
|
|
|
|
nir_tex_src_sampler_offset, !has_plane, state);
|
|
|
|
|
tex->sampler_index += plane;
|
2016-02-09 20:13:32 +00:00
|
|
|
|
}
|
2015-11-14 17:00:35 +00:00
|
|
|
|
|
2016-01-15 02:58:25 +00:00
|
|
|
|
/* The backend only ever uses this to mark used surfaces. We don't care
|
|
|
|
|
* about that little optimization so it just needs to be non-zero.
|
|
|
|
|
*/
|
|
|
|
|
tex->texture_array_size = 1;
|
|
|
|
|
|
2016-02-09 20:13:32 +00:00
|
|
|
|
cleanup_tex_deref(tex, tex->texture);
|
|
|
|
|
if (tex->sampler)
|
|
|
|
|
cleanup_tex_deref(tex, tex->sampler);
|
2015-11-14 17:00:35 +00:00
|
|
|
|
tex->texture = NULL;
|
2015-10-15 00:39:58 +01:00
|
|
|
|
tex->sampler = NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-20 05:19:56 +01:00
|
|
|
|
static void
|
|
|
|
|
apply_pipeline_layout_block(nir_block *block,
|
|
|
|
|
struct apply_pipeline_layout_state *state)
|
2015-10-15 00:39:58 +01:00
|
|
|
|
{
|
2016-04-27 02:34:19 +01:00
|
|
|
|
nir_foreach_instr_safe(instr, block) {
|
2015-10-15 00:39:58 +01:00
|
|
|
|
switch (instr->type) {
|
2015-10-27 20:42:51 +00:00
|
|
|
|
case nir_instr_type_intrinsic: {
|
|
|
|
|
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
|
2017-12-01 01:13:56 +00:00
|
|
|
|
switch (intrin->intrinsic) {
|
|
|
|
|
case nir_intrinsic_vulkan_resource_index:
|
2015-10-27 20:42:51 +00:00
|
|
|
|
lower_res_index_intrinsic(intrin, state);
|
2017-12-01 01:13:56 +00:00
|
|
|
|
break;
|
|
|
|
|
case nir_intrinsic_vulkan_resource_reindex:
|
|
|
|
|
lower_res_reindex_intrinsic(intrin, state);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
2015-10-27 20:42:51 +00:00
|
|
|
|
}
|
2015-10-15 00:39:58 +01:00
|
|
|
|
break;
|
2015-10-27 20:42:51 +00:00
|
|
|
|
}
|
2015-10-15 00:39:58 +01:00
|
|
|
|
case nir_instr_type_tex:
|
|
|
|
|
lower_tex(nir_instr_as_tex(instr), state);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
continue;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-11-18 23:14:05 +00:00
|
|
|
|
static void
|
2017-09-29 00:25:31 +01:00
|
|
|
|
setup_vec4_uniform_value(uint32_t *params, uint32_t offset, unsigned n)
|
2015-11-18 23:14:05 +00:00
|
|
|
|
{
|
|
|
|
|
for (unsigned i = 0; i < n; ++i)
|
2017-09-29 00:25:31 +01:00
|
|
|
|
params[i] = ANV_PARAM_PUSH(offset + i * sizeof(uint32_t));
|
2015-11-18 23:14:05 +00:00
|
|
|
|
|
|
|
|
|
for (unsigned i = n; i < 4; ++i)
|
2017-09-29 00:25:31 +01:00
|
|
|
|
params[i] = BRW_PARAM_BUILTIN_ZERO;
|
2015-11-18 23:14:05 +00:00
|
|
|
|
}
|
|
|
|
|
|
2016-02-03 20:14:28 +00:00
|
|
|
|
void
|
|
|
|
|
anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
|
|
|
|
|
nir_shader *shader,
|
2016-03-04 20:56:14 +00:00
|
|
|
|
struct brw_stage_prog_data *prog_data,
|
|
|
|
|
struct anv_pipeline_bind_map *map)
|
2015-10-15 00:39:58 +01:00
|
|
|
|
{
|
2016-02-03 20:14:28 +00:00
|
|
|
|
struct anv_pipeline_layout *layout = pipeline->layout;
|
2017-09-15 03:52:38 +01:00
|
|
|
|
gl_shader_stage stage = shader->info.stage;
|
2016-02-03 20:14:28 +00:00
|
|
|
|
|
2015-10-15 00:39:58 +01:00
|
|
|
|
struct apply_pipeline_layout_state state = {
|
|
|
|
|
.shader = shader,
|
2016-05-19 05:41:05 +01:00
|
|
|
|
.layout = layout,
|
|
|
|
|
.add_bounds_checks = pipeline->device->robust_buffer_access,
|
2015-10-15 00:39:58 +01:00
|
|
|
|
};
|
|
|
|
|
|
2016-02-03 20:14:28 +00:00
|
|
|
|
void *mem_ctx = ralloc_context(NULL);
|
|
|
|
|
|
|
|
|
|
for (unsigned s = 0; s < layout->num_sets; s++) {
|
|
|
|
|
const unsigned count = layout->set[s].layout->binding_count;
|
|
|
|
|
const unsigned words = BITSET_WORDS(count);
|
|
|
|
|
state.set[s].used = rzalloc_array(mem_ctx, BITSET_WORD, words);
|
|
|
|
|
state.set[s].surface_offsets = rzalloc_array(mem_ctx, uint8_t, count);
|
|
|
|
|
state.set[s].sampler_offsets = rzalloc_array(mem_ctx, uint8_t, count);
|
|
|
|
|
state.set[s].image_offsets = rzalloc_array(mem_ctx, uint8_t, count);
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-27 04:26:42 +01:00
|
|
|
|
nir_foreach_function(function, shader) {
|
2016-04-20 05:19:56 +01:00
|
|
|
|
if (!function->impl)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
nir_foreach_block(block, function->impl)
|
|
|
|
|
get_used_bindings_block(block, &state);
|
2016-02-03 20:14:28 +00:00
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (uint32_t set = 0; set < layout->num_sets; set++) {
|
|
|
|
|
struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
|
|
|
|
|
|
|
|
|
|
BITSET_WORD b, _tmp;
|
|
|
|
|
BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
|
|
|
|
|
set_layout->binding_count) {
|
2017-09-15 03:52:38 +01:00
|
|
|
|
if (set_layout->binding[b].stage[stage].surface_index >= 0) {
|
2017-09-25 18:46:16 +01:00
|
|
|
|
map->surface_count +=
|
|
|
|
|
anv_descriptor_set_binding_layout_get_hw_size(&set_layout->binding[b]);
|
|
|
|
|
}
|
2017-09-15 03:52:38 +01:00
|
|
|
|
if (set_layout->binding[b].stage[stage].sampler_index >= 0) {
|
2017-09-25 18:46:16 +01:00
|
|
|
|
map->sampler_count +=
|
|
|
|
|
anv_descriptor_set_binding_layout_get_hw_size(&set_layout->binding[b]);
|
|
|
|
|
}
|
2017-09-15 03:52:38 +01:00
|
|
|
|
if (set_layout->binding[b].stage[stage].image_index >= 0)
|
2016-03-04 20:56:14 +00:00
|
|
|
|
map->image_count += set_layout->binding[b].array_size;
|
2016-02-03 20:14:28 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
unsigned surface = 0;
|
|
|
|
|
unsigned sampler = 0;
|
|
|
|
|
unsigned image = 0;
|
|
|
|
|
for (uint32_t set = 0; set < layout->num_sets; set++) {
|
|
|
|
|
struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
|
|
|
|
|
|
|
|
|
|
BITSET_WORD b, _tmp;
|
|
|
|
|
BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
|
|
|
|
|
set_layout->binding_count) {
|
2017-09-25 18:46:16 +01:00
|
|
|
|
struct anv_descriptor_set_binding_layout *binding =
|
|
|
|
|
&set_layout->binding[b];
|
2016-02-03 20:14:28 +00:00
|
|
|
|
|
2017-09-15 03:52:38 +01:00
|
|
|
|
if (binding->stage[stage].surface_index >= 0) {
|
2016-02-03 20:14:28 +00:00
|
|
|
|
state.set[set].surface_offsets[b] = surface;
|
2017-09-25 18:46:16 +01:00
|
|
|
|
struct anv_sampler **samplers = binding->immutable_samplers;
|
|
|
|
|
for (unsigned i = 0; i < binding->array_size; i++) {
|
|
|
|
|
uint8_t planes = samplers ? samplers[i]->n_planes : 1;
|
|
|
|
|
for (uint8_t p = 0; p < planes; p++) {
|
|
|
|
|
map->surface_to_descriptor[surface].set = set;
|
|
|
|
|
map->surface_to_descriptor[surface].binding = b;
|
|
|
|
|
map->surface_to_descriptor[surface].index = i;
|
|
|
|
|
map->surface_to_descriptor[surface].plane = p;
|
|
|
|
|
surface++;
|
|
|
|
|
}
|
2016-02-03 20:14:28 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-09-15 03:52:38 +01:00
|
|
|
|
if (binding->stage[stage].sampler_index >= 0) {
|
2016-02-03 20:14:28 +00:00
|
|
|
|
state.set[set].sampler_offsets[b] = sampler;
|
2017-09-25 18:46:16 +01:00
|
|
|
|
struct anv_sampler **samplers = binding->immutable_samplers;
|
|
|
|
|
for (unsigned i = 0; i < binding->array_size; i++) {
|
|
|
|
|
uint8_t planes = samplers ? samplers[i]->n_planes : 1;
|
|
|
|
|
for (uint8_t p = 0; p < planes; p++) {
|
|
|
|
|
map->sampler_to_descriptor[sampler].set = set;
|
|
|
|
|
map->sampler_to_descriptor[sampler].binding = b;
|
|
|
|
|
map->sampler_to_descriptor[sampler].index = i;
|
|
|
|
|
map->sampler_to_descriptor[sampler].plane = p;
|
|
|
|
|
sampler++;
|
|
|
|
|
}
|
2016-02-03 20:14:28 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-09-15 03:52:38 +01:00
|
|
|
|
if (binding->stage[stage].image_index >= 0) {
|
2016-02-03 20:14:28 +00:00
|
|
|
|
state.set[set].image_offsets[b] = image;
|
2017-09-25 18:46:16 +01:00
|
|
|
|
image += binding->array_size;
|
2016-02-03 20:14:28 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-11-15 23:21:08 +00:00
|
|
|
|
nir_foreach_variable(var, &shader->uniforms) {
|
|
|
|
|
if (!glsl_type_is_image(var->interface_type))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
enum glsl_sampler_dim dim = glsl_get_sampler_dim(var->interface_type);
|
|
|
|
|
|
|
|
|
|
const uint32_t set = var->data.descriptor_set;
|
|
|
|
|
const uint32_t binding = var->data.binding;
|
|
|
|
|
const uint32_t array_size =
|
|
|
|
|
layout->set[set].layout->binding[binding].array_size;
|
|
|
|
|
|
|
|
|
|
if (!BITSET_TEST(state.set[set].used, binding))
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
struct anv_pipeline_binding *pipe_binding =
|
|
|
|
|
&map->surface_to_descriptor[state.set[set].surface_offsets[binding]];
|
|
|
|
|
for (unsigned i = 0; i < array_size; i++) {
|
|
|
|
|
assert(pipe_binding[i].set == set);
|
|
|
|
|
assert(pipe_binding[i].binding == binding);
|
|
|
|
|
assert(pipe_binding[i].index == i);
|
2017-02-14 10:34:49 +00:00
|
|
|
|
|
|
|
|
|
if (dim == GLSL_SAMPLER_DIM_SUBPASS ||
|
|
|
|
|
dim == GLSL_SAMPLER_DIM_SUBPASS_MS)
|
|
|
|
|
pipe_binding[i].input_attachment_index = var->data.index + i;
|
|
|
|
|
|
|
|
|
|
pipe_binding[i].write_only = var->data.image.write_only;
|
2016-11-15 23:21:08 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-04-27 04:26:42 +01:00
|
|
|
|
nir_foreach_function(function, shader) {
|
2016-04-20 05:19:56 +01:00
|
|
|
|
if (!function->impl)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
nir_builder_init(&state.builder, function->impl);
|
|
|
|
|
nir_foreach_block(block, function->impl)
|
|
|
|
|
apply_pipeline_layout_block(block, &state);
|
|
|
|
|
nir_metadata_preserve(function->impl, nir_metadata_block_index |
|
|
|
|
|
nir_metadata_dominance);
|
2015-10-15 00:39:58 +01:00
|
|
|
|
}
|
|
|
|
|
|
2016-03-04 20:56:14 +00:00
|
|
|
|
if (map->image_count > 0) {
|
|
|
|
|
assert(map->image_count <= MAX_IMAGES);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
nir_foreach_variable(var, &shader->uniforms) {
|
|
|
|
|
if (glsl_type_is_image(var->type) ||
|
|
|
|
|
(glsl_type_is_array(var->type) &&
|
|
|
|
|
glsl_type_is_image(glsl_get_array_element(var->type)))) {
|
|
|
|
|
/* Images are represented as uniform push constants and the actual
|
|
|
|
|
* information required for reading/writing to/from the image is
|
|
|
|
|
* storred in the uniform.
|
|
|
|
|
*/
|
2016-02-03 20:14:28 +00:00
|
|
|
|
unsigned set = var->data.descriptor_set;
|
|
|
|
|
unsigned binding = var->data.binding;
|
|
|
|
|
unsigned image_index = state.set[set].image_offsets[binding];
|
2015-11-18 23:14:05 +00:00
|
|
|
|
|
|
|
|
|
var->data.driver_location = shader->num_uniforms +
|
2015-12-11 06:36:47 +00:00
|
|
|
|
image_index * BRW_IMAGE_PARAM_SIZE * 4;
|
2015-11-18 23:14:05 +00:00
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2017-09-29 19:10:22 +01:00
|
|
|
|
uint32_t *param = brw_stage_prog_data_add_params(prog_data,
|
|
|
|
|
map->image_count *
|
|
|
|
|
BRW_IMAGE_PARAM_SIZE);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
struct anv_push_constants *null_data = NULL;
|
|
|
|
|
const struct brw_image_param *image_param = null_data->images;
|
2016-03-04 20:56:14 +00:00
|
|
|
|
for (uint32_t i = 0; i < map->image_count; i++) {
|
2015-11-18 23:14:05 +00:00
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
|
2017-09-29 00:25:31 +01:00
|
|
|
|
(uintptr_t)&image_param->surface_idx, 1);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
|
2017-09-29 00:25:31 +01:00
|
|
|
|
(uintptr_t)image_param->offset, 2);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
|
2017-09-29 00:25:31 +01:00
|
|
|
|
(uintptr_t)image_param->size, 3);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
|
2017-09-29 00:25:31 +01:00
|
|
|
|
(uintptr_t)image_param->stride, 4);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
|
2017-09-29 00:25:31 +01:00
|
|
|
|
(uintptr_t)image_param->tiling, 3);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
|
2017-09-29 00:25:31 +01:00
|
|
|
|
(uintptr_t)image_param->swizzling, 2);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
|
|
|
|
|
param += BRW_IMAGE_PARAM_SIZE;
|
|
|
|
|
image_param ++;
|
|
|
|
|
}
|
2017-09-29 19:10:22 +01:00
|
|
|
|
assert(param == prog_data->param + prog_data->nr_params);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
|
2016-03-04 20:56:14 +00:00
|
|
|
|
shader->num_uniforms += map->image_count * BRW_IMAGE_PARAM_SIZE * 4;
|
2015-11-18 23:14:05 +00:00
|
|
|
|
}
|
2016-02-18 19:04:53 +00:00
|
|
|
|
|
|
|
|
|
ralloc_free(mem_ctx);
|
2015-10-15 00:39:58 +01:00
|
|
|
|
}
|