anv: Put image params in the descriptor set buffer on gen8 and earlier
This is really where they belong; not push constants. The one downside here is that we can't push them anymore for compute shaders. However, that's a general problem and we should figure out how to push descriptor sets for compute shaders. This lets us bump MAX_IMAGES to 64 on BDW and earlier platforms because we no longer have to worry about push constant overhead limits. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
This commit is contained in:
Jason Ekstrand
Jason Ekstrand
parent
83b943cc2f
commit
3b755b52e8
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@ -90,7 +90,12 @@ anv_descriptor_data_for_type(const struct anv_physical_device *device,
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static unsigned
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anv_descriptor_data_size(enum anv_descriptor_data data)
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{
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return 0;
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unsigned size = 0;
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if (data & ANV_DESCRIPTOR_IMAGE_PARAM)
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size += BRW_IMAGE_PARAM_SIZE * 4;
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return size;
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}
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/** Returns the size in bytes of each descriptor with the given layout */
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@ -902,6 +907,24 @@ VkResult anv_FreeDescriptorSets(
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return VK_SUCCESS;
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}
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static void
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anv_descriptor_set_write_image_param(uint32_t *param_desc_map,
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const struct brw_image_param *param)
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{
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#define WRITE_PARAM_FIELD(field, FIELD) \
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for (unsigned i = 0; i < ARRAY_SIZE(param->field); i++) \
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param_desc_map[BRW_IMAGE_PARAM_##FIELD##_OFFSET + i] = param->field[i]
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WRITE_PARAM_FIELD(offset, OFFSET);
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WRITE_PARAM_FIELD(size, SIZE);
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WRITE_PARAM_FIELD(stride, STRIDE);
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WRITE_PARAM_FIELD(tiling, TILING);
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WRITE_PARAM_FIELD(swizzling, SWIZZLING);
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WRITE_PARAM_FIELD(size, SIZE);
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#undef WRITE_PARAM_FIELD
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}
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void
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anv_descriptor_set_write_image_view(struct anv_device *device,
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struct anv_descriptor_set *set,
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@ -952,6 +975,18 @@ anv_descriptor_set_write_image_view(struct anv_device *device,
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.image_view = image_view,
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.sampler = sampler,
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};
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void *desc_map = set->desc_mem.map + bind_layout->descriptor_offset +
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element * anv_descriptor_size(bind_layout);
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if (bind_layout->data & ANV_DESCRIPTOR_IMAGE_PARAM) {
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/* Storage images can only ever have one plane */
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assert(image_view->n_planes == 1);
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const struct brw_image_param *image_param =
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&image_view->planes[0].storage_image_param;
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anv_descriptor_set_write_image_param(desc_map, image_param);
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}
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}
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void
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@ -973,6 +1008,14 @@ anv_descriptor_set_write_buffer_view(struct anv_device *device,
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.type = type,
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.buffer_view = buffer_view,
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};
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void *desc_map = set->desc_mem.map + bind_layout->descriptor_offset +
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element * anv_descriptor_size(bind_layout);
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if (bind_layout->data & ANV_DESCRIPTOR_IMAGE_PARAM) {
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anv_descriptor_set_write_image_param(desc_map,
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&buffer_view->storage_image_param);
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}
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}
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void
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@ -1096,8 +1096,6 @@ void anv_GetPhysicalDeviceProperties(
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const uint32_t max_samplers = (devinfo->gen >= 8 || devinfo->is_haswell) ?
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128 : 16;
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const uint32_t max_images = devinfo->gen < 9 ? MAX_GEN8_IMAGES : MAX_IMAGES;
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VkSampleCountFlags sample_counts =
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isl_device_get_sample_counts(&pdevice->isl_dev);
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@ -1121,7 +1119,7 @@ void anv_GetPhysicalDeviceProperties(
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.maxPerStageDescriptorUniformBuffers = 64,
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.maxPerStageDescriptorStorageBuffers = 64,
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.maxPerStageDescriptorSampledImages = max_samplers,
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.maxPerStageDescriptorStorageImages = max_images,
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.maxPerStageDescriptorStorageImages = MAX_IMAGES,
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.maxPerStageDescriptorInputAttachments = 64,
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.maxPerStageResources = 250,
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.maxDescriptorSetSamplers = 6 * max_samplers, /* number of stages * maxPerStageDescriptorSamplers */
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@ -1130,7 +1128,7 @@ void anv_GetPhysicalDeviceProperties(
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.maxDescriptorSetStorageBuffers = 6 * 64, /* number of stages * maxPerStageDescriptorStorageBuffers */
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.maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
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.maxDescriptorSetSampledImages = 6 * max_samplers, /* number of stages * maxPerStageDescriptorSampledImages */
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.maxDescriptorSetStorageImages = 6 * max_images, /* number of stages * maxPerStageDescriptorStorageImages */
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.maxDescriptorSetStorageImages = 6 * MAX_IMAGES, /* number of stages * maxPerStageDescriptorStorageImages */
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.maxDescriptorSetInputAttachments = 256,
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.maxVertexInputAttributes = MAX_VBS,
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.maxVertexInputBindings = MAX_VBS,
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@ -35,8 +35,6 @@ struct apply_pipeline_layout_state {
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struct anv_pipeline_layout *layout;
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bool add_bounds_checks;
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unsigned first_image_uniform;
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bool uses_constants;
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uint8_t constants_offset;
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struct {
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@ -46,7 +44,6 @@ struct apply_pipeline_layout_state {
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BITSET_WORD *used;
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uint8_t *surface_offsets;
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uint8_t *sampler_offsets;
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uint8_t *image_offsets;
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} set[MAX_SETS];
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};
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@ -239,11 +236,11 @@ lower_get_buffer_size(nir_intrinsic_instr *intrin,
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nir_src_for_ssa(nir_channel(b, index, 0)));
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}
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static void
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lower_image_intrinsic(nir_intrinsic_instr *intrin,
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static nir_ssa_def *
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build_descriptor_load(nir_deref_instr *deref, unsigned offset,
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unsigned num_components, unsigned bit_size,
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struct apply_pipeline_layout_state *state)
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{
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nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
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nir_variable *var = nir_deref_instr_get_variable(deref);
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unsigned set = var->data.descriptor_set;
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@ -251,47 +248,80 @@ lower_image_intrinsic(nir_intrinsic_instr *intrin,
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unsigned array_size =
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state->layout->set[set].layout->binding[binding].array_size;
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nir_builder *b = &state->builder;
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b->cursor = nir_before_instr(&intrin->instr);
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const struct anv_descriptor_set_binding_layout *bind_layout =
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&state->layout->set[set].layout->binding[binding];
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nir_ssa_def *index = NULL;
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nir_builder *b = &state->builder;
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nir_ssa_def *desc_buffer_index =
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nir_imm_int(b, state->set[set].desc_offset);
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nir_ssa_def *desc_offset =
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nir_imm_int(b, bind_layout->descriptor_offset + offset);
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if (deref->deref_type != nir_deref_type_var) {
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assert(deref->deref_type == nir_deref_type_array);
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index = nir_ssa_for_src(b, deref->arr.index, 1);
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const unsigned descriptor_size = anv_descriptor_size(bind_layout);
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nir_ssa_def *arr_index = nir_ssa_for_src(b, deref->arr.index, 1);
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if (state->add_bounds_checks)
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index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
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} else {
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index = nir_imm_int(b, 0);
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arr_index = nir_umin(b, arr_index, nir_imm_int(b, array_size - 1));
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desc_offset = nir_iadd(b, desc_offset,
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nir_imul_imm(b, arr_index, descriptor_size));
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}
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nir_intrinsic_instr *desc_load =
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nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_ubo);
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desc_load->src[0] = nir_src_for_ssa(desc_buffer_index);
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desc_load->src[1] = nir_src_for_ssa(desc_offset);
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desc_load->num_components = num_components;
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nir_ssa_dest_init(&desc_load->instr, &desc_load->dest,
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num_components, bit_size, NULL);
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nir_builder_instr_insert(b, &desc_load->instr);
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return &desc_load->dest.ssa;
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}
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static void
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lower_image_intrinsic(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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{
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nir_deref_instr *deref = nir_src_as_deref(intrin->src[0]);
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nir_builder *b = &state->builder;
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b->cursor = nir_before_instr(&intrin->instr);
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if (intrin->intrinsic == nir_intrinsic_image_deref_load_param_intel) {
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b->cursor = nir_instr_remove(&intrin->instr);
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nir_intrinsic_instr *load =
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nir_intrinsic_instr_create(b->shader, nir_intrinsic_load_uniform);
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nir_intrinsic_set_base(load, state->first_image_uniform +
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state->set[set].image_offsets[binding] *
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BRW_IMAGE_PARAM_SIZE * 4);
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nir_intrinsic_set_range(load, array_size * BRW_IMAGE_PARAM_SIZE * 4);
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const unsigned param = nir_intrinsic_base(intrin);
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nir_ssa_def *offset =
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nir_imul(b, index, nir_imm_int(b, BRW_IMAGE_PARAM_SIZE * 4));
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offset = nir_iadd(b, offset, nir_imm_int(b, param * 16));
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load->src[0] = nir_src_for_ssa(offset);
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load->num_components = intrin->dest.ssa.num_components;
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nir_ssa_dest_init(&load->instr, &load->dest,
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intrin->dest.ssa.num_components,
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intrin->dest.ssa.bit_size, NULL);
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nir_builder_instr_insert(b, &load->instr);
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nir_ssa_def *desc =
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build_descriptor_load(deref, param * 16,
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intrin->dest.ssa.num_components,
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intrin->dest.ssa.bit_size, state);
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
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nir_src_for_ssa(&load->dest.ssa));
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(desc));
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} else {
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nir_variable *var = nir_deref_instr_get_variable(deref);
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unsigned set = var->data.descriptor_set;
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unsigned binding = var->data.binding;
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unsigned binding_offset = state->set[set].surface_offsets[binding];
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index = nir_iadd(b, index, nir_imm_int(b, binding_offset));
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unsigned array_size =
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state->layout->set[set].layout->binding[binding].array_size;
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nir_ssa_def *index = NULL;
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if (deref->deref_type != nir_deref_type_var) {
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assert(deref->deref_type == nir_deref_type_array);
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index = nir_ssa_for_src(b, deref->arr.index, 1);
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if (state->add_bounds_checks)
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index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
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} else {
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index = nir_imm_int(b, 0);
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}
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index = nir_iadd_imm(b, index, binding_offset);
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nir_rewrite_image_intrinsic(intrin, index, false);
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}
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}
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@ -475,16 +505,6 @@ apply_pipeline_layout_block(nir_block *block,
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}
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}
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static void
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setup_vec4_uniform_value(uint32_t *params, uint32_t offset, unsigned n)
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{
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for (unsigned i = 0; i < n; ++i)
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params[i] = ANV_PARAM_PUSH(offset + i * sizeof(uint32_t));
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for (unsigned i = n; i < 4; ++i)
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params[i] = BRW_PARAM_BUILTIN_ZERO;
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}
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void
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anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
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bool robust_buffer_access,
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@ -508,7 +528,6 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
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state.set[s].used = rzalloc_array(mem_ctx, BITSET_WORD, words);
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state.set[s].surface_offsets = rzalloc_array(mem_ctx, uint8_t, count);
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state.set[s].sampler_offsets = rzalloc_array(mem_ctx, uint8_t, count);
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state.set[s].image_offsets = rzalloc_array(mem_ctx, uint8_t, count);
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}
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nir_foreach_function(function, shader) {
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@ -583,45 +602,9 @@ anv_nir_apply_pipeline_layout(const struct anv_physical_device *pdevice,
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}
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}
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}
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if (binding->data & ANV_DESCRIPTOR_IMAGE_PARAM) {
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state.set[set].image_offsets[b] = map->image_param_count;
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map->image_param_count += binding->array_size;
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}
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}
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}
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if (map->image_param_count > 0) {
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assert(map->image_param_count <= MAX_GEN8_IMAGES);
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assert(shader->num_uniforms == prog_data->nr_params * 4);
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state.first_image_uniform = shader->num_uniforms;
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uint32_t *param = brw_stage_prog_data_add_params(prog_data,
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map->image_param_count *
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BRW_IMAGE_PARAM_SIZE);
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struct anv_push_constants *null_data = NULL;
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const struct brw_image_param *image_param = null_data->images;
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for (uint32_t i = 0; i < map->image_param_count; i++) {
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setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
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(uintptr_t)image_param->offset, 2);
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setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
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(uintptr_t)image_param->size, 3);
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setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
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(uintptr_t)image_param->stride, 4);
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setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
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(uintptr_t)image_param->tiling, 3);
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setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
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(uintptr_t)image_param->swizzling, 2);
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param += BRW_IMAGE_PARAM_SIZE;
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image_param ++;
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}
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assert(param == prog_data->param + prog_data->nr_params);
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shader->num_uniforms += map->image_param_count *
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BRW_IMAGE_PARAM_SIZE * 4;
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assert(shader->num_uniforms == prog_data->nr_params * 4);
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}
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nir_foreach_variable(var, &shader->uniforms) {
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const struct glsl_type *glsl_type = glsl_without_array(var->type);
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@ -154,7 +154,6 @@ anv_shader_bin_write_to_blob(const struct anv_shader_bin *shader,
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blob_write_uint32(blob, shader->bind_map.surface_count);
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blob_write_uint32(blob, shader->bind_map.sampler_count);
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blob_write_uint32(blob, shader->bind_map.image_param_count);
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blob_write_bytes(blob, shader->bind_map.surface_to_descriptor,
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shader->bind_map.surface_count *
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sizeof(*shader->bind_map.surface_to_descriptor));
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@ -194,7 +193,6 @@ anv_shader_bin_create_from_blob(struct anv_device *device,
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struct anv_pipeline_bind_map bind_map;
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bind_map.surface_count = blob_read_uint32(blob);
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bind_map.sampler_count = blob_read_uint32(blob);
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bind_map.image_param_count = blob_read_uint32(blob);
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bind_map.surface_to_descriptor = (void *)
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blob_read_bytes(blob, bind_map.surface_count *
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sizeof(*bind_map.surface_to_descriptor));
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@ -158,7 +158,6 @@ struct gen_l3_config;
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#define MAX_PUSH_CONSTANTS_SIZE 128
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#define MAX_DYNAMIC_BUFFERS 16
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#define MAX_IMAGES 64
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#define MAX_GEN8_IMAGES 8
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#define MAX_PUSH_DESCRIPTORS 32 /* Minimum requirement */
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#define MAX_INLINE_UNIFORM_BLOCK_SIZE 4096
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#define MAX_INLINE_UNIFORM_BLOCK_DESCRIPTORS 32
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@ -2077,9 +2076,6 @@ struct anv_push_constants {
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/* Used for vkCmdDispatchBase */
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uint32_t base_work_group_id[3];
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/* Image data for image_load_store on pre-SKL */
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struct brw_image_param images[MAX_GEN8_IMAGES];
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};
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struct anv_dynamic_state {
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@ -2587,7 +2583,6 @@ mesa_to_vk_shader_stage(gl_shader_stage mesa_stage)
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struct anv_pipeline_bind_map {
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uint32_t surface_count;
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uint32_t sampler_count;
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uint32_t image_param_count;
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struct anv_pipeline_binding * surface_to_descriptor;
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struct anv_pipeline_binding * sampler_to_descriptor;
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@ -2010,7 +2010,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
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gl_shader_stage stage,
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struct anv_state *bt_state)
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{
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const struct gen_device_info *devinfo = &cmd_buffer->device->info;
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struct anv_subpass *subpass = cmd_buffer->state.subpass;
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struct anv_cmd_pipeline_state *pipe_state;
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struct anv_pipeline *pipeline;
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@ -2051,17 +2050,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
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const bool need_client_mem_relocs =
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!cmd_buffer->device->instance->physicalDevice.use_softpin;
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/* We only use push constant space for images before gen9 */
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if (map->image_param_count > 0) {
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VkResult result =
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anv_cmd_buffer_ensure_push_constant_field(cmd_buffer, stage, images);
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if (result != VK_SUCCESS)
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return result;
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cmd_buffer->state.push_constants_dirty |= 1 << stage;
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}
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uint32_t image = 0;
|
||||
for (uint32_t s = 0; s < map->surface_count; s++) {
|
||||
struct anv_pipeline_binding *binding = &map->surface_to_descriptor[s];
|
||||
|
||||
|
|
@ -2201,18 +2189,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
|
|||
assert(surface_state.alloc_size);
|
||||
if (need_client_mem_relocs)
|
||||
add_surface_state_relocs(cmd_buffer, sstate);
|
||||
if (devinfo->gen < 9) {
|
||||
/* We only need the image params on gen8 and earlier. No image
|
||||
* workarounds that require tiling information are required on
|
||||
* SKL and above.
|
||||
*/
|
||||
assert(image < MAX_GEN8_IMAGES);
|
||||
struct brw_image_param *image_param =
|
||||
&cmd_buffer->state.push_constants[stage]->images[image++];
|
||||
|
||||
*image_param =
|
||||
desc->image_view->planes[binding->plane].storage_image_param;
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
|
|
@ -2262,13 +2238,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
|
|||
add_surface_reloc(cmd_buffer, surface_state,
|
||||
desc->buffer_view->address);
|
||||
}
|
||||
if (devinfo->gen < 9) {
|
||||
assert(image < MAX_GEN8_IMAGES);
|
||||
struct brw_image_param *image_param =
|
||||
&cmd_buffer->state.push_constants[stage]->images[image++];
|
||||
|
||||
*image_param = desc->buffer_view->storage_image_param;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -2278,7 +2247,6 @@ emit_binding_table(struct anv_cmd_buffer *cmd_buffer,
|
|||
|
||||
bt_map[s] = surface_state.offset + state_offset;
|
||||
}
|
||||
assert(image == map->image_param_count);
|
||||
|
||||
#if GEN_GEN >= 11
|
||||
/* The PIPE_CONTROL command description says:
|
||||
|
|
|
|||
Loading…
Reference in New Issue