218 lines
6.8 KiB
C
218 lines
6.8 KiB
C
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "anv_nir.h"
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#include "glsl/nir/nir_builder.h"
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struct apply_pipeline_layout_state {
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nir_shader *shader;
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nir_builder builder;
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VkShaderStage stage;
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const struct anv_pipeline_layout *layout;
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bool progress;
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};
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static nir_intrinsic_op
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lowered_op(nir_intrinsic_op op)
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{
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switch (op) {
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case nir_intrinsic_load_ubo_vk:
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return nir_intrinsic_load_ubo;
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case nir_intrinsic_load_ubo_vk_indirect:
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return nir_intrinsic_load_ubo_indirect;
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case nir_intrinsic_load_ssbo_vk:
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return nir_intrinsic_load_ssbo;
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case nir_intrinsic_load_ssbo_vk_indirect:
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return nir_intrinsic_load_ssbo_indirect;
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case nir_intrinsic_store_ssbo_vk:
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return nir_intrinsic_store_ssbo;
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case nir_intrinsic_store_ssbo_vk_indirect:
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return nir_intrinsic_store_ssbo_indirect;
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default:
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unreachable("Invalid intrinsic for lowering");
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}
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}
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static uint32_t
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get_surface_index(unsigned set, unsigned binding,
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struct apply_pipeline_layout_state *state)
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{
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assert(set < state->layout->num_sets);
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struct anv_descriptor_set_layout *set_layout =
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state->layout->set[set].layout;
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assert(binding < set_layout->binding_count);
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assert(set_layout->binding[binding].stage[state->stage].surface_index >= 0);
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uint32_t surface_index =
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state->layout->set[set].stage[state->stage].surface_start +
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set_layout->binding[binding].stage[state->stage].surface_index;
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assert(surface_index < state->layout->stage[state->stage].surface_count);
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return surface_index;
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}
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static bool
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try_lower_intrinsic(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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{
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nir_builder *b = &state->builder;
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int block_idx_src;
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_ubo_vk:
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case nir_intrinsic_load_ubo_vk_indirect:
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case nir_intrinsic_load_ssbo_vk:
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case nir_intrinsic_load_ssbo_vk_indirect:
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block_idx_src = 0;
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break;
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case nir_intrinsic_store_ssbo_vk:
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case nir_intrinsic_store_ssbo_vk_indirect:
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block_idx_src = 1;
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break;
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default:
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return false;
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}
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b->cursor = nir_before_instr(&intrin->instr);
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uint32_t set = intrin->const_index[0];
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uint32_t binding = intrin->const_index[1];
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uint32_t surface_index = get_surface_index(set, binding, state);
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nir_const_value *const_block_idx =
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nir_src_as_const_value(intrin->src[block_idx_src]);
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nir_ssa_def *block_index;
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if (const_block_idx) {
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block_index = nir_imm_int(b, surface_index + const_block_idx->u[0]);
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} else {
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block_index = nir_iadd(b, nir_imm_int(b, surface_index),
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nir_ssa_for_src(b, intrin->src[block_idx_src], 1));
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}
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nir_instr_rewrite_src(&intrin->instr, &intrin->src[block_idx_src],
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nir_src_for_ssa(block_index));
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intrin->intrinsic = lowered_op(intrin->intrinsic);
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/* Shift the offset indices down */
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intrin->const_index[0] = intrin->const_index[2];
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intrin->const_index[1] = intrin->const_index[3];
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return true;
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}
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static void
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lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
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{
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/* No one should have come by and lowered it already */
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assert(tex->sampler);
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unsigned set = tex->sampler->var->data.descriptor_set;
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unsigned binding = tex->sampler->var->data.binding;
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tex->sampler_index = get_surface_index(set, binding, state);
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if (tex->sampler->deref.child) {
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assert(tex->sampler->deref.child->deref_type == nir_deref_type_array);
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nir_deref_array *deref_array =
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nir_deref_as_array(tex->sampler->deref.child);
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tex->sampler_index += deref_array->base_offset;
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if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
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nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
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tex->num_srcs + 1);
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for (unsigned i = 0; i < tex->num_srcs; i++) {
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new_srcs[i].src_type = tex->src[i].src_type;
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nir_instr_move_src(&tex->instr, &new_srcs[i].src, &tex->src[i].src);
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}
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ralloc_free(tex->src);
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tex->src = new_srcs;
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/* Now we can go ahead and move the source over to being a
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* first-class texture source.
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*/
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tex->src[tex->num_srcs].src_type = nir_tex_src_sampler_offset;
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tex->num_srcs++;
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nir_instr_move_src(&tex->instr, &tex->src[tex->num_srcs - 1].src,
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&deref_array->indirect);
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}
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}
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tex->sampler = NULL;
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}
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static bool
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apply_pipeline_layout_block(nir_block *block, void *void_state)
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{
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struct apply_pipeline_layout_state *state = void_state;
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nir_foreach_instr_safe(block, instr) {
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switch (instr->type) {
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case nir_instr_type_intrinsic:
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if (try_lower_intrinsic(nir_instr_as_intrinsic(instr), state))
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state->progress = true;
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break;
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case nir_instr_type_tex:
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lower_tex(nir_instr_as_tex(instr), state);
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/* All texture instructions need lowering */
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state->progress = true;
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break;
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default:
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continue;
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}
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}
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return true;
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}
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bool
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anv_nir_apply_pipeline_layout(nir_shader *shader,
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const struct anv_pipeline_layout *layout)
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{
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struct apply_pipeline_layout_state state = {
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.shader = shader,
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.stage = anv_vk_shader_stage_for_mesa_stage(shader->stage),
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.layout = layout,
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};
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nir_foreach_overload(shader, overload) {
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if (overload->impl) {
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nir_builder_init(&state.builder, overload->impl);
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nir_foreach_block(overload->impl, apply_pipeline_layout_block, &state);
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nir_metadata_preserve(overload->impl, nir_metadata_block_index |
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nir_metadata_dominance);
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}
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}
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return state.progress;
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}
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