2015-10-15 00:39:58 +01:00
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/*
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "anv_nir.h"
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2015-12-11 00:58:24 +00:00
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#include "program/prog_parameter.h"
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2016-02-05 23:03:04 +00:00
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#include "nir/nir_builder.h"
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2015-10-15 00:39:58 +01:00
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struct apply_pipeline_layout_state {
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nir_shader *shader;
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nir_builder builder;
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2016-02-03 20:14:28 +00:00
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struct {
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BITSET_WORD *used;
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uint8_t *surface_offsets;
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uint8_t *sampler_offsets;
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uint8_t *image_offsets;
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} set[MAX_SETS];
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2015-10-15 00:39:58 +01:00
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};
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2016-02-03 20:14:28 +00:00
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static void
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add_binding(struct apply_pipeline_layout_state *state,
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uint32_t set, uint32_t binding)
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2015-10-15 00:39:58 +01:00
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{
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2016-02-03 20:14:28 +00:00
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BITSET_SET(state->set[set].used, binding);
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2015-10-15 00:39:58 +01:00
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}
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2016-02-03 20:14:28 +00:00
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static void
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add_var_binding(struct apply_pipeline_layout_state *state, nir_variable *var)
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2015-11-14 17:00:35 +00:00
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{
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2016-02-03 20:14:28 +00:00
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add_binding(state, var->data.descriptor_set, var->data.binding);
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2015-11-14 17:00:35 +00:00
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}
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2016-02-03 20:14:28 +00:00
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static bool
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get_used_bindings_block(nir_block *block, void *void_state)
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2015-11-18 23:14:05 +00:00
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{
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2016-02-03 20:14:28 +00:00
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struct apply_pipeline_layout_state *state = void_state;
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2015-11-18 23:14:05 +00:00
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2016-02-03 20:14:28 +00:00
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nir_foreach_instr_safe(block, instr) {
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switch (instr->type) {
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_vulkan_resource_index:
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add_binding(state, nir_intrinsic_desc_set(intrin),
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nir_intrinsic_binding(intrin));
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break;
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case nir_intrinsic_image_load:
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case nir_intrinsic_image_store:
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case nir_intrinsic_image_atomic_add:
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case nir_intrinsic_image_atomic_min:
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case nir_intrinsic_image_atomic_max:
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case nir_intrinsic_image_atomic_and:
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case nir_intrinsic_image_atomic_or:
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case nir_intrinsic_image_atomic_xor:
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case nir_intrinsic_image_atomic_exchange:
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case nir_intrinsic_image_atomic_comp_swap:
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case nir_intrinsic_image_size:
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case nir_intrinsic_image_samples:
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add_var_binding(state, intrin->variables[0]->var);
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break;
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default:
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break;
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}
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break;
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}
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case nir_instr_type_tex: {
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nir_tex_instr *tex = nir_instr_as_tex(instr);
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assert(tex->texture);
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add_var_binding(state, tex->texture->var);
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if (tex->sampler)
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add_var_binding(state, tex->sampler->var);
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break;
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}
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default:
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continue;
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}
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}
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2015-11-18 23:14:05 +00:00
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2016-02-03 20:14:28 +00:00
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return true;
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2015-11-18 23:14:05 +00:00
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}
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2015-10-27 20:42:51 +00:00
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static void
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lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
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struct apply_pipeline_layout_state *state)
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2015-10-15 00:39:58 +01:00
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{
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nir_builder *b = &state->builder;
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b->cursor = nir_before_instr(&intrin->instr);
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2016-02-09 23:32:21 +00:00
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uint32_t set = nir_intrinsic_desc_set(intrin);
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uint32_t binding = nir_intrinsic_binding(intrin);
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2015-10-15 00:39:58 +01:00
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2016-02-03 20:14:28 +00:00
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uint32_t surface_index = state->set[set].surface_offsets[binding];
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2015-10-15 00:39:58 +01:00
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nir_const_value *const_block_idx =
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2015-10-27 20:42:51 +00:00
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nir_src_as_const_value(intrin->src[0]);
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2015-10-15 00:39:58 +01:00
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nir_ssa_def *block_index;
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if (const_block_idx) {
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block_index = nir_imm_int(b, surface_index + const_block_idx->u[0]);
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} else {
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block_index = nir_iadd(b, nir_imm_int(b, surface_index),
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2015-10-27 20:42:51 +00:00
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nir_ssa_for_src(b, intrin->src[0], 1));
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2015-10-15 00:39:58 +01:00
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}
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2015-10-27 20:42:51 +00:00
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assert(intrin->dest.is_ssa);
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nir_ssa_def_rewrite_uses(&intrin->dest.ssa, nir_src_for_ssa(block_index));
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nir_instr_remove(&intrin->instr);
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2015-10-15 00:39:58 +01:00
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}
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static void
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2015-11-14 17:00:35 +00:00
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lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
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unsigned *const_index, nir_tex_src_type src_type,
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struct apply_pipeline_layout_state *state)
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2015-10-15 00:39:58 +01:00
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{
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2015-11-14 17:00:35 +00:00
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if (deref->deref.child) {
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assert(deref->deref.child->deref_type == nir_deref_type_array);
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nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
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2015-10-15 00:39:58 +01:00
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2015-11-14 17:00:35 +00:00
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*const_index += deref_array->base_offset;
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2015-10-15 00:39:58 +01:00
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if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
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nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
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tex->num_srcs + 1);
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for (unsigned i = 0; i < tex->num_srcs; i++) {
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new_srcs[i].src_type = tex->src[i].src_type;
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nir_instr_move_src(&tex->instr, &new_srcs[i].src, &tex->src[i].src);
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}
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ralloc_free(tex->src);
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tex->src = new_srcs;
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/* Now we can go ahead and move the source over to being a
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* first-class texture source.
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*/
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2015-11-14 17:00:35 +00:00
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tex->src[tex->num_srcs].src_type = src_type;
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2015-10-15 00:39:58 +01:00
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tex->num_srcs++;
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2015-11-14 17:00:35 +00:00
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assert(deref_array->indirect.is_ssa);
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nir_instr_rewrite_src(&tex->instr, &tex->src[tex->num_srcs - 1].src,
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deref_array->indirect);
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2015-10-15 00:39:58 +01:00
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}
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}
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2015-11-14 17:00:35 +00:00
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}
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static void
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cleanup_tex_deref(nir_tex_instr *tex, nir_deref_var *deref)
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{
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if (deref->deref.child == NULL)
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return;
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nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
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if (deref_array->deref_array_type != nir_deref_array_type_indirect)
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return;
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nir_instr_rewrite_src(&tex->instr, &deref_array->indirect, NIR_SRC_INIT);
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}
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static void
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lower_tex(nir_tex_instr *tex, struct apply_pipeline_layout_state *state)
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{
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/* No one should have come by and lowered it already */
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2016-02-09 20:13:32 +00:00
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assert(tex->texture);
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2015-10-15 00:39:58 +01:00
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2016-02-03 20:14:28 +00:00
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unsigned set = tex->texture->var->data.descriptor_set;
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unsigned binding = tex->texture->var->data.binding;
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tex->texture_index = state->set[set].surface_offsets[binding];
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2016-02-09 20:13:32 +00:00
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lower_tex_deref(tex, tex->texture, &tex->texture_index,
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2015-11-14 17:00:35 +00:00
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nir_tex_src_texture_offset, state);
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2016-02-09 20:13:32 +00:00
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if (tex->sampler) {
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2016-02-03 20:14:28 +00:00
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unsigned set = tex->sampler->var->data.descriptor_set;
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unsigned binding = tex->sampler->var->data.binding;
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tex->sampler_index = state->set[set].surface_offsets[binding];
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2016-02-09 20:13:32 +00:00
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lower_tex_deref(tex, tex->sampler, &tex->sampler_index,
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nir_tex_src_sampler_offset, state);
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}
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2015-11-14 17:00:35 +00:00
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2016-01-15 02:58:25 +00:00
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/* The backend only ever uses this to mark used surfaces. We don't care
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* about that little optimization so it just needs to be non-zero.
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*/
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tex->texture_array_size = 1;
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2016-02-09 20:13:32 +00:00
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cleanup_tex_deref(tex, tex->texture);
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if (tex->sampler)
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cleanup_tex_deref(tex, tex->sampler);
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2015-11-14 17:00:35 +00:00
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tex->texture = NULL;
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2015-10-15 00:39:58 +01:00
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tex->sampler = NULL;
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}
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static bool
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apply_pipeline_layout_block(nir_block *block, void *void_state)
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{
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struct apply_pipeline_layout_state *state = void_state;
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nir_foreach_instr_safe(block, instr) {
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switch (instr->type) {
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2015-10-27 20:42:51 +00:00
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case nir_instr_type_intrinsic: {
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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if (intrin->intrinsic == nir_intrinsic_vulkan_resource_index) {
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lower_res_index_intrinsic(intrin, state);
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}
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2015-10-15 00:39:58 +01:00
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break;
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2015-10-27 20:42:51 +00:00
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}
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2015-10-15 00:39:58 +01:00
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case nir_instr_type_tex:
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lower_tex(nir_instr_as_tex(instr), state);
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break;
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default:
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continue;
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}
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}
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return true;
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}
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2015-11-18 23:14:05 +00:00
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static void
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2015-12-11 00:58:24 +00:00
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setup_vec4_uniform_value(const union gl_constant_value **params,
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const union gl_constant_value *values,
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2015-11-18 23:14:05 +00:00
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unsigned n)
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{
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static const gl_constant_value zero = { 0 };
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for (unsigned i = 0; i < n; ++i)
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params[i] = &values[i];
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for (unsigned i = n; i < 4; ++i)
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params[i] = &zero;
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}
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2016-02-03 20:14:28 +00:00
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void
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anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
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nir_shader *shader,
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struct brw_stage_prog_data *prog_data)
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2015-10-15 00:39:58 +01:00
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{
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2016-02-03 20:14:28 +00:00
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struct anv_pipeline_layout *layout = pipeline->layout;
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2015-10-15 00:39:58 +01:00
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struct apply_pipeline_layout_state state = {
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.shader = shader,
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};
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2016-02-03 20:14:28 +00:00
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void *mem_ctx = ralloc_context(NULL);
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for (unsigned s = 0; s < layout->num_sets; s++) {
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const unsigned count = layout->set[s].layout->binding_count;
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const unsigned words = BITSET_WORDS(count);
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state.set[s].used = rzalloc_array(mem_ctx, BITSET_WORD, words);
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state.set[s].surface_offsets = rzalloc_array(mem_ctx, uint8_t, count);
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state.set[s].sampler_offsets = rzalloc_array(mem_ctx, uint8_t, count);
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state.set[s].image_offsets = rzalloc_array(mem_ctx, uint8_t, count);
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}
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nir_foreach_function(shader, function) {
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if (function->impl)
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nir_foreach_block(function->impl, get_used_bindings_block, &state);
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}
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struct anv_pipeline_bind_map map = {
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.surface_count = 0,
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.sampler_count = 0,
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};
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for (uint32_t set = 0; set < layout->num_sets; set++) {
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struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
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BITSET_WORD b, _tmp;
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BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
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set_layout->binding_count) {
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if (set_layout->binding[b].stage[shader->stage].surface_index >= 0)
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map.surface_count += set_layout->binding[b].array_size;
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if (set_layout->binding[b].stage[shader->stage].sampler_index >= 0)
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map.sampler_count += set_layout->binding[b].array_size;
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if (set_layout->binding[b].stage[shader->stage].image_index >= 0)
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map.image_count += set_layout->binding[b].array_size;
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}
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}
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map.surface_to_descriptor =
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malloc(map.surface_count * sizeof(struct anv_pipeline_binding));
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map.sampler_to_descriptor =
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malloc(map.sampler_count * sizeof(struct anv_pipeline_binding));
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pipeline->bindings[shader->stage] = map;
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|
|
|
unsigned surface = 0;
|
|
|
|
unsigned sampler = 0;
|
|
|
|
unsigned image = 0;
|
|
|
|
for (uint32_t set = 0; set < layout->num_sets; set++) {
|
|
|
|
struct anv_descriptor_set_layout *set_layout = layout->set[set].layout;
|
|
|
|
|
|
|
|
BITSET_WORD b, _tmp;
|
|
|
|
BITSET_FOREACH_SET(b, _tmp, state.set[set].used,
|
|
|
|
set_layout->binding_count) {
|
|
|
|
unsigned array_size = set_layout->binding[b].array_size;
|
|
|
|
unsigned set_offset = set_layout->binding[b].descriptor_index;
|
|
|
|
|
|
|
|
if (set_layout->binding[b].stage[shader->stage].surface_index >= 0) {
|
|
|
|
state.set[set].surface_offsets[b] = surface;
|
|
|
|
for (unsigned i = 0; i < array_size; i++) {
|
|
|
|
map.surface_to_descriptor[surface + i].set = set;
|
|
|
|
map.surface_to_descriptor[surface + i].offset = set_offset + i;
|
|
|
|
}
|
|
|
|
surface += array_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (set_layout->binding[b].stage[shader->stage].sampler_index >= 0) {
|
|
|
|
state.set[set].sampler_offsets[b] = sampler;
|
|
|
|
for (unsigned i = 0; i < array_size; i++) {
|
|
|
|
map.sampler_to_descriptor[sampler + i].set = set;
|
|
|
|
map.sampler_to_descriptor[sampler + i].offset = set_offset + i;
|
|
|
|
}
|
|
|
|
sampler += array_size;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (set_layout->binding[b].stage[shader->stage].image_index >= 0) {
|
|
|
|
state.set[set].image_offsets[b] = image;
|
|
|
|
image += array_size;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2015-12-28 18:56:31 +00:00
|
|
|
nir_foreach_function(shader, function) {
|
|
|
|
if (function->impl) {
|
|
|
|
nir_builder_init(&state.builder, function->impl);
|
|
|
|
nir_foreach_block(function->impl, apply_pipeline_layout_block, &state);
|
|
|
|
nir_metadata_preserve(function->impl, nir_metadata_block_index |
|
2015-10-15 00:39:58 +01:00
|
|
|
nir_metadata_dominance);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2016-02-03 20:14:28 +00:00
|
|
|
if (map.image_count > 0) {
|
2015-11-18 23:14:05 +00:00
|
|
|
nir_foreach_variable(var, &shader->uniforms) {
|
|
|
|
if (glsl_type_is_image(var->type) ||
|
|
|
|
(glsl_type_is_array(var->type) &&
|
|
|
|
glsl_type_is_image(glsl_get_array_element(var->type)))) {
|
|
|
|
/* Images are represented as uniform push constants and the actual
|
|
|
|
* information required for reading/writing to/from the image is
|
|
|
|
* storred in the uniform.
|
|
|
|
*/
|
2016-02-03 20:14:28 +00:00
|
|
|
unsigned set = var->data.descriptor_set;
|
|
|
|
unsigned binding = var->data.binding;
|
|
|
|
unsigned image_index = state.set[set].image_offsets[binding];
|
2015-11-18 23:14:05 +00:00
|
|
|
|
|
|
|
var->data.driver_location = shader->num_uniforms +
|
2015-12-11 06:36:47 +00:00
|
|
|
image_index * BRW_IMAGE_PARAM_SIZE * 4;
|
2015-11-18 23:14:05 +00:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
struct anv_push_constants *null_data = NULL;
|
|
|
|
const gl_constant_value **param = prog_data->param + shader->num_uniforms;
|
|
|
|
const struct brw_image_param *image_param = null_data->images;
|
2016-02-03 20:14:28 +00:00
|
|
|
for (uint32_t i = 0; i < map.image_count; i++) {
|
2015-11-18 23:14:05 +00:00
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
|
2015-12-11 00:58:24 +00:00
|
|
|
(const union gl_constant_value *)&image_param->surface_idx, 1);
|
2015-11-18 23:14:05 +00:00
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
|
2015-12-11 00:58:24 +00:00
|
|
|
(const union gl_constant_value *)image_param->offset, 2);
|
2015-11-18 23:14:05 +00:00
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SIZE_OFFSET,
|
2015-12-11 00:58:24 +00:00
|
|
|
(const union gl_constant_value *)image_param->size, 3);
|
2015-11-18 23:14:05 +00:00
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_STRIDE_OFFSET,
|
2015-12-11 00:58:24 +00:00
|
|
|
(const union gl_constant_value *)image_param->stride, 4);
|
2015-11-18 23:14:05 +00:00
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_TILING_OFFSET,
|
2015-12-11 00:58:24 +00:00
|
|
|
(const union gl_constant_value *)image_param->tiling, 3);
|
2015-11-18 23:14:05 +00:00
|
|
|
setup_vec4_uniform_value(param + BRW_IMAGE_PARAM_SWIZZLING_OFFSET,
|
2015-12-11 00:58:24 +00:00
|
|
|
(const union gl_constant_value *)image_param->swizzling, 2);
|
2015-11-18 23:14:05 +00:00
|
|
|
|
|
|
|
param += BRW_IMAGE_PARAM_SIZE;
|
|
|
|
image_param ++;
|
|
|
|
}
|
|
|
|
|
2016-02-03 20:14:28 +00:00
|
|
|
shader->num_uniforms += map.image_count * BRW_IMAGE_PARAM_SIZE * 4;
|
2015-11-18 23:14:05 +00:00
|
|
|
}
|
2015-10-15 00:39:58 +01:00
|
|
|
}
|