2017-09-01 10:41:18 +01:00
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/*
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* Copyright © 2016 Red Hat.
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* Copyright © 2016 Bas Nieuwenhuizen
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*
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* based in part on anv driver which is:
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* Copyright © 2015 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef RADV_SHADER_H
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#define RADV_SHADER_H
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2019-07-29 16:51:01 +01:00
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#include "ac_binary.h"
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2020-10-08 15:52:36 +01:00
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#include "ac_shader_util.h"
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2019-07-29 16:51:01 +01:00
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#include "amd_family.h"
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#include "radv_constants.h"
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2017-09-01 10:41:18 +01:00
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#include "nir/nir.h"
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2021-10-01 22:45:44 +01:00
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#include "vulkan/runtime/vk_object.h"
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#include "vulkan/runtime/vk_shader_module.h"
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2021-04-10 02:24:05 +01:00
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#include "vulkan/vulkan.h"
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2020-10-08 12:14:21 +01:00
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2022-05-16 05:54:05 +01:00
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#include "aco_shader_info.h"
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2020-08-08 23:51:15 +01:00
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#define RADV_VERT_ATTRIB_MAX MAX2(VERT_ATTRIB_MAX, VERT_ATTRIB_GENERIC0 + MAX_VERTEX_ATTRIBS)
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2020-06-16 16:33:32 +01:00
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struct radv_physical_device;
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2019-07-29 16:51:01 +01:00
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struct radv_device;
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2021-04-10 02:24:05 +01:00
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struct radv_pipeline;
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struct radv_pipeline_cache;
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struct radv_pipeline_key;
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2022-03-16 11:39:47 +00:00
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struct radv_shader_args;
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2021-04-16 11:55:59 +01:00
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struct radv_vs_input_state;
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2020-09-24 14:50:54 +01:00
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struct radv_shader_args;
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2018-04-06 13:10:34 +01:00
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2021-07-02 16:07:51 +01:00
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enum radv_vs_input_alpha_adjust {
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ALPHA_ADJUST_NONE = 0,
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ALPHA_ADJUST_SNORM = 1,
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ALPHA_ADJUST_SSCALED = 2,
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ALPHA_ADJUST_SINT = 3,
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};
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2021-09-24 14:38:56 +01:00
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struct radv_pipeline_key {
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uint32_t has_multiview_view_index : 1;
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uint32_t optimisations_disabled : 1;
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2021-09-29 10:07:02 +01:00
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uint32_t invariant_geom : 1;
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2021-09-29 11:01:57 +01:00
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uint32_t use_ngg : 1;
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2022-02-25 14:54:22 +00:00
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uint32_t adjust_frag_coord_z : 1;
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uint32_t disable_aniso_single_level : 1;
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2022-04-26 13:20:56 +01:00
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uint32_t disable_sinking_load_input_fs : 1;
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2022-05-03 09:39:59 +01:00
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uint32_t image_2d_view_of_3d : 1;
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2022-06-08 13:28:12 +01:00
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uint32_t primitives_generated_query : 1;
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2021-09-24 14:38:56 +01:00
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struct {
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uint32_t instance_rate_inputs;
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uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
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uint8_t vertex_attribute_formats[MAX_VERTEX_ATTRIBS];
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uint32_t vertex_attribute_bindings[MAX_VERTEX_ATTRIBS];
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uint32_t vertex_attribute_offsets[MAX_VERTEX_ATTRIBS];
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uint32_t vertex_attribute_strides[MAX_VERTEX_ATTRIBS];
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uint8_t vertex_binding_align[MAX_VBS];
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2021-07-02 16:07:51 +01:00
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enum radv_vs_input_alpha_adjust vertex_alpha_adjust[MAX_VERTEX_ATTRIBS];
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2021-09-24 14:38:56 +01:00
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uint32_t vertex_post_shuffle;
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uint32_t provoking_vtx_last : 1;
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2021-04-16 11:55:59 +01:00
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uint32_t dynamic_input_state : 1;
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2021-09-24 14:38:56 +01:00
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uint8_t topology;
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} vs;
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struct {
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unsigned tess_input_vertices;
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} tcs;
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struct {
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uint32_t col_format;
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uint32_t is_int8;
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uint32_t is_int10;
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radv: remove color exports in presence of holes
If there is holes, eg. if only MRT0 and MRT2 are exported, we have to
set MRT1 to SPI_SHADER_32_R to avoid a GPU hang but the export can
still be removed from the fragment shader.
fossils-db (Sienna Cichlid):
Totals from 565 (0.42% of 134913) affected shaders:
VGPRs: 13328 -> 11456 (-14.05%)
CodeSize: 613232 -> 548224 (-10.60%); split: -11.13%, +0.53%
LDS: 284672 -> 296960 (+4.32%)
MaxWaves: 17624 -> 17684 (+0.34%)
Instrs: 113056 -> 100445 (-11.15%); split: -11.68%, +0.53%
Latency: 684327 -> 639348 (-6.57%); split: -7.17%, +0.60%
InvThroughput: 122877 -> 104382 (-15.05%); split: -15.18%, +0.13%
VClause: 2601 -> 2323 (-10.69%); split: -10.77%, +0.08%
SClause: 5629 -> 5443 (-3.30%); split: -3.91%, +0.60%
Copies: 9393 -> 8720 (-7.16%); split: -8.22%, +1.05%
PreSGPRs: 14623 -> 13666 (-6.54%); split: -6.76%, +0.22%
PreVGPRs: 9847 -> 8503 (-13.65%)
fossils-db (Polaris10):
Totals from 565 (0.42% of 135960) affected shaders:
SGPRs: 28064 -> 27104 (-3.42%)
VGPRs: 12516 -> 10544 (-15.76%); split: -15.79%, +0.03%
CodeSize: 516920 -> 456536 (-11.68%); split: -11.68%, +0.00%
MaxWaves: 4369 -> 4418 (+1.12%)
Instrs: 97771 -> 85903 (-12.14%); split: -12.14%, +0.00%
Latency: 767482 -> 708545 (-7.68%); split: -7.97%, +0.29%
InvThroughput: 280017 -> 235744 (-15.81%)
VClause: 2270 -> 2090 (-7.93%); split: -8.50%, +0.57%
SClause: 5185 -> 5012 (-3.34%); split: -3.86%, +0.52%
Copies: 8328 -> 7555 (-9.28%); split: -9.35%, +0.07%
Branches: 1143 -> 1113 (-2.62%)
PreSGPRs: 13816 -> 12725 (-7.90%); split: -7.92%, +0.02%
PreVGPRs: 9707 -> 8270 (-14.80%)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15108>
2022-02-21 14:47:46 +00:00
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uint32_t cb_target_mask;
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2021-09-24 14:38:56 +01:00
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uint8_t log2_ps_iter_samples;
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uint8_t num_samples;
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radv: remove color exports in presence of holes
If there is holes, eg. if only MRT0 and MRT2 are exported, we have to
set MRT1 to SPI_SHADER_32_R to avoid a GPU hang but the export can
still be removed from the fragment shader.
fossils-db (Sienna Cichlid):
Totals from 565 (0.42% of 134913) affected shaders:
VGPRs: 13328 -> 11456 (-14.05%)
CodeSize: 613232 -> 548224 (-10.60%); split: -11.13%, +0.53%
LDS: 284672 -> 296960 (+4.32%)
MaxWaves: 17624 -> 17684 (+0.34%)
Instrs: 113056 -> 100445 (-11.15%); split: -11.68%, +0.53%
Latency: 684327 -> 639348 (-6.57%); split: -7.17%, +0.60%
InvThroughput: 122877 -> 104382 (-15.05%); split: -15.18%, +0.13%
VClause: 2601 -> 2323 (-10.69%); split: -10.77%, +0.08%
SClause: 5629 -> 5443 (-3.30%); split: -3.91%, +0.60%
Copies: 9393 -> 8720 (-7.16%); split: -8.22%, +1.05%
PreSGPRs: 14623 -> 13666 (-6.54%); split: -6.76%, +0.22%
PreVGPRs: 9847 -> 8503 (-13.65%)
fossils-db (Polaris10):
Totals from 565 (0.42% of 135960) affected shaders:
SGPRs: 28064 -> 27104 (-3.42%)
VGPRs: 12516 -> 10544 (-15.76%); split: -15.79%, +0.03%
CodeSize: 516920 -> 456536 (-11.68%); split: -11.68%, +0.00%
MaxWaves: 4369 -> 4418 (+1.12%)
Instrs: 97771 -> 85903 (-12.14%); split: -12.14%, +0.00%
Latency: 767482 -> 708545 (-7.68%); split: -7.97%, +0.29%
InvThroughput: 280017 -> 235744 (-15.81%)
VClause: 2270 -> 2090 (-7.93%); split: -8.50%, +0.57%
SClause: 5185 -> 5012 (-3.34%); split: -3.86%, +0.52%
Copies: 8328 -> 7555 (-9.28%); split: -9.35%, +0.07%
Branches: 1143 -> 1113 (-2.62%)
PreSGPRs: 13816 -> 12725 (-7.90%); split: -7.92%, +0.02%
PreVGPRs: 9707 -> 8270 (-14.80%)
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15108>
2022-02-21 14:47:46 +00:00
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bool mrt0_is_dual_src;
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2021-09-29 10:01:31 +01:00
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bool lower_discard_to_demote;
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2022-04-21 11:41:27 +01:00
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uint8_t enable_mrt_output_nan_fixup;
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2022-02-11 08:30:39 +00:00
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bool force_vrs_enabled;
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2022-05-06 11:39:13 +01:00
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/* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
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bool alpha_to_coverage_via_mrtz;
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2022-06-17 15:26:32 +01:00
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bool has_epilog;
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2021-09-24 14:38:56 +01:00
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} ps;
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struct {
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/* Non-zero if a required subgroup size is specified via
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* VK_EXT_subgroup_size_control.
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*/
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uint8_t compute_subgroup_size;
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bool require_full_subgroups;
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} cs;
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};
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2018-03-13 13:54:04 +00:00
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struct radv_nir_compiler_options {
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2021-09-24 14:38:56 +01:00
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struct radv_pipeline_key key;
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2021-04-10 02:24:05 +01:00
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bool robust_buffer_access;
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bool dump_shader;
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bool dump_preoptir;
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bool record_ir;
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bool record_stats;
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bool check_ir;
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bool has_ls_vgpr_init_bug;
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2022-04-21 11:41:27 +01:00
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uint8_t enable_mrt_output_nan_fixup;
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2021-04-10 02:24:05 +01:00
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bool wgp_mode;
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enum radeon_family family;
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2022-05-12 07:50:17 +01:00
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enum amd_gfx_level gfx_level;
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2021-04-10 02:24:05 +01:00
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uint32_t address32_hi;
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2022-05-16 05:35:07 +01:00
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bool has_3d_cube_border_color_mipmap;
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2021-04-10 02:24:05 +01:00
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struct {
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2022-05-16 05:54:05 +01:00
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void (*func)(void *private_data, enum aco_compiler_debug_level level, const char *message);
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2021-04-10 02:24:05 +01:00
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void *private_data;
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} debug;
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2018-03-13 13:54:04 +00:00
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};
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enum radv_ud_index {
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2021-04-10 02:24:05 +01:00
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AC_UD_SCRATCH_RING_OFFSETS = 0,
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AC_UD_PUSH_CONSTANTS = 1,
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AC_UD_INLINE_PUSH_CONSTANTS = 2,
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AC_UD_INDIRECT_DESCRIPTOR_SETS = 3,
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AC_UD_VIEW_INDEX = 4,
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AC_UD_STREAMOUT_BUFFERS = 5,
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2022-04-29 15:05:55 +01:00
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AC_UD_NGG_QUERY_STATE = 6,
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2021-06-07 22:23:38 +01:00
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AC_UD_NGG_CULLING_SETTINGS = 7,
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AC_UD_NGG_VIEWPORT = 8,
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2022-01-25 07:57:54 +00:00
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AC_UD_FORCE_VRS_RATES = 9,
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2022-01-23 17:35:12 +00:00
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AC_UD_TASK_RING_ENTRY = 10,
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AC_UD_SHADER_START = 11,
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2021-04-10 02:24:05 +01:00
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AC_UD_VS_VERTEX_BUFFERS = AC_UD_SHADER_START,
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AC_UD_VS_BASE_VERTEX_START_INSTANCE,
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2021-04-16 11:55:59 +01:00
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AC_UD_VS_PROLOG_INPUTS,
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2021-04-10 02:24:05 +01:00
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AC_UD_VS_MAX_UD,
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2022-06-17 15:22:18 +01:00
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AC_UD_PS_EPILOG_PC,
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2021-04-10 02:24:05 +01:00
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AC_UD_PS_MAX_UD,
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AC_UD_CS_GRID_SIZE = AC_UD_SHADER_START,
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2021-03-23 01:20:55 +00:00
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AC_UD_CS_SBT_DESCRIPTORS,
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2022-04-01 15:01:41 +01:00
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AC_UD_CS_RAY_LAUNCH_SIZE_ADDR,
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2022-01-23 17:35:12 +00:00
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AC_UD_CS_TASK_RING_OFFSETS,
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AC_UD_CS_TASK_DRAW_ID,
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AC_UD_CS_TASK_IB,
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2021-04-10 02:24:05 +01:00
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AC_UD_CS_MAX_UD,
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AC_UD_GS_MAX_UD,
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AC_UD_TCS_MAX_UD,
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AC_UD_TES_MAX_UD,
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AC_UD_MAX_UD = AC_UD_TCS_MAX_UD,
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2018-03-13 13:54:04 +00:00
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};
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2018-10-05 16:45:58 +01:00
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struct radv_stream_output {
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2021-04-10 02:24:05 +01:00
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uint8_t location;
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uint8_t buffer;
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uint16_t offset;
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uint8_t component_mask;
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uint8_t stream;
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2018-10-05 16:45:58 +01:00
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};
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struct radv_streamout_info {
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2021-04-10 02:24:05 +01:00
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uint16_t num_outputs;
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struct radv_stream_output outputs[MAX_SO_OUTPUTS];
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uint16_t strides[MAX_SO_BUFFERS];
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uint32_t enabled_stream_buffers_mask;
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2018-10-05 16:45:58 +01:00
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};
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2019-09-03 16:39:23 +01:00
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struct radv_userdata_info {
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2021-04-10 02:24:05 +01:00
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int8_t sgpr_idx;
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uint8_t num_sgprs;
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2019-09-03 16:39:23 +01:00
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};
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struct radv_userdata_locations {
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2021-04-10 02:24:05 +01:00
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struct radv_userdata_info descriptor_sets[MAX_SETS];
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struct radv_userdata_info shader_data[AC_UD_MAX_UD];
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uint32_t descriptor_sets_enabled;
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2019-09-03 16:39:23 +01:00
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};
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struct radv_vs_output_info {
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2021-04-10 02:24:05 +01:00
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uint8_t vs_output_param_offset[VARYING_SLOT_MAX];
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uint8_t clip_dist_mask;
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uint8_t cull_dist_mask;
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uint8_t param_exports;
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2021-10-28 15:52:35 +01:00
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uint8_t prim_param_exports;
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2021-04-10 02:24:05 +01:00
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bool writes_pointsize;
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bool writes_layer;
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2021-10-28 15:52:35 +01:00
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bool writes_layer_per_primitive;
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2021-04-10 02:24:05 +01:00
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bool writes_viewport_index;
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2021-10-28 15:52:35 +01:00
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bool writes_viewport_index_per_primitive;
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2021-04-10 02:24:05 +01:00
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bool writes_primitive_shading_rate;
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2021-12-17 16:50:35 +00:00
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bool writes_primitive_shading_rate_per_primitive;
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2021-04-10 02:24:05 +01:00
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bool export_prim_id;
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2021-09-24 12:55:10 +01:00
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bool export_clip_dists;
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2021-04-10 02:24:05 +01:00
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unsigned pos_exports;
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2019-09-03 16:39:23 +01:00
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};
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struct radv_es_output_info {
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2021-04-10 02:24:05 +01:00
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|
|
uint32_t esgs_itemsize;
|
2019-09-03 16:39:23 +01:00
|
|
|
};
|
|
|
|
|
2019-09-03 10:14:18 +01:00
|
|
|
struct gfx9_gs_info {
|
2021-04-10 02:24:05 +01:00
|
|
|
uint32_t vgt_gs_onchip_cntl;
|
|
|
|
uint32_t vgt_gs_max_prims_per_subgroup;
|
|
|
|
uint32_t vgt_esgs_ring_itemsize;
|
|
|
|
uint32_t lds_size;
|
2019-09-03 10:14:18 +01:00
|
|
|
};
|
|
|
|
|
2019-09-03 10:20:54 +01:00
|
|
|
struct gfx10_ngg_info {
|
2021-04-10 02:24:05 +01:00
|
|
|
uint16_t ngg_emit_size; /* in dwords */
|
|
|
|
uint32_t hw_max_esverts;
|
|
|
|
uint32_t max_gsprims;
|
|
|
|
uint32_t max_out_verts;
|
|
|
|
uint32_t prim_amp_factor;
|
|
|
|
uint32_t vgt_esgs_ring_itemsize;
|
|
|
|
uint32_t esgs_ring_size;
|
|
|
|
bool max_vert_out_per_gs_instance;
|
2021-06-07 22:33:01 +01:00
|
|
|
bool enable_vertex_grouping;
|
2019-09-03 10:20:54 +01:00
|
|
|
};
|
|
|
|
|
2018-03-13 13:49:11 +00:00
|
|
|
struct radv_shader_info {
|
2021-07-29 16:47:44 +01:00
|
|
|
uint64_t inline_push_constant_mask;
|
|
|
|
bool can_inline_all_push_constants;
|
2021-04-10 02:24:05 +01:00
|
|
|
bool loads_push_constants;
|
|
|
|
bool loads_dynamic_offsets;
|
|
|
|
uint32_t desc_set_used_mask;
|
2021-10-06 13:18:01 +01:00
|
|
|
bool uses_view_index;
|
2021-04-10 02:24:05 +01:00
|
|
|
bool uses_invocation_id;
|
|
|
|
bool uses_prim_id;
|
|
|
|
uint8_t wave_size;
|
|
|
|
uint8_t ballot_bit_size;
|
|
|
|
struct radv_userdata_locations user_sgprs_locs;
|
|
|
|
bool is_ngg;
|
|
|
|
bool is_ngg_passthrough;
|
2021-06-07 22:23:38 +01:00
|
|
|
bool has_ngg_culling;
|
2021-07-05 14:26:18 +01:00
|
|
|
bool has_ngg_early_prim_export;
|
2021-06-07 22:23:38 +01:00
|
|
|
uint32_t num_lds_blocks_when_not_culling;
|
2021-04-10 02:24:05 +01:00
|
|
|
uint32_t num_tess_patches;
|
2021-08-11 07:54:28 +01:00
|
|
|
unsigned workgroup_size;
|
2022-01-25 07:57:54 +00:00
|
|
|
bool force_vrs_per_vertex;
|
2021-04-10 02:24:05 +01:00
|
|
|
struct {
|
|
|
|
uint8_t input_usage_mask[RADV_VERT_ATTRIB_MAX];
|
|
|
|
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
|
|
|
bool needs_draw_id;
|
|
|
|
bool needs_instance_id;
|
|
|
|
struct radv_vs_output_info outinfo;
|
|
|
|
struct radv_es_output_info es_info;
|
|
|
|
bool as_es;
|
|
|
|
bool as_ls;
|
|
|
|
bool tcs_in_out_eq;
|
|
|
|
uint64_t tcs_temp_only_input_mask;
|
|
|
|
uint8_t num_linked_outputs;
|
|
|
|
bool needs_base_instance;
|
radv,aco: use per-attribute vertex descriptors for robustness
We have to use a different num_records for each attribute to correctly
implement robust buffer access.
fossil-db (GFX10.3, robustBufferAccess enabled):
Totals from 60059 (41.06% of 146267) affected shaders:
VGPRs: 2169040 -> 2169024 (-0.00%); split: -0.02%, +0.02%
CodeSize: 79473128 -> 81156016 (+2.12%); split: -0.00%, +2.12%
MaxWaves: 1635360 -> 1635258 (-0.01%); split: +0.00%, -0.01%
Instrs: 15559040 -> 15793205 (+1.51%); split: -0.01%, +1.52%
Latency: 90954792 -> 91308768 (+0.39%); split: -0.30%, +0.69%
InvThroughput: 14937873 -> 14958761 (+0.14%); split: -0.04%, +0.18%
VClause: 444280 -> 412074 (-7.25%); split: -9.22%, +1.97%
SClause: 588545 -> 644141 (+9.45%); split: -0.54%, +9.99%
Copies: 1010395 -> 1011232 (+0.08%); split: -0.44%, +0.53%
Branches: 274279 -> 274282 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1431171 -> 1405056 (-1.82%); split: -2.89%, +1.07%
PreVGPRs: 1575253 -> 1575259 (+0.00%)
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7871>
2020-12-01 17:41:16 +00:00
|
|
|
bool use_per_attribute_vb_descs;
|
|
|
|
uint32_t vb_desc_usage_mask;
|
2021-04-16 11:55:59 +01:00
|
|
|
bool has_prolog;
|
|
|
|
bool dynamic_inputs;
|
2021-04-10 02:24:05 +01:00
|
|
|
} vs;
|
|
|
|
struct {
|
|
|
|
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
|
|
|
uint8_t num_stream_output_components[4];
|
|
|
|
uint8_t output_streams[VARYING_SLOT_VAR31 + 1];
|
|
|
|
uint8_t max_stream;
|
|
|
|
unsigned gsvs_vertex_size;
|
|
|
|
unsigned max_gsvs_emit_size;
|
|
|
|
unsigned vertices_in;
|
|
|
|
unsigned vertices_out;
|
|
|
|
unsigned output_prim;
|
|
|
|
unsigned invocations;
|
|
|
|
unsigned es_type; /* GFX9: VS or TES */
|
|
|
|
uint8_t num_linked_inputs;
|
|
|
|
} gs;
|
|
|
|
struct {
|
|
|
|
uint8_t output_usage_mask[VARYING_SLOT_VAR31 + 1];
|
|
|
|
struct radv_vs_output_info outinfo;
|
|
|
|
struct radv_es_output_info es_info;
|
|
|
|
bool as_es;
|
2022-01-19 01:43:15 +00:00
|
|
|
enum tess_primitive_mode _primitive_mode;
|
2021-04-10 02:24:05 +01:00
|
|
|
enum gl_tess_spacing spacing;
|
|
|
|
bool ccw;
|
|
|
|
bool point_mode;
|
|
|
|
uint8_t num_linked_inputs;
|
|
|
|
uint8_t num_linked_patch_inputs;
|
|
|
|
uint8_t num_linked_outputs;
|
|
|
|
} tes;
|
|
|
|
struct {
|
|
|
|
bool uses_sample_shading;
|
|
|
|
bool needs_sample_positions;
|
|
|
|
bool writes_memory;
|
|
|
|
bool writes_z;
|
|
|
|
bool writes_stencil;
|
|
|
|
bool writes_sample_mask;
|
|
|
|
bool has_pcoord;
|
|
|
|
bool prim_id_input;
|
|
|
|
bool layer_input;
|
|
|
|
bool viewport_index_input;
|
|
|
|
uint8_t num_input_clips_culls;
|
|
|
|
uint32_t input_mask;
|
2021-10-28 15:52:35 +01:00
|
|
|
uint32_t input_per_primitive_mask;
|
2021-04-10 02:24:05 +01:00
|
|
|
uint32_t flat_shaded_mask;
|
|
|
|
uint32_t explicit_shaded_mask;
|
|
|
|
uint32_t float16_shaded_mask;
|
|
|
|
uint32_t num_interp;
|
2021-10-28 15:52:35 +01:00
|
|
|
uint32_t num_prim_interp;
|
2021-04-10 02:24:05 +01:00
|
|
|
bool can_discard;
|
|
|
|
bool early_fragment_test;
|
|
|
|
bool post_depth_coverage;
|
|
|
|
bool reads_sample_mask_in;
|
2021-10-04 17:37:15 +01:00
|
|
|
bool reads_front_face;
|
|
|
|
bool reads_sample_id;
|
|
|
|
bool reads_frag_shading_rate;
|
|
|
|
bool reads_barycentric_model;
|
|
|
|
bool reads_persp_sample;
|
|
|
|
bool reads_persp_center;
|
|
|
|
bool reads_persp_centroid;
|
|
|
|
bool reads_linear_sample;
|
|
|
|
bool reads_linear_center;
|
|
|
|
bool reads_linear_centroid;
|
|
|
|
uint8_t reads_frag_coord_mask;
|
|
|
|
uint8_t reads_sample_pos_mask;
|
2021-04-10 02:24:05 +01:00
|
|
|
uint8_t depth_layout;
|
|
|
|
bool allow_flat_shading;
|
2022-06-17 15:26:32 +01:00
|
|
|
bool has_epilog;
|
2021-10-04 18:05:38 +01:00
|
|
|
unsigned spi_ps_input;
|
2021-04-10 02:24:05 +01:00
|
|
|
} ps;
|
|
|
|
struct {
|
|
|
|
bool uses_grid_size;
|
|
|
|
bool uses_block_id[3];
|
|
|
|
bool uses_thread_id[3];
|
|
|
|
bool uses_local_invocation_idx;
|
|
|
|
unsigned block_size[3];
|
2021-03-23 01:20:55 +00:00
|
|
|
|
2021-09-24 14:10:32 +01:00
|
|
|
uint8_t subgroup_size;
|
|
|
|
|
2021-03-23 01:20:55 +00:00
|
|
|
bool uses_sbt;
|
2021-04-11 00:04:42 +01:00
|
|
|
bool uses_ray_launch_size;
|
2022-01-18 15:37:34 +00:00
|
|
|
bool uses_task_rings;
|
2021-04-10 02:24:05 +01:00
|
|
|
} cs;
|
|
|
|
struct {
|
|
|
|
uint64_t tes_inputs_read;
|
|
|
|
uint64_t tes_patch_inputs_read;
|
|
|
|
unsigned tcs_vertices_out;
|
|
|
|
uint32_t num_lds_blocks;
|
|
|
|
uint8_t num_linked_inputs;
|
|
|
|
uint8_t num_linked_outputs;
|
|
|
|
uint8_t num_linked_patch_outputs;
|
|
|
|
bool tes_reads_tess_factors : 1;
|
|
|
|
} tcs;
|
2021-10-28 15:45:18 +01:00
|
|
|
struct {
|
|
|
|
struct radv_vs_output_info outinfo;
|
2022-01-19 03:17:27 +00:00
|
|
|
enum shader_prim output_prim;
|
2022-05-20 17:12:36 +01:00
|
|
|
bool needs_ms_scratch_ring;
|
2021-10-28 15:45:18 +01:00
|
|
|
} ms;
|
2021-04-10 02:24:05 +01:00
|
|
|
|
|
|
|
struct radv_streamout_info so;
|
|
|
|
|
|
|
|
struct gfx9_gs_info gs_ring_info;
|
|
|
|
struct gfx10_ngg_info ngg_info;
|
2018-03-13 13:49:11 +00:00
|
|
|
};
|
|
|
|
|
2021-04-16 11:55:59 +01:00
|
|
|
struct radv_vs_input_state {
|
|
|
|
uint32_t attribute_mask;
|
2021-07-01 19:42:59 +01:00
|
|
|
uint32_t misaligned_mask;
|
|
|
|
uint32_t possibly_misaligned_mask;
|
2021-04-16 11:55:59 +01:00
|
|
|
|
|
|
|
uint32_t instance_rate_inputs;
|
|
|
|
uint32_t nontrivial_divisors;
|
2022-04-18 13:46:09 +01:00
|
|
|
uint32_t zero_divisors;
|
2021-04-16 11:55:59 +01:00
|
|
|
uint32_t post_shuffle;
|
|
|
|
/* Having two separate fields instead of a single uint64_t makes it easier to remove attributes
|
|
|
|
* using bitwise arithmetic.
|
|
|
|
*/
|
|
|
|
uint32_t alpha_adjust_lo;
|
|
|
|
uint32_t alpha_adjust_hi;
|
2021-07-01 19:42:59 +01:00
|
|
|
|
|
|
|
uint8_t bindings[MAX_VERTEX_ATTRIBS];
|
|
|
|
uint32_t divisors[MAX_VERTEX_ATTRIBS];
|
|
|
|
uint32_t offsets[MAX_VERTEX_ATTRIBS];
|
2021-04-16 11:55:59 +01:00
|
|
|
uint8_t formats[MAX_VERTEX_ATTRIBS];
|
|
|
|
uint8_t format_align_req_minus_1[MAX_VERTEX_ATTRIBS];
|
|
|
|
uint8_t format_sizes[MAX_VERTEX_ATTRIBS];
|
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_vs_prolog_key {
|
2021-07-01 20:20:36 +01:00
|
|
|
const struct radv_vs_input_state *state;
|
2021-04-16 11:55:59 +01:00
|
|
|
unsigned num_attributes;
|
|
|
|
uint32_t misaligned_mask;
|
|
|
|
bool as_ls;
|
|
|
|
bool is_ngg;
|
|
|
|
bool wave32;
|
|
|
|
gl_shader_stage next_stage;
|
|
|
|
};
|
|
|
|
|
2022-06-17 15:27:33 +01:00
|
|
|
struct radv_ps_epilog_key {
|
|
|
|
uint32_t spi_shader_col_format;
|
|
|
|
|
|
|
|
/* Bitmasks, each bit represents one of the 8 MRTs. */
|
|
|
|
uint8_t color_is_int8;
|
|
|
|
uint8_t color_is_int10;
|
|
|
|
uint8_t enable_mrt_output_nan_fixup;
|
|
|
|
|
|
|
|
bool wave32;
|
|
|
|
};
|
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
enum radv_shader_binary_type { RADV_BINARY_TYPE_LEGACY, RADV_BINARY_TYPE_RTLD };
|
2019-07-01 00:29:24 +01:00
|
|
|
|
|
|
|
struct radv_shader_binary {
|
2021-04-10 02:24:05 +01:00
|
|
|
enum radv_shader_binary_type type;
|
|
|
|
gl_shader_stage stage;
|
|
|
|
bool is_gs_copy_shader;
|
2019-07-01 00:29:24 +01:00
|
|
|
|
2021-09-22 09:13:01 +01:00
|
|
|
struct ac_shader_config config;
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_shader_info info;
|
2019-07-01 00:29:24 +01:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
/* Self-referential size so we avoid consistency issues. */
|
|
|
|
uint32_t total_size;
|
2019-07-01 00:29:24 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_shader_binary_legacy {
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_shader_binary base;
|
|
|
|
unsigned code_size;
|
|
|
|
unsigned exec_size;
|
|
|
|
unsigned ir_size;
|
|
|
|
unsigned disasm_size;
|
|
|
|
unsigned stats_size;
|
|
|
|
|
|
|
|
/* data has size of stats_size + code_size + ir_size + disasm_size + 2,
|
|
|
|
* where the +2 is for 0 of the ir strings. */
|
|
|
|
uint8_t data[0];
|
2019-07-01 00:29:24 +01:00
|
|
|
};
|
|
|
|
|
|
|
|
struct radv_shader_binary_rtld {
|
2021-04-10 02:24:05 +01:00
|
|
|
struct radv_shader_binary base;
|
|
|
|
unsigned elf_size;
|
|
|
|
unsigned llvm_ir_size;
|
|
|
|
uint8_t data[0];
|
2019-07-01 00:29:24 +01:00
|
|
|
};
|
|
|
|
|
2022-06-16 15:32:56 +01:00
|
|
|
struct radv_shader_part_binary {
|
2021-04-16 11:55:59 +01:00
|
|
|
uint8_t num_sgprs;
|
|
|
|
uint8_t num_vgprs;
|
|
|
|
uint8_t num_preserved_sgprs;
|
|
|
|
unsigned code_size;
|
2021-10-15 09:03:21 +01:00
|
|
|
unsigned disasm_size;
|
2021-04-16 11:55:59 +01:00
|
|
|
uint8_t data[0];
|
|
|
|
};
|
|
|
|
|
2021-05-14 12:44:17 +01:00
|
|
|
struct radv_shader_arena {
|
|
|
|
struct list_head list;
|
|
|
|
struct list_head entries;
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
char *ptr;
|
|
|
|
};
|
|
|
|
|
|
|
|
union radv_shader_arena_block {
|
|
|
|
struct list_head pool;
|
|
|
|
struct {
|
|
|
|
/* List of blocks in the arena, sorted by address. */
|
|
|
|
struct list_head list;
|
|
|
|
/* For holes, a list_head for the free-list. For allocations, freelist.prev=NULL and
|
|
|
|
* freelist.next is a pointer associated with the allocation.
|
|
|
|
*/
|
|
|
|
struct list_head freelist;
|
|
|
|
struct radv_shader_arena *arena;
|
|
|
|
uint32_t offset;
|
|
|
|
uint32_t size;
|
|
|
|
};
|
|
|
|
};
|
|
|
|
|
2021-10-27 12:20:29 +01:00
|
|
|
struct radv_shader {
|
2021-04-10 02:24:05 +01:00
|
|
|
uint32_t ref_count;
|
|
|
|
|
2021-11-05 12:58:12 +00:00
|
|
|
uint64_t va;
|
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
struct ac_shader_config config;
|
|
|
|
uint8_t *code_ptr;
|
|
|
|
uint32_t code_size;
|
|
|
|
uint32_t exec_size;
|
|
|
|
struct radv_shader_info info;
|
|
|
|
|
2022-05-12 07:50:17 +01:00
|
|
|
/* debug only */
|
2021-04-10 02:24:05 +01:00
|
|
|
char *spirv;
|
|
|
|
uint32_t spirv_size;
|
|
|
|
char *nir_string;
|
|
|
|
char *disasm_string;
|
|
|
|
char *ir_string;
|
|
|
|
uint32_t *statistics;
|
2017-09-01 10:41:18 +01:00
|
|
|
};
|
|
|
|
|
2022-02-09 13:48:07 +00:00
|
|
|
struct radv_trap_handler_shader {
|
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
union radv_shader_arena_block *alloc;
|
|
|
|
};
|
|
|
|
|
2022-06-16 15:32:56 +01:00
|
|
|
struct radv_shader_part {
|
2021-04-16 11:55:59 +01:00
|
|
|
struct radeon_winsys_bo *bo;
|
|
|
|
union radv_shader_arena_block *alloc;
|
|
|
|
uint32_t rsrc1;
|
|
|
|
uint8_t num_preserved_sgprs;
|
2021-10-15 13:27:38 +01:00
|
|
|
bool nontrivial_divisors;
|
2021-10-15 09:03:21 +01:00
|
|
|
|
|
|
|
/* debug only */
|
|
|
|
char *disasm_string;
|
2021-04-16 11:55:59 +01:00
|
|
|
};
|
|
|
|
|
2022-03-29 08:26:40 +01:00
|
|
|
struct radv_pipeline_layout;
|
|
|
|
|
2022-01-10 16:16:16 +00:00
|
|
|
void radv_optimize_nir(struct nir_shader *shader, bool optimize_conservatively, bool allow_copies);
|
2021-07-05 08:05:43 +01:00
|
|
|
void radv_optimize_nir_algebraic(nir_shader *shader, bool opt_offsets);
|
2021-04-10 02:24:05 +01:00
|
|
|
bool radv_nir_lower_ycbcr_textures(nir_shader *shader, const struct radv_pipeline_layout *layout);
|
|
|
|
|
2022-01-14 22:08:27 +00:00
|
|
|
bool radv_nir_lower_ray_queries(nir_shader *shader, struct radv_device *device);
|
|
|
|
|
radv,aco: lower vulkan_resource_index in NIR
fossil-db (Sienna Cichlid):
Totals from 31338 (19.31% of 162293) affected shaders:
MaxWaves: 758634 -> 758616 (-0.00%)
Instrs: 26398289 -> 26378282 (-0.08%); split: -0.09%, +0.01%
CodeSize: 141048208 -> 140971060 (-0.05%); split: -0.07%, +0.01%
VGPRs: 1373656 -> 1373736 (+0.01%)
SpillSGPRs: 9944 -> 9924 (-0.20%); split: -0.24%, +0.04%
SpillVGPRs: 1892 -> 1898 (+0.32%); split: -0.95%, +1.27%
Latency: 308570144 -> 308528462 (-0.01%); split: -0.03%, +0.02%
InvThroughput: 57698072 -> 57684901 (-0.02%); split: -0.07%, +0.04%
VClause: 440357 -> 440602 (+0.06%); split: -0.02%, +0.08%
SClause: 974724 -> 973315 (-0.14%); split: -0.18%, +0.04%
Copies: 1944925 -> 1945103 (+0.01%); split: -0.11%, +0.12%
Branches: 799444 -> 799461 (+0.00%); split: -0.00%, +0.00%
PreSGPRs: 1619860 -> 1619233 (-0.04%); split: -0.05%, +0.02%
PreVGPRs: 1252813 -> 1252863 (+0.00%); split: -0.00%, +0.00%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12773>
2021-08-04 12:59:26 +01:00
|
|
|
void radv_nir_apply_pipeline_layout(nir_shader *shader, struct radv_device *device,
|
|
|
|
const struct radv_pipeline_layout *layout,
|
|
|
|
const struct radv_shader_info *info,
|
|
|
|
const struct radv_shader_args *args);
|
|
|
|
|
2022-04-05 12:09:35 +01:00
|
|
|
struct radv_pipeline_stage;
|
|
|
|
|
2022-04-13 08:55:45 +01:00
|
|
|
nir_shader *radv_shader_spirv_to_nir(struct radv_device *device,
|
|
|
|
const struct radv_pipeline_stage *stage,
|
|
|
|
const struct radv_pipeline_key *key);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
2022-05-12 07:50:17 +01:00
|
|
|
void radv_nir_lower_abi(nir_shader *shader, enum amd_gfx_level gfx_level,
|
|
|
|
const struct radv_shader_info *info, const struct radv_shader_args *args,
|
2022-05-16 15:42:22 +01:00
|
|
|
const struct radv_pipeline_key *pl_key, bool use_llvm);
|
2022-03-16 11:39:47 +00:00
|
|
|
|
2021-05-14 12:44:17 +01:00
|
|
|
void radv_init_shader_arenas(struct radv_device *device);
|
|
|
|
void radv_destroy_shader_arenas(struct radv_device *device);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
2022-05-18 10:26:53 +01:00
|
|
|
struct radv_pipeline_shader_stack_size;
|
|
|
|
|
2021-10-06 14:28:20 +01:00
|
|
|
VkResult radv_create_shaders(struct radv_pipeline *pipeline,
|
|
|
|
struct radv_pipeline_layout *pipeline_layout,
|
|
|
|
struct radv_device *device, struct radv_pipeline_cache *cache,
|
|
|
|
const struct radv_pipeline_key *key,
|
2022-04-07 15:01:10 +01:00
|
|
|
const VkPipelineShaderStageCreateInfo *pStages,
|
|
|
|
uint32_t stageCount,
|
2021-08-27 03:20:59 +01:00
|
|
|
const VkPipelineCreateFlags flags, const uint8_t *custom_hash,
|
2022-05-18 10:26:53 +01:00
|
|
|
const VkPipelineCreationFeedbackCreateInfo *creation_feedback,
|
|
|
|
struct radv_pipeline_shader_stack_size **stack_sizes,
|
|
|
|
uint32_t *num_stack_sizes,
|
|
|
|
gl_shader_stage *last_vgt_api_stage);
|
2021-04-10 02:24:05 +01:00
|
|
|
|
2021-10-27 09:20:24 +01:00
|
|
|
struct radv_shader_args;
|
|
|
|
|
2021-10-27 12:20:29 +01:00
|
|
|
struct radv_shader *radv_shader_create(struct radv_device *device,
|
|
|
|
const struct radv_shader_binary *binary,
|
2021-10-27 09:20:24 +01:00
|
|
|
bool keep_shader_info, bool from_cache,
|
|
|
|
const struct radv_shader_args *args);
|
2022-04-13 08:55:45 +01:00
|
|
|
struct radv_shader *radv_shader_nir_to_asm(
|
2022-04-05 12:09:35 +01:00
|
|
|
struct radv_device *device, struct radv_pipeline_stage *stage, struct nir_shader *const *shaders,
|
|
|
|
int shader_count, const struct radv_pipeline_key *key, bool keep_shader_info, bool keep_statistic_info,
|
|
|
|
struct radv_shader_binary **binary_out);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2021-11-05 12:30:28 +00:00
|
|
|
bool radv_shader_binary_upload(struct radv_device *device, const struct radv_shader_binary *binary,
|
2021-11-05 12:58:12 +00:00
|
|
|
struct radv_shader *shader, void *dest_ptr);
|
|
|
|
|
|
|
|
union radv_shader_arena_block *radv_alloc_shader_memory(struct radv_device *device, uint32_t size,
|
|
|
|
void *ptr);
|
|
|
|
void radv_free_shader_memory(struct radv_device *device, union radv_shader_arena_block *alloc);
|
2021-11-05 12:30:28 +00:00
|
|
|
|
2021-10-27 12:20:29 +01:00
|
|
|
struct radv_shader *
|
2017-09-01 10:41:18 +01:00
|
|
|
radv_create_gs_copy_shader(struct radv_device *device, struct nir_shader *nir,
|
2020-09-24 14:50:54 +01:00
|
|
|
struct radv_shader_info *info, const struct radv_shader_args *args,
|
2022-03-18 12:49:44 +00:00
|
|
|
struct radv_shader_binary **binary_out,
|
2020-09-24 14:50:54 +01:00
|
|
|
bool keep_shader_info, bool keep_statistic_info,
|
2021-04-10 02:24:05 +01:00
|
|
|
bool disable_optimizations);
|
2020-08-18 17:44:07 +01:00
|
|
|
|
2022-02-09 13:48:07 +00:00
|
|
|
struct radv_trap_handler_shader *radv_create_trap_handler_shader(struct radv_device *device);
|
|
|
|
uint64_t radv_trap_handler_shader_get_va(const struct radv_trap_handler_shader *trap);
|
|
|
|
void radv_trap_handler_shader_destroy(struct radv_device *device,
|
|
|
|
struct radv_trap_handler_shader *trap);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2022-06-16 15:32:56 +01:00
|
|
|
struct radv_shader_part *radv_create_vs_prolog(struct radv_device *device,
|
|
|
|
const struct radv_vs_prolog_key *key);
|
2021-04-16 11:55:59 +01:00
|
|
|
|
2022-07-14 17:54:20 +01:00
|
|
|
struct radv_shader_part *radv_create_ps_epilog(struct radv_device *device,
|
|
|
|
const struct radv_ps_epilog_key *key);
|
|
|
|
|
2021-10-27 12:20:29 +01:00
|
|
|
void radv_shader_destroy(struct radv_device *device, struct radv_shader *shader);
|
2019-06-01 17:46:21 +01:00
|
|
|
|
2022-06-16 15:32:56 +01:00
|
|
|
void radv_shader_part_destroy(struct radv_device *device, struct radv_shader_part *shader_part);
|
2021-04-16 11:55:59 +01:00
|
|
|
|
2021-10-27 12:20:29 +01:00
|
|
|
uint64_t radv_shader_get_va(const struct radv_shader *shader);
|
|
|
|
struct radv_shader *radv_find_shader(struct radv_device *device, uint64_t pc);
|
2021-05-27 17:29:42 +01:00
|
|
|
|
2021-10-27 12:20:29 +01:00
|
|
|
unsigned radv_get_max_waves(const struct radv_device *device, struct radv_shader *shader,
|
2021-04-10 02:24:05 +01:00
|
|
|
gl_shader_stage stage);
|
2019-06-01 17:46:21 +01:00
|
|
|
|
2021-10-27 10:20:15 +01:00
|
|
|
const char *radv_get_shader_name(const struct radv_shader_info *info, gl_shader_stage stage);
|
2017-09-01 10:41:18 +01:00
|
|
|
|
2022-03-18 07:34:26 +00:00
|
|
|
unsigned radv_compute_spi_ps_input(const struct radv_pipeline_key *pipeline_key,
|
2021-10-04 18:05:38 +01:00
|
|
|
const struct radv_shader_info *info);
|
|
|
|
|
2022-04-06 11:23:40 +01:00
|
|
|
bool radv_can_dump_shader(struct radv_device *device, nir_shader *nir, bool meta_shader);
|
2018-05-11 15:36:02 +01:00
|
|
|
|
2022-04-06 11:54:37 +01:00
|
|
|
bool radv_can_dump_shader_stats(struct radv_device *device, nir_shader *nir);
|
2019-07-29 16:51:01 +01:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
VkResult radv_dump_shader_stats(struct radv_device *device, struct radv_pipeline *pipeline,
|
|
|
|
gl_shader_stage stage, FILE *output);
|
2020-08-20 15:03:36 +01:00
|
|
|
|
2019-11-14 20:14:01 +00:00
|
|
|
static inline unsigned
|
2022-05-12 07:50:17 +01:00
|
|
|
calculate_tess_lds_size(enum amd_gfx_level gfx_level, unsigned tcs_num_input_vertices,
|
2021-04-10 02:24:05 +01:00
|
|
|
unsigned tcs_num_output_vertices, unsigned tcs_num_inputs,
|
|
|
|
unsigned tcs_num_patches, unsigned tcs_num_outputs,
|
|
|
|
unsigned tcs_num_patch_outputs)
|
2020-02-24 14:44:48 +00:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
unsigned input_vertex_size = tcs_num_inputs * 16;
|
|
|
|
unsigned output_vertex_size = tcs_num_outputs * 16;
|
2020-02-24 14:44:48 +00:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
unsigned input_patch_size = tcs_num_input_vertices * input_vertex_size;
|
2020-02-24 14:44:48 +00:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
unsigned pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
|
|
|
|
unsigned output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
|
2020-02-24 14:44:48 +00:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
unsigned output_patch0_offset = input_patch_size * tcs_num_patches;
|
2020-02-24 14:44:48 +00:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
unsigned lds_size = output_patch0_offset + output_patch_size * tcs_num_patches;
|
2020-07-09 09:06:43 +01:00
|
|
|
|
2022-05-12 07:50:17 +01:00
|
|
|
if (gfx_level >= GFX7) {
|
2021-04-10 02:24:05 +01:00
|
|
|
assert(lds_size <= 65536);
|
|
|
|
lds_size = align(lds_size, 512) / 512;
|
|
|
|
} else {
|
|
|
|
assert(lds_size <= 32768);
|
|
|
|
lds_size = align(lds_size, 256) / 256;
|
|
|
|
}
|
2020-07-09 09:06:43 +01:00
|
|
|
|
2021-04-10 02:24:05 +01:00
|
|
|
return lds_size;
|
2020-02-24 14:44:48 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static inline unsigned
|
2021-04-10 02:24:05 +01:00
|
|
|
get_tcs_num_patches(unsigned tcs_num_input_vertices, unsigned tcs_num_output_vertices,
|
|
|
|
unsigned tcs_num_inputs, unsigned tcs_num_outputs,
|
|
|
|
unsigned tcs_num_patch_outputs, unsigned tess_offchip_block_dw_size,
|
2022-05-12 07:50:17 +01:00
|
|
|
enum amd_gfx_level gfx_level, enum radeon_family family)
|
2020-02-24 14:44:48 +00:00
|
|
|
{
|
2021-04-10 02:24:05 +01:00
|
|
|
uint32_t input_vertex_size = tcs_num_inputs * 16;
|
|
|
|
uint32_t input_patch_size = tcs_num_input_vertices * input_vertex_size;
|
|
|
|
uint32_t output_vertex_size = tcs_num_outputs * 16;
|
|
|
|
uint32_t pervertex_output_patch_size = tcs_num_output_vertices * output_vertex_size;
|
|
|
|
uint32_t output_patch_size = pervertex_output_patch_size + tcs_num_patch_outputs * 16;
|
|
|
|
|
|
|
|
/* Ensure that we only need one wave per SIMD so we don't need to check
|
|
|
|
* resource usage. Also ensures that the number of tcs in and out
|
|
|
|
* vertices per threadgroup are at most 256.
|
|
|
|
*/
|
|
|
|
unsigned num_patches = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices) * 4;
|
|
|
|
/* Make sure that the data fits in LDS. This assumes the shaders only
|
|
|
|
* use LDS for the inputs and outputs.
|
|
|
|
*/
|
|
|
|
unsigned hardware_lds_size = 32768;
|
|
|
|
|
|
|
|
/* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
|
|
|
|
* threadgroup, even though there is more than 32 KiB LDS.
|
|
|
|
*
|
|
|
|
* Test: dEQP-VK.tessellation.shader_input_output.barrier
|
|
|
|
*/
|
2022-05-12 07:50:17 +01:00
|
|
|
if (gfx_level >= GFX7 && family != CHIP_STONEY)
|
2021-04-10 02:24:05 +01:00
|
|
|
hardware_lds_size = 65536;
|
|
|
|
|
|
|
|
if (input_patch_size + output_patch_size)
|
|
|
|
num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
|
|
|
|
/* Make sure the output data fits in the offchip buffer */
|
|
|
|
if (output_patch_size)
|
|
|
|
num_patches = MIN2(num_patches, (tess_offchip_block_dw_size * 4) / output_patch_size);
|
|
|
|
/* Not necessary for correctness, but improves performance. The
|
|
|
|
* specific value is taken from the proprietary driver.
|
|
|
|
*/
|
|
|
|
num_patches = MIN2(num_patches, 40);
|
|
|
|
|
|
|
|
/* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
|
2022-05-12 07:50:17 +01:00
|
|
|
if (gfx_level == GFX6) {
|
2021-04-10 02:24:05 +01:00
|
|
|
unsigned one_wave = 64 / MAX2(tcs_num_input_vertices, tcs_num_output_vertices);
|
|
|
|
num_patches = MIN2(num_patches, one_wave);
|
|
|
|
}
|
|
|
|
return num_patches;
|
2020-02-24 14:44:48 +00:00
|
|
|
}
|
|
|
|
|
2022-05-13 20:32:12 +01:00
|
|
|
void radv_lower_io(struct radv_device *device, nir_shader *nir, bool is_mesh_shading);
|
2019-08-29 10:16:44 +01:00
|
|
|
|
2022-04-05 12:09:35 +01:00
|
|
|
bool radv_lower_io_to_mem(struct radv_device *device, struct radv_pipeline_stage *stage,
|
|
|
|
const struct radv_pipeline_key *pl_key);
|
2021-03-11 16:45:10 +00:00
|
|
|
|
2022-04-05 12:09:35 +01:00
|
|
|
void radv_lower_ngg(struct radv_device *device, struct radv_pipeline_stage *ngg_stage,
|
2021-09-10 16:25:05 +01:00
|
|
|
const struct radv_pipeline_key *pl_key);
|
2021-06-08 11:32:35 +01:00
|
|
|
|
2022-05-18 13:59:42 +01:00
|
|
|
bool radv_consider_culling(const struct radv_physical_device *pdevice, struct nir_shader *nir,
|
2021-04-16 11:55:59 +01:00
|
|
|
uint64_t ps_inputs_read, unsigned num_vertices_per_primitive,
|
|
|
|
const struct radv_shader_info *info);
|
2021-04-15 16:21:57 +01:00
|
|
|
|
2020-06-16 16:33:32 +01:00
|
|
|
void radv_get_nir_options(struct radv_physical_device *device);
|
|
|
|
|
2021-07-13 12:29:57 +01:00
|
|
|
bool radv_force_primitive_shading_rate(nir_shader *nir, struct radv_device *device);
|
|
|
|
|
2022-04-05 12:09:35 +01:00
|
|
|
bool radv_lower_fs_intrinsics(nir_shader *nir, const struct radv_pipeline_stage *fs_stage,
|
2022-03-10 14:56:49 +00:00
|
|
|
const struct radv_pipeline_key *key);
|
|
|
|
|
2017-09-01 10:41:18 +01:00
|
|
|
#endif
|