radv,aco: track if a fragment shader needs an epilog

This is currently disabled but it will be used for testing first,
and then for graphics pipeline libraries.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17485>

src/amd/compiler/aco_shader_info.h

@@ -126,6 +126,7 @@ struct aco_shader_info {
       bool writes_z;
       bool writes_stencil;
       bool writes_sample_mask;
+      bool has_epilog;
       uint32_t num_interp;
       unsigned spi_ps_input;
    } ps;

src/amd/vulkan/radv_aco_shader_info.h

@@ -95,6 +95,7 @@ radv_aco_convert_shader_info(struct aco_shader_info *aco_info,
    ASSIGN_FIELD(ps.writes_z);
    ASSIGN_FIELD(ps.writes_stencil);
    ASSIGN_FIELD(ps.writes_sample_mask);
+   ASSIGN_FIELD(ps.has_epilog);
    ASSIGN_FIELD(ps.num_interp);
    ASSIGN_FIELD(ps.spi_ps_input);
    ASSIGN_FIELD(cs.subgroup_size);

src/amd/vulkan/radv_pipeline.c

@@ -3374,6 +3374,8 @@ radv_generate_graphics_pipeline_key(const struct radv_graphics_pipeline *pipelin
    if (device->primitives_generated_query)
       key.primitives_generated_query = true;
 
+   key.ps.has_epilog = false; /* TODO: hook up PS epilogs */
+
    return key;
 }
 

src/amd/vulkan/radv_shader.h

@@ -104,6 +104,8 @@ struct radv_pipeline_key {
 
       /* Used to export alpha through MRTZ for alpha-to-coverage (GFX11+). */
       bool alpha_to_coverage_via_mrtz;
+
+      bool has_epilog;
    } ps;
 
    struct {
@@ -337,6 +339,7 @@ struct radv_shader_info {
       uint8_t reads_sample_pos_mask;
       uint8_t depth_layout;
       bool allow_flat_shading;
+      bool has_epilog;
       unsigned spi_ps_input;
    } ps;
    struct {

src/amd/vulkan/radv_shader_info.c

@@ -479,6 +479,12 @@ radv_nir_shader_info_pass(struct radv_device *device, const struct nir_shader *n
       info->vs.use_per_attribute_vb_descs = device->robust_buffer_access || info->vs.dynamic_inputs;
    }
 
+   if (nir->info.stage == MESA_SHADER_FRAGMENT) {
+      if (pipeline_key->ps.has_epilog) {
+         info->ps.has_epilog = true;
+      }
+   }
+
    /* We have to ensure consistent input register assignments between the main shader and the
     * prolog. */
    info->vs.needs_instance_id |= info->vs.has_prolog;