radv: Lower ABI in NIR for tess/ESGS/NGG shader arguments.
Totals from 58720 (45.64% of 128653) affected shaders: VGPRs: 2056576 -> 2056568 (-0.00%) CodeSize: 153906488 -> 154609536 (+0.46%); split: -0.00%, +0.46% MaxWaves: 1665056 -> 1665058 (+0.00%) Instrs: 29242117 -> 29417265 (+0.60%); split: -0.00%, +0.60% Latency: 134149608 -> 134238738 (+0.07%); split: -0.00%, +0.07% InvThroughput: 20348833 -> 20349641 (+0.00%); split: -0.00%, +0.00% VClause: 489376 -> 489385 (+0.00%) SClause: 729383 -> 729382 (-0.00%) Copies: 2672567 -> 2673132 (+0.02%); split: -0.00%, +0.02% Branches: 1192117 -> 1192121 (+0.00%); split: -0.00%, +0.00% Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Daniel Schürmann <daniel@schuermann.dev> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13155>
This commit is contained in:
Timur Kristóf
Marge Bot
parent
7f189e3467
commit
896a55f47d
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@ -70,6 +70,7 @@ libradv_files = files(
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'radv_meta_resolve_cs.c',
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'radv_meta_resolve_fs.c',
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'radv_nir_apply_pipeline_layout.c',
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'radv_nir_lower_abi.c',
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'radv_nir_lower_ray_queries.c',
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'radv_nir_lower_ycbcr_textures.c',
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'radv_pass.c',
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@ -0,0 +1,218 @@
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/*
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* Copyright © 2022 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#include "nir.h"
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#include "nir_builder.h"
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#include "ac_nir.h"
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#include "radv_constants.h"
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#include "radv_private.h"
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#include "radv_shader.h"
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#include "radv_shader_args.h"
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typedef struct {
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enum chip_class chip_class;
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const struct radv_shader_args *args;
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const struct radv_shader_info *info;
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const struct radv_pipeline_key *pl_key;
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} lower_abi_state;
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static nir_ssa_def *
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load_ring(nir_builder *b, unsigned ring, lower_abi_state *s)
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{
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nir_ssa_def *ring_offsets = ac_nir_load_arg(b, &s->args->ac, s->args->ring_offsets);
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ring_offsets = nir_pack_64_2x32_split(b, nir_channel(b, ring_offsets, 0), nir_channel(b, ring_offsets, 1));
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return nir_load_smem_amd(b, 4, ring_offsets, nir_imm_int(b, ring * 16u), .align_mul = 4u);
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}
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static nir_ssa_def *
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nggc_bool_setting(nir_builder *b, unsigned mask, lower_abi_state *s)
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{
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nir_ssa_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->ngg_culling_settings);
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nir_ssa_def *x = nir_iand_imm(b, settings, mask);
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return nir_ine(b, x, nir_imm_int(b, 0));
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}
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static nir_ssa_def *
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lower_abi_instr(nir_builder *b, nir_instr *instr, void *state)
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{
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lower_abi_state *s = (lower_abi_state *) state;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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gl_shader_stage stage = b->shader->info.stage;
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_ring_tess_factors_amd:
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return load_ring(b, RING_HS_TESS_FACTOR, s);
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case nir_intrinsic_load_ring_tess_factors_offset_amd:
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return ac_nir_load_arg(b, &s->args->ac, s->args->ac.tcs_factor_offset);
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case nir_intrinsic_load_ring_tess_offchip_amd:
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return load_ring(b, RING_HS_TESS_OFFCHIP, s);
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case nir_intrinsic_load_ring_tess_offchip_offset_amd:
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return ac_nir_load_arg(b, &s->args->ac, s->args->ac.tess_offchip_offset);
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case nir_intrinsic_load_tcs_num_patches_amd:
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return nir_imm_int(b, s->info->num_tess_patches);
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case nir_intrinsic_load_ring_esgs_amd:
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return load_ring(b, stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS : RING_ESGS_VS, s);
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case nir_intrinsic_load_ring_es2gs_offset_amd:
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return ac_nir_load_arg(b, &s->args->ac, s->args->ac.es2gs_offset);
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case nir_intrinsic_load_tess_rel_patch_id_amd:
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if (stage == MESA_SHADER_TESS_CTRL) {
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return nir_extract_u8(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.tcs_rel_ids), nir_imm_int(b, 0));
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} else if (stage == MESA_SHADER_TESS_EVAL) {
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/* Setting an upper bound like this will actually make it possible
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* to optimize some multiplications (in address calculations) so that
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* constant additions can be added to the const offset in memory load instructions.
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*/
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nir_ssa_def *arg = ac_nir_load_arg(b, &s->args->ac, s->args->ac.tes_rel_patch_id);
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nir_intrinsic_instr *load_arg = nir_instr_as_intrinsic(arg->parent_instr);
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nir_intrinsic_set_arg_upper_bound_u32_amd(load_arg, 2048 / MAX2(b->shader->info.tess.tcs_vertices_out, 1));
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return arg;
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} else {
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unreachable("invalid tessellation shader stage");
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}
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case nir_intrinsic_load_patch_vertices_in:
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if (stage == MESA_SHADER_TESS_CTRL)
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return nir_imm_int(b, s->pl_key->tcs.tess_input_vertices);
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else if (stage == MESA_SHADER_TESS_EVAL)
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return nir_imm_int(b, b->shader->info.tess.tcs_vertices_out);
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else
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unreachable("invalid tessellation shader stage");
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case nir_intrinsic_load_gs_vertex_offset_amd:
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return ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_vtx_offset[nir_intrinsic_base(intrin)]);
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case nir_intrinsic_load_workgroup_num_input_vertices_amd:
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return nir_ubfe(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info),
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nir_imm_int(b, 12), nir_imm_int(b, 9));
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case nir_intrinsic_load_workgroup_num_input_primitives_amd:
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return nir_ubfe(b, ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_tg_info),
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nir_imm_int(b, 22), nir_imm_int(b, 9));
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case nir_intrinsic_load_packed_passthrough_primitive_amd:
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/* NGG passthrough mode: the HW already packs the primitive export value to a single register. */
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return ac_nir_load_arg(b, &s->args->ac, s->args->ac.gs_vtx_offset[0]);
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case nir_intrinsic_load_shader_query_enabled_amd:
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return nir_ieq_imm(b, ac_nir_load_arg(b, &s->args->ac, s->args->ngg_gs_state), 1);
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case nir_intrinsic_load_cull_any_enabled_amd:
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return nggc_bool_setting(b, radv_nggc_front_face | radv_nggc_back_face | radv_nggc_small_primitives, s);
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case nir_intrinsic_load_cull_front_face_enabled_amd:
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return nggc_bool_setting(b, radv_nggc_front_face, s);
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case nir_intrinsic_load_cull_back_face_enabled_amd:
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return nggc_bool_setting(b, radv_nggc_back_face, s);
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case nir_intrinsic_load_cull_ccw_amd:
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return nggc_bool_setting(b, radv_nggc_face_is_ccw, s);
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case nir_intrinsic_load_cull_small_primitives_enabled_amd:
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return nggc_bool_setting(b, radv_nggc_small_primitives, s);
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case nir_intrinsic_load_cull_small_prim_precision_amd: {
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/* To save space, only the exponent is stored in the high 8 bits.
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* We calculate the precision from those 8 bits:
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* exponent = nggc_settings >> 24
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* precision = 1.0 * 2 ^ exponent
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*/
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nir_ssa_def *settings = ac_nir_load_arg(b, &s->args->ac, s->args->ngg_culling_settings);
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nir_ssa_def *exponent = nir_ishr_imm(b, settings, 24u);
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return nir_ldexp(b, nir_imm_float(b, 1.0f), exponent);
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}
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case nir_intrinsic_load_viewport_x_scale:
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return ac_nir_load_arg(b, &s->args->ac, s->args->ngg_viewport_scale[0]);
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case nir_intrinsic_load_viewport_x_offset:
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return ac_nir_load_arg(b, &s->args->ac, s->args->ngg_viewport_translate[0]);
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case nir_intrinsic_load_viewport_y_scale:
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return ac_nir_load_arg(b, &s->args->ac, s->args->ngg_viewport_scale[1]);
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case nir_intrinsic_load_viewport_y_offset:
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return ac_nir_load_arg(b, &s->args->ac, s->args->ngg_viewport_translate[1]);
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default:
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unreachable("invalid NIR RADV ABI intrinsic.");
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}
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}
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static bool
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filter_abi_instr(const nir_instr *instr,
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UNUSED const void *state)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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return intrin->intrinsic == nir_intrinsic_load_ring_tess_factors_amd ||
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intrin->intrinsic == nir_intrinsic_load_ring_tess_factors_offset_amd ||
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intrin->intrinsic == nir_intrinsic_load_ring_tess_offchip_amd ||
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intrin->intrinsic == nir_intrinsic_load_ring_tess_offchip_offset_amd ||
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intrin->intrinsic == nir_intrinsic_load_patch_vertices_in ||
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intrin->intrinsic == nir_intrinsic_load_tcs_num_patches_amd ||
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intrin->intrinsic == nir_intrinsic_load_ring_esgs_amd ||
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intrin->intrinsic == nir_intrinsic_load_ring_es2gs_offset_amd ||
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intrin->intrinsic == nir_intrinsic_load_tess_rel_patch_id_amd ||
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intrin->intrinsic == nir_intrinsic_load_gs_vertex_offset_amd ||
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intrin->intrinsic == nir_intrinsic_load_workgroup_num_input_vertices_amd ||
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intrin->intrinsic == nir_intrinsic_load_workgroup_num_input_primitives_amd ||
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intrin->intrinsic == nir_intrinsic_load_packed_passthrough_primitive_amd ||
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intrin->intrinsic == nir_intrinsic_load_shader_query_enabled_amd ||
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intrin->intrinsic == nir_intrinsic_load_cull_any_enabled_amd ||
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intrin->intrinsic == nir_intrinsic_load_cull_front_face_enabled_amd ||
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intrin->intrinsic == nir_intrinsic_load_cull_back_face_enabled_amd ||
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intrin->intrinsic == nir_intrinsic_load_cull_ccw_amd ||
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intrin->intrinsic == nir_intrinsic_load_cull_small_primitives_enabled_amd ||
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intrin->intrinsic == nir_intrinsic_load_cull_small_prim_precision_amd ||
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intrin->intrinsic == nir_intrinsic_load_viewport_x_scale ||
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intrin->intrinsic == nir_intrinsic_load_viewport_x_offset ||
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intrin->intrinsic == nir_intrinsic_load_viewport_y_scale ||
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intrin->intrinsic == nir_intrinsic_load_viewport_y_offset;
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}
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void
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radv_nir_lower_abi(nir_shader *shader,
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enum chip_class chip_class,
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const struct radv_shader_info *info,
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const struct radv_shader_args *args,
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const struct radv_pipeline_key *pl_key)
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{
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lower_abi_state state = {
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.chip_class = chip_class,
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.info = info,
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.args = args,
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.pl_key = pl_key,
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};
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nir_shader_lower_instructions(shader, filter_abi_instr, lower_abi_instr, &state);
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}
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@ -4488,7 +4488,8 @@ radv_create_shaders(struct radv_pipeline *pipeline, struct radv_pipeline_layout
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radv_lower_ngg(device, &stages[i], pipeline_key);
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ac_nir_lower_global_access(stages[i].nir);
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radv_nir_lower_abi(stages[i].nir, device->physical_device->rad_info.chip_class,
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&stages[i].info, &stages[i].args, pipeline_key);
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radv_optimize_nir_algebraic(stages[i].nir, io_to_mem || lowered_ngg || i == MESA_SHADER_COMPUTE);
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if (stages[i].nir->info.bit_sizes_int & (8 | 16)) {
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@ -46,6 +46,7 @@ struct radv_device;
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struct radv_pipeline;
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struct radv_pipeline_cache;
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struct radv_pipeline_key;
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struct radv_shader_args;
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struct radv_vs_input_state;
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struct radv_shader_args;
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@ -519,6 +520,11 @@ nir_shader *radv_shader_compile_to_nir(struct radv_device *device,
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const struct radv_pipeline_stage *stage,
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const struct radv_pipeline_key *key);
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void radv_nir_lower_abi(nir_shader *shader, enum chip_class chip_class,
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const struct radv_shader_info *info,
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const struct radv_shader_args *args,
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const struct radv_pipeline_key *pl_key);
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void radv_init_shader_arenas(struct radv_device *device);
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void radv_destroy_shader_arenas(struct radv_device *device);
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