Commit Graph

163274 Commits

Author SHA1 Message Date
Frank Binns c580172701 CODEOWNERS: add MTCoster as an Imagination maintainer
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19845>
2022-11-22 09:24:43 +00:00
Yonggang Luo af50f6a490 util: Remove EXPLICIT_CONVERSION macro and use c++11 explicit directly
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19895>
2022-11-22 15:42:15 +08:00
Yonggang Luo 8c32686116 tree-wide: Fixes multi-line macro width after replace to __func__
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
2022-11-22 06:53:47 +00:00
Yonggang Luo c24e2428ad gallium: __FUNCTION__ now never be used, remove it
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
2022-11-22 06:53:47 +00:00
Yonggang Luo 6f4dc9b807 gallium: Replace the usage of __FUNCTION__ with __func__ in all gallium code
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
2022-11-22 06:53:47 +00:00
Yonggang Luo 40a9fc57aa tree-wide: Use __func__ instead of __FUNCTION__ in non-gallium code
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Acked-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19861>
2022-11-22 06:53:46 +00:00
Danylo Piliaiev 703d85485f meson: do not use source_root() when possible
source_root() function is deprecated in Meson version 0.56.0 because
it returns the source root of the parent project if called from a
subproject.

Why would anyone need Mesa as a meson subproject?
It would be used as subproject in a project generated by command buffer
"decompiler" for Freedreno.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19901>
2022-11-22 06:11:07 +00:00
Qiang Yu 74ad255c8c ac/nir/cull: fix culling for lines
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19868>
2022-11-22 05:46:06 +00:00
Qiang Yu d18a28ae87 ac/nir/ngg,radv: use intrinsic base for instance_rate_inputs check
radeonsi use packed location base while radv use un-packed location.
So we adjust instance_rate_inputs in each driver to hide the difference.
Note the attribute slot number is less than 16, so we can shift
instance_rate_inputs in radv by VERT_ATTRIB_GENERIC0 which is 16.

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19868>
2022-11-22 05:46:06 +00:00
Jason Ekstrand 9cec1ed51d vulkan: Add a dummy vk_common_CmdSetColorBlendAdvancedEXT()
The entrypoint needs to exist but we don't need to do anything with it.

Fixes: 13c422e1b2 ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
2022-11-22 05:09:17 +00:00
Jason Ekstrand 182aa9eb15 vulkan: Add a common implementation of CmdSetSampleLocationsEnableEXT
Fixes: 13c422e1b2 ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
2022-11-22 05:09:17 +00:00
Jason Ekstrand b172fd62f5 vulkan: Add state for extraPrimitiveOverestimationSize
Fixes: 13c422e1b2 ("anv: toggle on EXT_extended_dynamic_state3")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19817>
2022-11-22 05:09:17 +00:00
Karol Herbst fa99fc3491 rusticl: advertise conformance on 12th Intel iGPUs
Submission can be found here:
https://www.khronos.org/conformance/adopters/conformant-products/opencl#submission_405

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Hard-reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Acked-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19699>
2022-11-22 04:42:19 +00:00
Lionel Landwerlin 507a86e131 anv: ensure CPS is initialized when KHR_fragment_shading_rate is disabled
We need to set CPS_MODE_NONE when no per coarse pixel dispatch.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 231651fd89 ("anv: implement VK_KHR_fragment_shading_rate")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19867>
2022-11-22 03:53:57 +00:00
Lionel Landwerlin 62f12c2dad anv: fix 3d state initialization
We missed a couple of restriction leading to inconsistent 3d pipeline
state. It is mostly noticeable when doing a multiple sample dispatch
as the verify first 3d operation.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7531
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19867>
2022-11-22 03:53:57 +00:00
Ian Romanick f75c83c4aa nir/loop_analyze: Fix get_iteration for nir_op_fneu
Consider the loop:

    float i = 0.0;
    while (true) {
       if (i != 0.0)
          break;

       i = i + 1.0;
    }

This loop clearly executes exactly one time.

Some trickery is necessary to handle cases where the initial loop value
is very large and the increment is, by comparison, very small.  From the
fenu_once test case,

    float i = -604462909807314587353088.0;
    while (true) {
       if (i != -604462909807314587353088.0)
          break;

       i = i + 36028797018963968.0;
    }

This loop should also execute exactly once, but this is much more
challenging to calculate due to precision issues.

Going towards smaller magnitude (i.e., adding a small positive value to
a large negative value) requires a smaller delta to make a difference
than going towards a larger magnitude. For this reason,
-604462909807314587353088.0 + 36028797018963968.0 !=
-604462909807314587353088.0, but -604462909807314587353088.0 +
-36028797018963968.0 == -604462909807314587353088.0. Math class is
tough.

No changes in shader-db or fossil-db.

v2: Fix major bug in checking result of the eval_const_binop(nir_op_feq,
...) discovered while developing fneu_once_easy unit test. Fix a typo in
the comment just above that. Add fneu_once_easy test.

v3: Skip the iteration count adjustment tests for nir_op_fenu and
nir_op_ine. Since the iteration count is either 1 or unknown, all this
function can do is add numerical error. Add fenu_once tests.

v4: Change the initial value in the fneu_once test from large positive
to large negative. Change check in get_iteration from nir_op_fsub to
nir_op_fadd. Both changes from discussion with M Henning. Also add some
more explanation in fneu_once.

v5: Rename test cases.

Fixes: 6772a17acc ("nir: Add a loop analysis pass")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19732>
2022-11-22 03:18:54 +00:00
Ian Romanick d9f014401b nir/loop_analyze: Fix get_iteration for nir_op_ine
I discovered this problem because adding an algebraic transformation to
convert some uge and ult to ieq or ine caused a couple loops to stop
unrolling. Consider the loop:

    uint i = 0;
    while (true) {
       if (i >= 1)
          break;

       i++;
    }

This loop clearly executes exactly one time. Note that uge(x, 1) is
equivalent to ine(x, 0). Changing the condition to 'if (i != 0)' will
also execute exactly one time.

In the added test cases, uge_once correctly get an exact loop trip count
of 1. Without the changes to nir_loop_analyze.c, the ine_once case
detects a maximum loop trip count of zero and does not get an exact loop
trip count.

No changes in shader-db or fossil-db.

v2: Move nir_op_fneu changes to a separate commit.

v3: Rename test cases.

Fixes: 6772a17acc ("nir: Add a loop analysis pass")
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19732>
2022-11-22 03:18:54 +00:00
Ian Romanick dbad33da16 nir/loop_analyze: Add basic unit test framework
This test comes from a comment in the loop analysis code.

The ine_zero test checks that zero iteration loops involving ine are
correctly identified.

v2: Add ine_zero test. Suggested by Tim.

v3: Rename test cases.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19732>
2022-11-22 03:18:54 +00:00
Karol Herbst b51eb98cf6 rusticl/device: put space at the end of CL_DEVICE_VERSION
Apparently some software relies on that and the spec kind of says it's
there.

Fixes: 20c90fed5a ("rusticl: added")
Reported-by: sobkas
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19872>
2022-11-22 03:10:33 +00:00
Adam Jackson 3732c7aa63 egl: Fix uninitialized variable warning
Fedora's gcc 12.2.1 says:

    ../src/egl/main/eglapi.c: In function ‘eglDupNativeFenceFDANDROID’:
    ../src/egl/main/eglapi.c:2268:11: warning: ‘ret’ may be used uninitialized [-Wmaybe-uninitialized]
     2268 |    EGLint ret;

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19913>
2022-11-22 01:54:51 +00:00
Pavel Ondračka 90df5c3b5f r300: don't reuse destination registers when lowering
Regalloc can sort it out later. No significant change is shader-db, the
one instruction reduction is likely because some optimize pass can
actually work better when we are closer to ssa-like form.

RV530:
total instructions in shared programs: 133718 -> 133717 (<.01%)
instructions in affected programs: 47 -> 46 (-2.13%)
helped: 1
HURT: 0

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19853>
2022-11-22 01:45:19 +00:00
Pavel Ondračka b33845cf24 r300: simplify rc_find_free_temporary
Back when we had a stupid register allocator we did a lot of tricks to
optimize the register usage. The old version of rc_find_free_temporary
did a full program search each time it was called to find out what
registers and channels are actually used and than used that info to give
us the first free register to use.

Now that we have a proper register allocator both for vertex and
fragment shaders, this is no longer needed. Just scan the program when
called for the first time to find the first unused temporary index and
than increment by one everytime. Regalloc can sort it out later.

No change in shader-db confirms this assumption is sound.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19853>
2022-11-22 01:45:19 +00:00
Rob Clark ded82cf4bd freedreno/a6xx: Remove unneeded MSAA clear fallback
This was added in commit 911ce374ca ("freedreno/a6xx: Fix MSAA clear"),
but the only case that can't handle fast-clear is sysmem blitter clear
path.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19884>
2022-11-21 23:38:56 +00:00
Rob Clark 87563e64c9 freedreno/a6xx: Use fallback path for MSAA clear_texture()
The trick for emulating MSAA clear by adjusting blit coords tends to
fall over with tiled/ubwc, so just use the fallback path instead.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19884>
2022-11-21 23:38:56 +00:00
David Heidelberg 042f006a43 .gitignore: add VSCode and VSCodium
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19902>
2022-11-21 23:09:30 +00:00
David Heidelberg c415d8f08b ci: ci_run_n_monitor.py: fail when job is not found
Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19902>
2022-11-21 23:09:30 +00:00
Emma Anholt 50c7abefa6 ci/freedreno: add some missing a630 flakes.
Two from the GL 4.5 update, one that's been around longer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19905>
2022-11-21 22:45:46 +00:00
Emma Anholt be64e0cdc0 ci/turnip+zink: Generalize the 16-bit copy_image fails.
We just had another fail of the non_compressed texture2d_array group, and
we've got enough of a pattern here.

I left in the specific cases that had some debug info, though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19905>
2022-11-21 22:45:46 +00:00
Alyssa Rosenzweig 70f40ea4d3 asahi: Wire up all BCn formats
We have these native. Passes the relevant piglits. Large reduction in memory
usage on Xonotic on higher settings (8x less memory per texture), which allows
Xonotic to run at high settings without OOMing.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tested-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19903>
2022-11-21 22:33:43 +00:00
Gert Wollny e496d24cb2 virgl: don't a use staging when a resources created with the shared flag
There seems to be a problem with running firefox by using Xwayland that
results in a shared resources being not always tagged as using staging.

As a result one process tries to map the resource that was allocated as
one that uses staging without actually using the staging resource, and
hence the mapped range only accounts for the small region that we have
to allocated because a zero-allocation doesn't work, but the application
mapping the resource assumes that a properly sized range is mapped, and
consequently this results in invalid memory access.

To work around this issue disable creating staging for resources that
are created by using shared binding. It is not clear to me whether this
is the best fix, but it seems to quell the issue.

Fixes: c9d99b7eec
    virgl: Fix texture transfers by using a staging resource

Related: https://gitlab.freedesktop.org/virgl/virglrenderer/-/issues/291
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19655>
2022-11-21 21:37:50 +00:00
Sajeesh Sidharthan c22fbeb72a gallium/drivers: copy only the actual number of slice parameters
currently max number of slice(tile) parameters are copied for av1.
copy only actual number of slice parameters

Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19878>
2022-11-21 20:14:21 +00:00
Rhys Perry 368be87255 nir/algebraic: shrink 64-bit bitwise operations with 0/-1 constant half
fossil-db (navi21):
Totals from 457 (0.34% of 135636) affected shaders:
Instrs: 259349 -> 250383 (-3.46%)
CodeSize: 1411976 -> 1369136 (-3.03%)
Latency: 2175961 -> 2148158 (-1.28%)
InvThroughput: 502206 -> 490244 (-2.38%)
Copies: 15238 -> 15232 (-0.04%); split: -0.07%, +0.03%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19748>
2022-11-21 17:34:46 +00:00
Konstantin Seurer 8133d5551d radv/rt: Return the correct result for requested deferral
We do not implement deferred host operations so we will return
VK_OPERATION_NOT_DEFERRED_KHR for now.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19882>
2022-11-21 16:59:41 +00:00
Sajeesh Sidharthan 8d8caa44bd frontends/va: remove unused slice_param_idx variable
slice_param_idx was added to handle multiple slice params.
it's not used anymore.

Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19877>
2022-11-21 16:45:42 +00:00
Rhys Perry 3061bc792d aco: ensure MRT0 is written with dual source blending
Fixes crucible test func.shader.dualsrc_mrt0_undef on polaris10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19806>
2022-11-21 15:01:56 +00:00
Rhys Perry ea0ae17fc4 radv: disable MRT compaction with dual-source blending
Fixes crucible tests func.shader.dualsrc_mrt0_undef on navi21 and
func.shader.dualsrc_mrt1_undef on polaris10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19806>
2022-11-21 15:01:56 +00:00
José Roberto de Souza 68652dca0c iris: Fix iris_bo_alloc() flags call argument
binder_realloc() -> iris_bo_alloc() is setting 4096 as flags parameter.
Up to now this is harmeless as there is no BO_ALLOC flag that uses
bit 12 but is better to avoid any future issues.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19898>
2022-11-21 14:35:55 +00:00
Danylo Piliaiev f1305d49d9 tu: Implement VK_EXT_post_depth_coverage
Passes:
 dEQP-VK.pipeline.monolithic.multisample.sample_mask_with_depth_test.*
 KHR-GL45.post_depth_coverage_tests.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19682>
2022-11-21 14:11:05 +00:00
Pavel Ondračka 1ec172646c r300: more informative too many ALU instructions error
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
2022-11-21 13:54:39 +00:00
Pavel Ondračka b70543a955 r300: delete backend branch emulation
We now depend on NIR doing the right thing. It was not able to
handle the few cases where NIR failed anyway (and even if it did,
such complex cases would hit the instruction limit later).

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
2022-11-21 13:54:39 +00:00
Pavel Ondračka 2fe73e3bcb r300: abort shader compilation early on loops and branches
R300/R400 GPUs can't do it in hardware and all the lowering should have
happened in NIR already, there is no point in wasting CPU time, just to
abort later when emitting.

Reduces CPU time for dEQP run by ~25% for RV370. The wallclock time is
now just slighly above 1 minute at 10 threads, mostly determined by the
long-running dEQP-GLES2.functional.flush_finish.* tests.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
2022-11-21 13:54:39 +00:00
Bas Nieuwenhuizen 8d37ab6bfa radv: Fix custom build id with C90 compilation.
Seems some build configurations have problems with VLAs still.

Fixes: 97641e5c94 ("radv: Add ability to override the build id for the cache.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19869>
2022-11-21 12:57:41 +00:00
Maíra Canal d34f3a1db5 v3dv: fix multiple typos
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19538>
2022-11-21 11:31:29 +00:00
Gert Wollny 67ffe25fd9 r600: Fix lower-to-scalar on TTN path
We must limit what alu ops are scalazized, and since we now
run finalize_nir we also have to make sure not to try to
scalarize backend specific instructions that are introduced
there.

While we touch the code, also remove the vectorization, it is
no longer helping.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7747

Fixes: a81c50a2 (r600/sfn: implement finalize_nir)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19892>
2022-11-21 10:53:44 +00:00
Gert Wollny a69eafc422 r600: reference glsl type system during translation
VL doesn't initialize the type systen, but creates shaders in TGSI.
When these are translated to NIR and then compiled in the driver
we need to have a reference to the glsl type system.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7453

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19883>
2022-11-21 10:43:51 +00:00
Daniil Tatianin 089ae08ab1 intel_batch_decoder: disasm shaders when decoding states besides VS
Previously only 'decode_vs_state' would dump the referenced shader,
which meant we completely ignored every other shader when decoding
the '3DSTATE_PIPELINED_POINTERS' command.

Move the program disassembly logic from 'decode_vs_state' into a
common 'disasm_program_from_group' helper and call it from every
other decode_*_state function, too.

Signed-off-by: Daniil Tatianin <99danilt@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19880>
2022-11-21 10:00:32 +00:00
Jose Maria Casanova Crespo c82775e3c7 v3d: Minor fixes on sand8 blit based on sand30 modifications
* load_uniform for sand8_stride is uint32 instead of int32 and its range
  is 4 instead of 1 as it is counted in bytes.
* Now we save and restore constant buffer 1 properly for the ubo used
  in the blit. We need to take into account that in V3D the first UBO
  with index 0 is stored on constant buffer 1, because gallium uses
  internally contant buffer 0 (See for reference commit c8212731e7)
* Removed not needed return.
* Added shader information about uniforms, ubos, inputs and outputs.
* Fixed typos in the comments.

Fixes: 95c4f0f910 "v3d: Enables DRM_FORMAT_MOD_BROADCOM_SAND128 support"
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
2022-11-21 09:08:44 +00:00
Jose Maria Casanova Crespo e97b20f3ca v3d: Also expose DRM_FORMAT_MOD_BROADCOM_SAND128 with PIPE_FORMAT_P030
Now we can display h265-10bit decoded frames formats on Raspberry Pi 4
devices on GL/ES applications.

v2: Don't expose LINEAR or UIF formats for P030 format.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
2022-11-21 09:08:44 +00:00
Jose Maria Casanova Crespo 653cf8c8d2 v3d: Blit for P030 format with BROADCOM_SAND128 modifier to P010 UIF
Implements the support to blit SAND modifier with columns 128-bytes-wide
support for P030 format to P010 with UIF layout. This allows sampling
from H265 10-bit frames exported by the video decoder on the Raspberry
Pi 4 devices.

When a DRM_FORMAT_MOD_BROADCOM_SAND128 is enabled with an imported P030
texture. The sand30 blit converts the Luma and Chroma planes to
a tiled P010 format that can be sampled using gallium YUV lowerings
without the interleaved 128-bytes-wide-columns.

This patch follows a similar approach to SAND8 blit but extracting luma
and chroma components from the DRM_FORMAT_P030 format. P030 is a two
plane YCbCr420 format where 3 10 bit components with 2 padding bits are
packed in 4 bytes.

index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0
                       [2:10:10:10:2:10:10:10] little endian

After the sand30_blit is done, the shadow texture is an UIF tiled texture
with an R16_UNORM format for luma and R16G16_UNORM for chroma.

To reduce the number of texture-fetch operations during the blit, we
read pairs of 32-bit dwords. They include 6 10-bit unorm components.
And then we write 4 UNORM16 components from an uvec4 because our render
targets do not support writing to UNORM16 formats.

As sampling will be done using 16bpp (luma) and 32bpp (chroma), the
sand30_blit writes consider the different microtile layouts of UIF
format between 64, 32 and 16 bpp.

v2: Fixes save and recovery of constant buffers (Iago)
    Typo corrections. (Iago)
    Removed not needed return. (Iago)
    Added shader information about uniforms, ubos, inputs and outputs.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
2022-11-21 09:08:44 +00:00
Jose Maria Casanova Crespo 4ea4147935 gallium/dri: Add P030 format
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
2022-11-21 09:08:44 +00:00