mirrors
/
mesa
mirror of https://gitlab.freedesktop.org/mesa/mesa
1
0
Fork 0
Code Issues 9 Packages Projects Releases Wiki Activity

tu: Implement VK_EXT_post_depth_coverage 

Passes:
 dEQP-VK.pipeline.monolithic.multisample.sample_mask_with_depth_test.*
 KHR-GL45.post_depth_coverage_tests.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19682>
This commit is contained in:
Danylo Piliaiev 2022-11-11 16:40:53 +01:00 committed by Marge Bot
parent 1ec172646c
commit f1305d49d9
6 changed files with 10 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/freedreno/ir3/ir3_compiler_nir.c
View File

@ -5004,6 +5004,10 @@ ir3_compile_shader_nir(struct ir3_compiler *compiler,
!ctx->s->info.fs.early_fragment_tests)
ctx->so->no_earlyz |= ctx->s->info.writes_memory;
if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
ctx->s->info.fs.post_depth_coverage)
so->post_depth_coverage = true;
out:
if (ret) {
if (so->ir)

2
src/freedreno/ir3/ir3_shader.h
View File

@ -694,6 +694,8 @@ struct ir3_shader_variant {
bool per_samp;
bool post_depth_coverage;
/* Are we using split or merged register file? */
bool mergedregs;

2
src/freedreno/registers/adreno/a6xx.xml
View File

@ -1976,7 +1976,7 @@ to upconvert to 32b float internally?
<reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
<!-- enable bits for various FS sysvalue regs: -->
<bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
<bitfield name="UNK1" pos="1" type="boolean"/>
<bitfield name="POSTDEPTHCOVERAGE" pos="1" type="boolean"/>
<bitfield name="FACENESS" pos="2" type="boolean"/>
<bitfield name="SAMPLEID" pos="3" type="boolean"/>
<bitfield name="FRAGCOORDSAMPLEMODE" low="4" high="5" type="a6xx_fragcoord_sample_mode"/>

1
src/freedreno/vulkan/tu_device.c
View File

@ -242,6 +242,7 @@ get_device_extensions(const struct tu_physical_device *device,
.EXT_mutable_descriptor_type = true,
.KHR_pipeline_library = true,
.EXT_graphics_pipeline_library = true,
.EXT_post_depth_coverage = true,
};
}

1
src/freedreno/vulkan/tu_pipeline.c
View File

@ -1578,6 +1578,7 @@ tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs)
CONDREG(smask_in_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEMASK) |
CONDREG(samp_id_regid, A6XX_RB_RENDER_CONTROL1_SAMPLEID) |
CONDREG(ij_regid[IJ_PERSP_CENTER_RHW], A6XX_RB_RENDER_CONTROL1_CENTERRHW) |
COND(fs->post_depth_coverage, A6XX_RB_RENDER_CONTROL1_POSTDEPTHCOVERAGE) |
COND(fs->frag_face, A6XX_RB_RENDER_CONTROL1_FACENESS));
tu_cs_emit_pkt4(cs, REG_A6XX_RB_SAMPLE_CNTL, 1);

1
src/freedreno/vulkan/tu_shader.c
View File

@ -76,6 +76,7 @@ tu_spirv_to_nir(struct tu_device *dev,
.subgroup_shuffle = true,
.subgroup_arithmetic = true,
.physical_storage_buffer_address = true,
.post_depth_coverage = true,
},
};