Commit Graph

443 Commits

Author SHA1 Message Date
Alyssa Rosenzweig 7a4e0a4d35 agx: Implement texture offsets and comparators
Texture offsets and shadow comparison values get grouped into a vector
passed by register. Comparison values are provided as-is (fp32). Texture
offsets are packed into nibbles, but we can do this on the CPU, as
nonconstant offsets are forbidden in GLSL at least. They're also
forbidden in Vulkan/SPIR-V without ImageGatherExtended/
shaderImageGatherExtended. I'm happy kicking the NIR lowering can down
the line, this commit is complicated enough already.

Passes dEQP-GLES3.functional.shaders.texture_functions.texture.* and
dEQP-GLES3.functional.shaders.texture_functions.textureoffset.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
2022-09-13 16:04:29 +00:00
Alyssa Rosenzweig 4f85a7be8c agx: Make p_combine take a dynamic src count
For larger vectors.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
2022-09-13 16:04:28 +00:00
Alyssa Rosenzweig ef31dceee8 agx,asahi: Implement nir_intrinsic_load_texture_base_agx
Save off what we pass to BIND_TEXTURE.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18525>
2022-09-13 16:04:28 +00:00
Alyssa Rosenzweig a7ddb8ebf7 asahi: Handle Stream Link VDM commands
Jumps in the command streams, allowing us to chain ("link") command
buffers. Naming is from PowerVR, which contains an identical command.
PowerVR's has conditional jumps and function call support, it's likely
that AGX inherited this too but I haven't tested that. (Those might be
useful for conditional rendering and secondary command buffers
respectively?)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig 6f5c8d0e24 asahi: Express VDM commands according to PowerVR
Piles of unknown bits go away, as we find they're either "field present"
bits or block types. And yep, the block type enum lines up between AGX
and RGX.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig 80d8273705 asahi: Annotate VDM/CDM commands as per PVR
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig 22f6efde02 asahi: Dirty track everything
Now that we have fine grained state emit code, let's use it to reduce
driver overhead. Dirty tracking is delicate: while this seems to work,
I've also added an ASAHI_MESA_DEBUG=dirty option in debug builds
to disable the optimizations here for future debug.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig 942bda7f2d asahi: Match PPP data structures with PowerVR
Looking at PowerVR's PPP definitions in tree in Mesa
(src/imagination/csbgen/), we find that AGX's "tagged" data structures
are actually sequences of state items prefixed by a header specifying
which state follows. Rather than hardcoding the sequences in which Apple's
driver chooses to bundle state, we need the XML to be flexible enough to
encode or decode any valid combination of state. That means reworking
the XML. While doing so, we find a number of fields that are identical
between RGX and AGX, and fix the names while at it (for example, the W
Clamp floating point).

Names are from the PowerVR code in Mesa where sensible.

Once we've reworked the XML, we need to rework the decoder.  Instead of
reading tags and printing the combined state packets, the decoder now
must unpack the header and print the individual state items specified by
the header, with slightly more complicated bounds checking.

Finally, state emission in the driver becomes much more flexible. To
prove the flexibility actually works, we now emit all PPP state (except for
viewport and scissor state) as a single PPP update. This works. After
this we can move onto more interesting arrangements of state for lower
driver overhead.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig baadc1ec13 asahi: Don't use lower_wpos_pntc
Instead we can flip point coords with the object type. That means fewer
instructions without shader variants. Thanks, PowerVR ^_^

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig f7ef5eefdd asahi: Identify object type field via PowerVR
src/imagination/csbgen/rogue_ppp.xml STATE_ISPA bits 28. Looks like that
got split into two structs in AGX (with info duplicated?) but yeah I
have a lot to work with here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig d93878f77a asahi: Split RASTERIZER into constituent words
As done in the PowerVR driver.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-06 21:01:28 +00:00
Alyssa Rosenzweig 02babc834a asahi: Identify stencil test enable
There are a pair of flags controlling the stencil test. One enables
stencil testing in general, the other enables two-sided stencil. Compare
the identical "twosided" flag in src/imagination/csbgen/rogue_ppp.xml's
STATE_ISPCTL structure, at the samebit offset even. Evidently this word of
the "Rasterizer" is, in fact, a derivative of STATE_ISPCTL.

Fixes

   dEQP-GLES2.functional.fragment_ops.depth_stencil.*
   dEQP-GLES2.functional.fragment_ops.interaction.basic_shader.*
   dEQP-GLES2.functional.fragment_ops.random.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig b891d60efa asahi: Fix depth/stencil buffers
There are a bunch of bits we need to set right to get depth/stencil
loads/stores working, including with independent settings for each. The
kernel "helps" us here.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 66f1164976 asahi: Add 1D and 1D Array enums
To finish out the enum.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 2bdb8ba3ce asahi: Correct SET_SHADER_EXTENDED disambig bit
This is still a guess, but a considerably firmer one as it now corrects
handles the clear pipelines emitted by Metal as well as the regular
vertex/fragment shader, and gets rid of the preshader special cases
seen there. Fixes decode of clear pipeline's preshaders.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 210f4aff1e asahi: Identify and use first level field of texture
As we recently discovered, the layout of level L of a mipmapped 2D image
of size WxH is /not/ the same as the layout of a non-mipmapped 2D image
of size minify(W, L) x minify(H, L). The difference occurs due to
subtleties of the "power of two" miptrees which can force a level to use
a larger tile size than it would have required at root level. To handle
this quirk correctly, the driver must not implement texture views with
address arithmetic -- it must supply instead the base width/height of a
texture and use first/last level fields on the texture descriptor to map
it. Similar issues occur when writing a particular level of a mipmapped
texture, which was handled correctly in the colour case but not the Z/S
case.

Fixes

   dEQP-GLES2.functional.texture.mipmap.cube.generate.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 1d72d3feb6 asahi: Fix "stride" for tiled textures
It doesn't exist, but there's a count of mip levels for writeable image
descs. Setting that appropriately matters at high mip levels.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 4442be1155 asahi: Fix nonmipmapped array textures
pot_level can be greater than the number of levels actually included --
don't overallocate. Fix the issue and add a representative unit test.
Fixes:

   dEQP-GLES2.functional.texture.size.cube.512x512_rgb888

Fixes: 6ff75da8aa ("ail: Introduce image layout module")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig a41d732784 asahi: Fix depth for cube maps
For cube maps, depth=1 in the hardware (but 6 in Gallium). Likewise for
cube map arrays, depth=n in the hardware (but 6n in Gallium). We need to
divide to compensate. This will be relevant for cube map arrays in the
future -- add the dimension XML for cube map arrays too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig e66a901bc8 asahi: Relax assert in decoder
Seen == 0x8 with >4 render targets.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 9542f95864 asahi: Trim garbage at end of set shader
Unfortunately the actual size of this data structure is unclear.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig fb7860ed24 asahi: Handle empty fragment shaders
When an empty fragment shader is used with Metal, the stop command is
still included but this special bit is set, suppressing tilebuffer
access. Failing to do so but using empty shaders for u_blitter depth
clears causes Glitch Lina:

   https://twitter.com/LinaAsahi/status/1537869064793575424

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 968bbca578 asahi: Note some more unknowns in the XML
Lot of r/e waiting here...

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 47831969c8 asahi: Split up unk 2b
Seems to be flags.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 5f57fe0bc9 asahi: Fix Indexed Draw command
Add the missing stub in the decoder for it, so we can decode indexed
draws instead of reading back garbage, and fill in some known unknowns
in the structure.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 10c9aceadf agx: Plumb through nir_op_txf
nir_op_txf maps to AGX's texture_load, which is encoded like
texture_sample. The one outstanding question with this commit is the
rules for the sample required ... in NIR and APIs (including Metal), txf
is samplerless, but the AGX instruction consumes a sampler. Hopefully
any sampler will do, though?

Passes dEQP-GLES3.functional.shaders.texture_functions.texelfetch.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 44d79d39b6 agx: Defeature indirect vbufs
vb_mask can include garbage vbufs, we can't rely on it. This will
prevent a regression when switching to u_blitter based clears. This is
also simpler and shrinks the VS shader key so all in all a good thing.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 0fccd564b6 agx: Don't hardcode uniform enums
Let the compiler number them for us, the numbers are meaningless.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 18bb64fd3a agx: Add more unit tests for float copyprop
Would have caught the bug fixed by the previous commit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 095415cdf7 agx: Fix float copyprop of neg(neg) case
They should cancel each other. Fixes:

   dEQP-GLES2.functional.shaders.random.basic_expression.combined.0

Fixes: 28801b4849 ("agx: Add forward optimizing pass for fmov")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 9645e46a53 agx: Fix tib access in internal shaders
The only case where tilebuffer access can be specially optimized is the
st_tile used in internal clear (or reload) shaders. However, other
shaders (like those used with u_blitter) may have nir->info.internal
set, so we can't key off that. Instead, add a special key for this
optimization to ensure correctness with other internal shaders.

Fixes flaky tests in dEQP-GLES2.functional.color_clear.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-04 18:05:31 +00:00
Alyssa Rosenzweig 65c00ba7cb ail: Add unit tests for miptree layouts
The equations for calculating miptree offsets are complicated,
nonobvious, and full of subtle footguns. Worse, the driver doesn't
control the offsets -- it must simply agree with the offsets
implicitly calculated in the hardware. The CTS doesn't adequately
exercise all the corner cases. Make sure we have unit tests that do.

The tests themselves are generated by instrumenting agxdecode to scan
GPU memory after uploading test patterns in a variety of layout with a
Metal application.

Thank you to Asahi Lina and Dougall Johnson for the reverse-engineering
that led to this. The tests selected here are a subset of those used for
the reverse-engineering. The full set may be found in Lina's tilecalc
repo:

   https://github.com/asahilina/tilecalc

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig 4ed9843a26 asahi: Advertise ASTC formats
Now that we have layout and tiling code that can handle block-compressed
formats, including the non-square blocks found with some ASTC formats,
we can advertise ASTC formats. Passes dEQP-GLES3.*astc* which
exercises everything here. (These tests passed before by decompressing
the textures to RGBA8 UNORM in the frontend, but it's much more
efficient to use real ASTC textures as done here.)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig c71e84b37e asahi: Advertise ETC1
ETC2 is backwards compatible with ETC1, we just need to declare the
format mapping.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig b37b8eabd3 asahi: Handle 2-channel sRGB textures
I'm not sure why we need to set this magic bit, but this fixes the
non-depth_component portion of
dEQP-GLES3.functional.texture.format.sized.*, e.g

dEQP-GLES3.functional.texture.format.sized.cube.srgb_rg8_pot

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig 464f59f723 ail: Rewrite tiled memcpy for correctness
Move tiling.c into ail, using ail data structures and helpers to manage
the tiling. This fixes a staggering number of issues with the tiling
routines:

* NPOT block sizes defeatured. The hardware only supports POT block
  sizes. There's no need to handle anything else.

* Use ail to determine tile sizes, instead of the broken
  agx_select_tile_shift routine that didn't work for non-square tile
  sizes (for instance).

* Handle up to 128x128 tiles, as required by 8bpp textures.

* Handle non-square tiles. If the block size is not a multiple of 4, the
  tile size will be of the form 2n x n. This is easy with the ail_tile
  data structure, but not possible architecturally with
  agx_select_tile_shift. This is required for 16bpp and 64bpp textures.

* Express in terms of elements instead of pixels, using unit
  suffixes to make the dimensional analysis obvious. In particular this
  handles tiling of block-compressed textures by tiling the blocks
  themselves. This is required for block-compressed textures (internally handled
  like smaller 64bpp textures).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig 6ff75da8aa ail: Introduce image layout module
Introduce ail, a small library for working with the image (and buffer)
layouts encountered with AGX hardware. Its design is inspired by isl. In
particular, ail strives to use isl unit suffixes and to represent
quantities in a canonical, API-agnostic fashion [1].

ail replaces the old miptree code (based on some ad hoc heuristics that
passed a few dEQP tests). It is based on a thorough reverse-engineering
of AGX's twiddled format, courtesy of Asahi Lina, Dougall Johnson, and
me. This corrects our handling of many common cases that were totally
wrong in the old code, leading to GPU faults.

Unlike the code, ail differentiates between pixels and elements
consistently, allowing block-compressed formats like ETC2 to be
supported correctly. These formats will be enabled later in the series.

This commit fixes Inochi2D, glmark2 -brefract and -bterrain, and who
knows what else.

ail stands for { Asahi, AGX } Image { Layout, Library } at your
convenience. ail is best served warm.

Liberal use of ail is recommended. Yum!

[1] https://docs.mesa3d.org/isl/units.html

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig 5057d6787a asahi: Fix ASTC enums
The ASTC enum only encodes the block width/height. By contrast the
LDR/HDR/sRGB distinction is encoded as UNORM/Float and via the sRGB bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig 01323ba470 asahi: Fix bind sizes
Otherwise we get a nonsensical count of 129 in one Metal sample. Exact
size still not known but this bounds somewhat.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig e71f8ef439 asahi: Add XML for multisampled textures
Metal supports MSAA 2x and MSAA 4x, neither at the same time as
mipmapping. That matches the GL spec requirement.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig c8435e4bc6 asahi: Rename 'tiled 64x64' to 'twiddled'
To account for non-64x64 tile sizes, as well as the other forms of
tiling that may come up with compression.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Alyssa Rosenzweig 88eea62adb asahi: Identify compressed render target fields
We won't be implementing AGX compression for a while, but this gets some
unknowns out of the way when looking at dumps from Metal that use it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-09-01 22:30:48 +00:00
Emma Anholt 28b2252d0a nir: Make nir_lower_discard_if() handle demotes and terminates, too.
AGX and zink both want all of these lowered, but nir_to_tgsi will want
only demote (and terminate if it was possible from GLSL but it's not)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15932>
2022-08-31 18:26:19 +00:00
Jason Ekstrand 4fab5ae8ba asahi: Use util/bitpack_helpers.h
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18062>
2022-08-30 04:28:34 +00:00
Alyssa Rosenzweig 15e15422ba asahi: Fix warning building for macOS 12.0
Unnecessary rename that breaks forward compatibility... but Apple says
this is just NULL. Do the simpler thing. Note that the argument is a
mach_port_t, which is a natural_t == uint32_t in userspace... even
though it's a pointer in the kernel. Although Apple's docs claim that
kIOMasterPortDefault is NULL, it's really just 0.

../src/asahi/lib/agx_device.c:290:35: warning: 'kIOMasterPortDefault' is deprecated: first deprecated in macOS 12.0 [-Wdeprecated-declarations]
      IOServiceGetMatchingService(kIOMasterPortDefault, matching);
                                  ^~~~~~~~~~~~~~~~~~~~
                                  kIOMainPortDefault

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18121>
2022-08-21 14:32:40 -04:00
Alyssa Rosenzweig 5fd8ae1541 asahi: Identify depth clip mode bit
Setting this bit (at the batch level, not the draw level!) switches to
[-1, 1] clipping instead of Metal's preferred [0, 1] clipping. Using
this bit allows us to drop the clip_halfz lowering we had before, saving
2 instructions in every vertex shader.

Fixes dEQP-GLES2.functional.depth_range.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17948>
2022-08-14 19:59:19 +00:00
Alyssa Rosenzweig 3712609ee3 agx: Only emit the used components of gl_FragCoord
In case a shader only use gl_FragCoord.xy, this avoids wasting
coefficient registers for gl_FragCoord.zw which should be a small
optimization. It's also less work for DCE but I'm less worried about
that.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig 17168162fb agx: Remove p_extract
It's now unused. We didn't have coalescing for it anyway, splits are the
preferred alternative.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig c1900cb951 agx: Handle type-changing splits
If we want to break down a 64-bit value into its 32-bit halves, we want
to be able to use a split for this:

   lo, hi = split long

Extend the RA to handle this case.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig f86ad382c5 agx: Stop using broken idiv lowering
It is, as the name suggests, broken. Instruction count goes from 50->53
on the shader in
dEQP-GLES2.functional.shaders.operator.binary_operator.div.highp_int_fragment.
I'm happy to eat that cost in exchange for correct results!

There are lots more low-hanging opportunities for optimizations to that
shader:

- fuse double icmpsel for the b2i32(cmp) sequences
- promoting big immediates to uniforms
- fusing integer multiply+add

But for now this is acceptable and anyway I'm doing this on "fix broken
NIR lowering" time and not Asahi time.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig f28c631a89 agx: Implement nir_op_umul_high
This is crucial to the efficiency of the accurate idiv path.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig aab535ffda agx: Extract umul_high implementation
We can implement umul_high (for both 16-bit and 32-bit types)
efficiently by multiplying in the next larger type size and extracting
the upper word. We already have such an implementation (for instancing).
Extract it so we can use it for emit_alu too.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig a8cea8679d agx: Assert that registers are naturally aligned
This seems to be an architectural constraint. Ensure that RA satisfies
it, because otherwise we're left with mysterious fails.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig 8c2e626064 agx: Align 64-bit register pairs
This seems to be necessary for correct operation.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig 5631b3352e agx: Lower more ALU operations
Noticed while switching idiv lowerings. We could do better on some of these.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig f759459cd6 agx: Implement noperspective interpolation
We need to get a matching coefficient register and change the encoding
of the iter instruction slightly, but otherwise this is normal.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig 638d7f542e agx: Use split instead of extract for ldcf
For more uniform handling in the RA. This gets rid of the extra moves
with flat shading.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:54 -04:00
Alyssa Rosenzweig 744b4a0f7f agx: Rename varying load instructions
Unlike Mali (where I borrowed the old names from), these are not loads
in the memory sense. They are simply register loads and arithmetic.
Rename accordingly, using PowerVR names and public Apple names as a
guide.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:53 -04:00
Alyssa Rosenzweig 14bf020d75 agx: Model perspective coefficient reg in the IR
For perspective-correct interpolation, the W coefficient register is
needed. Instead of hardcoding this to cf0 and special casing, model this
in the IR and let the general handling kick in.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:53 -04:00
Alyssa Rosenzweig 24c3084411 agx: Add AGX_MESA_DEBUG=noopt option
To disable the optimizer. Trying to root cause a Neverball bug, this
gives one less thing to worry.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:53 -04:00
Alyssa Rosenzweig f3877f56ba asahi,agx: Rewrite varying linking
Instead of using driver_location magic and hoping things work, make the
linkage between vertex and fragment shaders explicit. Thanks to the
coefficient register mechanism reverse-engineered and documented earlier
in this series, this does not require any shader keys to support
separable shaders. It just requires that we regenerate the coefficient
register binding tables at draw time, based on the varying layouts
decided by the compiler independently for the VS and FS. This is more
robust in the face of separate shaders.

This also gets us glProvokingVertex() support without shader keys.

After that, we don't need any of the remapping prepasses. For fragment
shaders, any old mapping will do, so we can assign coefficient registers
as we go (based on what the program actually uses, not nir_variable
information that might be stale by this point). We do want to cache
coefficient registers, particularly for fragcoord.w which is used for
perspective interpolation everywhere.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:43:26 -04:00
Alyssa Rosenzweig 4b21db4111 asahi: Decode Interpolation packets
These have been known, just were missed.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:38:11 -04:00
Alyssa Rosenzweig c67169d218 asahi: Fix varying XML
Lots of changes from reverse-engineering harder the interactions with
fp16 and noperspective and such, and comparing against the PowerVR
driver code in Mesa that's been released since this XML was
originally written.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:38:11 -04:00
Alyssa Rosenzweig ed215183e2 asahi: Encode known bits of Linkage in the XML
I'm pretty sure about these. There's too much hex anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:15:03 -04:00
Alyssa Rosenzweig 034d52643c asahi: Correct bind fragment pipeline size
A number of structures encode their size, but we were ignoring it just
for this fragment pipeline bind. Fix that.

This fix might also apply to bind vertex pipeline. Unsure.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:15:03 -04:00
Alyssa Rosenzweig 651e4677ca asahi: Split vertex/fragment pipeline binds
Although these are similar data structures, they are not identical and
trying to cover both in the same struct is causing problems with
aliasing. Split them out to get a more accurate representation.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:15:03 -04:00
Alyssa Rosenzweig b1180fe2f6 asahi: Fix using multiple textures/samplers
The counts for textures/samplers are specified in the bind
texture/sampler packets. What's in the bind pipeline appear to be...
hints? of some kind? It's a direct function of the numbers of textures
and samplers, but much more coarse. Unknown purpose.

This should be correct for up to 48 textures and at least 8 samplers.
For more than 48 textures, Metal switches to a "bindless" mode, where
the textures are instead bound with a bind uniform packet, ts* is no
longer read in the shader, and instead registers and immediates are used
to index the texture with a substantial preshader. Details TBD. We don't
need to worry about that for a long while, though.

Fixes a number of dEQPs.

   dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_both,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_fragment,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_vertex,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_both,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_fragment,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_vertex,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_both,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_fragment,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_vertex,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_both,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_fragment,Crash
   dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_vertex,Crash

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:15:03 -04:00
Alyssa Rosenzweig d2fef02cc0 asahi: Dump all textures&samplers
This confirms the actual size of the texture descriptor -- 24 bytes.
The last 8 bytes have so far only been zeroed. It also confirms we got
the sampler descriptor size right.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:15:03 -04:00
Alyssa Rosenzweig c045d3761c asahi: Extend counts in BIND packets
We can bind at least 16 textures. Fix the sizes in the XML so this can
be decoded correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:15:03 -04:00
Alyssa Rosenzweig e441896eb8 agx: Fix ld_var cf packing
Make it handle larger coefficient registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:15:03 -04:00
Alyssa Rosenzweig 47a3f1226c agx: Fix packing of samplers in texture instrs
Typo in the handwritten packing code, oof!

Fixes incorrectly repeated shadows in Neverball (among many other bugs,
I assume). Huge thanks to Lina for the idea that this was the
bug -- fixing it was a breeze from there :-)

Fixes: 9f55538834 ("agx: Pack texture ops")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Suggested-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-08-07 20:15:03 -04:00
Alyssa Rosenzweig 8066ef9d30 agx: Port minifloat tests to GTest
These tests predate using GTest in the compiler. Now that we do, we'd like to
have the tests together so they run regularly.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17824>
2022-08-01 18:34:11 +00:00
Jason Ekstrand 642283a2c1 panfrost,asahi: Use util_sign_extend for unpacking
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17214>
2022-07-06 11:23:18 +00:00
Alyssa Rosenzweig 76981e5615 agx: Handle loop { if { loop { .. } } }
We need to push loop nesting to handle this correctly -- at the end of
the innermost loop, the correct nesting is 1 (from the if), not 0.

Fixes assertion failure in

  dEQP-GLES2.functional.shaders.struct.local.dynamic_loop_nested_struct_array_fragment,UnexpectedPass
  dEQP-GLES2.functional.shaders.struct.local.dynamic_loop_nested_struct_array_vertex,UnexpectedPass
  dEQP-GLES2.functional.shaders.struct.uniform.dynamic_loop_nested_struct_array_fragment,UnexpectedPass
  dEQP-GLES2.functional.shaders.struct.uniform.dynamic_loop_nested_struct_array_vertex,UnexpectedPass

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17128>
2022-06-22 21:23:50 +00:00
Alyssa Rosenzweig 2338dcd392 asahi,agx: Don't set PIPE_CAP_POINT_COORD_ORIGIN_UPPER_LEFT
Tell the state tracker our point coordinates have a lower left origin
instead of an upper left origin, and remove our point coordinate
flipping code. Saves an instruction in any shader that reads
gl_PointCoord.y

Note: the OpenGL blob also emits an "fadd $y', ^y.neg, 1.0" to flip
point coordinates, so this isn't just a Metal weirdness.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16829>
2022-06-08 14:10:50 +00:00
Alyssa Rosenzweig 1b7304f44b asahi: Add wrap library
Add a library that wraps the key IOKit entrypoints used in the macOS
UABI for AGX. Our wrapped routines print information about the kernel
calls made and dump work submitted to the GPU using agxdecode. This code
has two major use cases:

1. Debugging Mesa, particularly around the undocumented macOS
   user-kernel interface. Logs from Mesa may compared to Metal to check
   that the UABI is being used correcrly.

2. Reverse-engineering the hardware, using this as glue to get at the
   "interesting" GPU memory.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:58:07 -04:00
Alyssa Rosenzweig 1d0d27aac7 asahi: Allocate a larger segment list
This ought to be dynamically allocated but because this is macOS kernel
UABI only gunk, let's just hack around it...

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig 689be69681 asahi: Fix pipeline decoding
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig 8a1ee708a4 asahi: Improve render target dumping
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig d8227f09d0 asahi: Drop some unknowns
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig 03a3a7843e asahi: Identify suballocated size
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig 14d966734f asahi: Identify suballocation mechanism
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig ca9b1d48fe asahi: Decode resource allocation requests
We already know much of this structure, let's pretty print to simplify
our traces.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig 0c120cf141 asahi: Decode resource allocation responses
We already know much of this structure, let's pretty print to simplify
our traces.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig 1e42e4a390 asahi: Validate segment list length
This is easy now!

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig 343f4f886f asahi: Split unknown field in segment list header
Seen as 0x8000.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig 6b12292754 asahi: Add segment list pretty printer
Validate all the new expectations and print all the fields. This should
make differences between the drivers obvious, I hope.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:11:08 -04:00
Alyssa Rosenzweig db32b4a064 asahi: Sync some names with Project Zero
This should clarify a few things I didn't get independently
investigating the interface. Of coruse, I got other pieces... the sum of
the parts is better :-)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:10:57 -04:00
Alyssa Rosenzweig 6e59474ced asahi: Identify partial render pipeline
Needed if a partial render is incurred from overflowing the parameter
buffer (too much geometry).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig 666f307d41 asahi: Add a depth bias structure
This is simple and corresponds directly to the Metal inputs. However,
the alignment is a bit tricky, so let's add formal XML for it.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig cb760a00c2 asahi: Identify depth bias enable bit
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig 7a0c220401 asahi: Identify "set depth bias index" field
Grouped together with the "set scissor index" field, which is natural.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig ff84c07b21 asahi: Identify depth bias array
"Inspired" by PowerVR code, by comparison.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig a39fb009d2 asahi: Note unknown field
...used internally with visibility tests, together with a weird
vertex/compute-like shader used to zero the visibility buffer.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig baa54da7d6 asahi: Relax Draw "command" check
Other values in the lower byte seen with multiple draws and
visibility testing.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig d8541d52d2 asahi: Add XML used for visibility tests
Aka occlusion queries. There is an annoying limitation in the hardware
(reflected in Metal) that only a single buffer may be bound per render
pass, with the per-draw settings merely specifying an offset.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig 46a7c10349 asahi: Dump "unknown 4a" structure
A few fields are known at least, let's decode them correctly instead of
falling back to a hex dump.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:04 -04:00
Alyssa Rosenzweig a5e6a5e585 asahi: Identify more depth pipeline fields
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-22 17:09:00 -04:00
Alyssa Rosenzweig 6aadd72bd4 asahi: Account for every byte of the cmdbuf
This adds the remaining XML. I don't know how much of this is correct,
but it nominally accounts for every byte. So there shouldn't be more
surprises in the command buffer after this.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-21 22:01:33 -04:00
Alyssa Rosenzweig c61e660323 asahi: Handle 3rd deflake address
Context switching is so broken. Just trying to get closer. Adding some
XML here to see if we're missing something else obvious.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-05-21 22:01:33 -04:00