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asahi: Identify depth clip mode bit 

Setting this bit (at the batch level, not the draw level!) switches to
[-1, 1] clipping instead of Metal's preferred [0, 1] clipping. Using
this bit allows us to drop the clip_halfz lowering we had before, saving
2 instructions in every vertex shader.

Fixes dEQP-GLES2.functional.depth_range.*

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17948>
This commit is contained in:
Alyssa Rosenzweig 2022-08-07 19:17:40 -04:00 committed by Marge Bot
parent a6f88863f6
commit 5fd8ae1541
5 changed files with 5 additions and 17 deletions
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7
src/asahi/compiler/agx_compile.c
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@ -1673,13 +1673,6 @@ agx_compile_shader_nir(nir_shader *nir,
NIR_PASS_V(nir, nir_lower_vars_to_scratch, nir_var_function_temp, 16,
glsl_get_natural_size_align_bytes);
NIR_PASS_V(nir, nir_lower_indirect_derefs, nir_var_function_temp, ~0);
if (ctx->stage == MESA_SHADER_VERTEX) {
/* Lower from OpenGL [-1, 1] to [0, 1] if half-z is not set */
if (!key->vs.clip_halfz)
NIR_PASS_V(nir, nir_lower_clip_halfz);
}
NIR_PASS_V(nir, nir_split_var_copies);
NIR_PASS_V(nir, nir_lower_global_vars_to_local);
NIR_PASS_V(nir, nir_lower_var_copies);

3
src/asahi/compiler/agx_compile.h
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@ -236,9 +236,6 @@ struct agx_vs_shader_key {
unsigned vbuf_strides[AGX_MAX_VBUFS];
struct agx_attribute attributes[AGX_MAX_ATTRIBS];
/* Set to true for clip coordinates to range [0, 1] instead of [-1, 1] */
bool clip_halfz : 1;
};
struct agx_fs_shader_key {

1
src/asahi/lib/cmdbuf.xml
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@ -581,6 +581,7 @@
<field name="Deflake 3" start="110:0" size="64" type="address"/>
<field name="Unk 112" start="112:0" size="32" default="0x1" type="hex"/>
<field name="Unk 114" start="114:0" size="32" default="0x1c" type="hex"/>
<field name="OpenGL depth clipping" start="116:24" size="1" type="bool"/>
<field name="Unk 118" start="118:0" size="32" default="0xffffffff" type="hex"/>
<field name="Unk 119" start="119:0" size="32" default="0xffffffff" type="hex"/>
<field name="Unk 120" start="120:0" size="32" default="0xffffffff" type="hex"/>

10
src/gallium/drivers/asahi/agx_state.c
View File

@ -670,14 +670,11 @@ agx_upload_viewport_scissor(struct agx_pool *pool,
cfg.translate_x = vp->translate[0];
cfg.translate_y = vp->translate[1];
cfg.translate_z = vp->translate[2];
cfg.scale_x = vp->scale[0];
cfg.scale_y = vp->scale[1];
/* Assumes [0, 1] clip coordinates. If half-z is not in use, lower_half_z
* is called to ensure this works. */
cfg.translate_z = minz;
cfg.scale_z = maxz - minz;
};
cfg.scale_z = vp->scale[2];
}
/* Allocate a new scissor descriptor */
struct agx_scissor_packed *ptr = batch->scissor.bo->ptr.cpu;
@ -1083,7 +1080,6 @@ agx_update_vs(struct agx_context *ctx)
{
struct agx_vs_shader_key key = {
.num_vbufs = util_last_bit(ctx->vb_mask),
.clip_halfz = ctx->rast->base.clip_halfz,
};
memcpy(key.attributes, ctx->attributes,

1
src/gallium/drivers/asahi/magic.c
View File

@ -268,6 +268,7 @@ demo_cmdbuf(uint64_t *buf, size_t size,
cfg.attachment_length = nr_attachments * AGX_IOGPU_ATTACHMENT_LENGTH;
cfg.unknown_offset = offset_unk;
cfg.encoder = encoder_ptr;
cfg.opengl_depth_clipping = true;
cfg.deflake_1 = deflake_1;
cfg.deflake_2 = deflake_2;