Commit Graph

163250 Commits

Author SHA1 Message Date
David Heidelberg 042f006a43 .gitignore: add VSCode and VSCodium
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19902>
2022-11-21 23:09:30 +00:00
David Heidelberg c415d8f08b ci: ci_run_n_monitor.py: fail when job is not found
Acked-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19902>
2022-11-21 23:09:30 +00:00
Emma Anholt 50c7abefa6 ci/freedreno: add some missing a630 flakes.
Two from the GL 4.5 update, one that's been around longer.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19905>
2022-11-21 22:45:46 +00:00
Emma Anholt be64e0cdc0 ci/turnip+zink: Generalize the 16-bit copy_image fails.
We just had another fail of the non_compressed texture2d_array group, and
we've got enough of a pattern here.

I left in the specific cases that had some debug info, though.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19905>
2022-11-21 22:45:46 +00:00
Alyssa Rosenzweig 70f40ea4d3 asahi: Wire up all BCn formats
We have these native. Passes the relevant piglits. Large reduction in memory
usage on Xonotic on higher settings (8x less memory per texture), which allows
Xonotic to run at high settings without OOMing.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Tested-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19903>
2022-11-21 22:33:43 +00:00
Gert Wollny e496d24cb2 virgl: don't a use staging when a resources created with the shared flag
There seems to be a problem with running firefox by using Xwayland that
results in a shared resources being not always tagged as using staging.

As a result one process tries to map the resource that was allocated as
one that uses staging without actually using the staging resource, and
hence the mapped range only accounts for the small region that we have
to allocated because a zero-allocation doesn't work, but the application
mapping the resource assumes that a properly sized range is mapped, and
consequently this results in invalid memory access.

To work around this issue disable creating staging for resources that
are created by using shared binding. It is not clear to me whether this
is the best fix, but it seems to quell the issue.

Fixes: c9d99b7eec
    virgl: Fix texture transfers by using a staging resource

Related: https://gitlab.freedesktop.org/virgl/virglrenderer/-/issues/291
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19655>
2022-11-21 21:37:50 +00:00
Sajeesh Sidharthan c22fbeb72a gallium/drivers: copy only the actual number of slice parameters
currently max number of slice(tile) parameters are copied for av1.
copy only actual number of slice parameters

Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19878>
2022-11-21 20:14:21 +00:00
Rhys Perry 368be87255 nir/algebraic: shrink 64-bit bitwise operations with 0/-1 constant half
fossil-db (navi21):
Totals from 457 (0.34% of 135636) affected shaders:
Instrs: 259349 -> 250383 (-3.46%)
CodeSize: 1411976 -> 1369136 (-3.03%)
Latency: 2175961 -> 2148158 (-1.28%)
InvThroughput: 502206 -> 490244 (-2.38%)
Copies: 15238 -> 15232 (-0.04%); split: -0.07%, +0.03%

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19748>
2022-11-21 17:34:46 +00:00
Konstantin Seurer 8133d5551d radv/rt: Return the correct result for requested deferral
We do not implement deferred host operations so we will return
VK_OPERATION_NOT_DEFERRED_KHR for now.

Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19882>
2022-11-21 16:59:41 +00:00
Sajeesh Sidharthan 8d8caa44bd frontends/va: remove unused slice_param_idx variable
slice_param_idx was added to handle multiple slice params.
it's not used anymore.

Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19877>
2022-11-21 16:45:42 +00:00
Rhys Perry 3061bc792d aco: ensure MRT0 is written with dual source blending
Fixes crucible test func.shader.dualsrc_mrt0_undef on polaris10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19806>
2022-11-21 15:01:56 +00:00
Rhys Perry ea0ae17fc4 radv: disable MRT compaction with dual-source blending
Fixes crucible tests func.shader.dualsrc_mrt0_undef on navi21 and
func.shader.dualsrc_mrt1_undef on polaris10.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: 22.3 mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19806>
2022-11-21 15:01:56 +00:00
José Roberto de Souza 68652dca0c iris: Fix iris_bo_alloc() flags call argument
binder_realloc() -> iris_bo_alloc() is setting 4096 as flags parameter.
Up to now this is harmeless as there is no BO_ALLOC flag that uses
bit 12 but is better to avoid any future issues.

Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19898>
2022-11-21 14:35:55 +00:00
Danylo Piliaiev f1305d49d9 tu: Implement VK_EXT_post_depth_coverage
Passes:
 dEQP-VK.pipeline.monolithic.multisample.sample_mask_with_depth_test.*
 KHR-GL45.post_depth_coverage_tests.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19682>
2022-11-21 14:11:05 +00:00
Pavel Ondračka 1ec172646c r300: more informative too many ALU instructions error
Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
2022-11-21 13:54:39 +00:00
Pavel Ondračka b70543a955 r300: delete backend branch emulation
We now depend on NIR doing the right thing. It was not able to
handle the few cases where NIR failed anyway (and even if it did,
such complex cases would hit the instruction limit later).

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
2022-11-21 13:54:39 +00:00
Pavel Ondračka 2fe73e3bcb r300: abort shader compilation early on loops and branches
R300/R400 GPUs can't do it in hardware and all the lowering should have
happened in NIR already, there is no point in wasting CPU time, just to
abort later when emitting.

Reduces CPU time for dEQP run by ~25% for RV370. The wallclock time is
now just slighly above 1 minute at 10 threads, mostly determined by the
long-running dEQP-GLES2.functional.flush_finish.* tests.

Signed-off-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Reviewed-by: Filip Gawin <filip@gawin.net>
Tested-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19766>
2022-11-21 13:54:39 +00:00
Bas Nieuwenhuizen 8d37ab6bfa radv: Fix custom build id with C90 compilation.
Seems some build configurations have problems with VLAs still.

Fixes: 97641e5c94 ("radv: Add ability to override the build id for the cache.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19869>
2022-11-21 12:57:41 +00:00
Maíra Canal d34f3a1db5 v3dv: fix multiple typos
Signed-off-by: Maíra Canal <mcanal@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19538>
2022-11-21 11:31:29 +00:00
Gert Wollny 67ffe25fd9 r600: Fix lower-to-scalar on TTN path
We must limit what alu ops are scalazized, and since we now
run finalize_nir we also have to make sure not to try to
scalarize backend specific instructions that are introduced
there.

While we touch the code, also remove the vectorization, it is
no longer helping.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7747

Fixes: a81c50a2 (r600/sfn: implement finalize_nir)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19892>
2022-11-21 10:53:44 +00:00
Gert Wollny a69eafc422 r600: reference glsl type system during translation
VL doesn't initialize the type systen, but creates shaders in TGSI.
When these are translated to NIR and then compiled in the driver
we need to have a reference to the glsl type system.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7453

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19883>
2022-11-21 10:43:51 +00:00
Daniil Tatianin 089ae08ab1 intel_batch_decoder: disasm shaders when decoding states besides VS
Previously only 'decode_vs_state' would dump the referenced shader,
which meant we completely ignored every other shader when decoding
the '3DSTATE_PIPELINED_POINTERS' command.

Move the program disassembly logic from 'decode_vs_state' into a
common 'disasm_program_from_group' helper and call it from every
other decode_*_state function, too.

Signed-off-by: Daniil Tatianin <99danilt@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19880>
2022-11-21 10:00:32 +00:00
Jose Maria Casanova Crespo c82775e3c7 v3d: Minor fixes on sand8 blit based on sand30 modifications
* load_uniform for sand8_stride is uint32 instead of int32 and its range
  is 4 instead of 1 as it is counted in bytes.
* Now we save and restore constant buffer 1 properly for the ubo used
  in the blit. We need to take into account that in V3D the first UBO
  with index 0 is stored on constant buffer 1, because gallium uses
  internally contant buffer 0 (See for reference commit c8212731e7)
* Removed not needed return.
* Added shader information about uniforms, ubos, inputs and outputs.
* Fixed typos in the comments.

Fixes: 95c4f0f910 "v3d: Enables DRM_FORMAT_MOD_BROADCOM_SAND128 support"
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
2022-11-21 09:08:44 +00:00
Jose Maria Casanova Crespo e97b20f3ca v3d: Also expose DRM_FORMAT_MOD_BROADCOM_SAND128 with PIPE_FORMAT_P030
Now we can display h265-10bit decoded frames formats on Raspberry Pi 4
devices on GL/ES applications.

v2: Don't expose LINEAR or UIF formats for P030 format.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
2022-11-21 09:08:44 +00:00
Jose Maria Casanova Crespo 653cf8c8d2 v3d: Blit for P030 format with BROADCOM_SAND128 modifier to P010 UIF
Implements the support to blit SAND modifier with columns 128-bytes-wide
support for P030 format to P010 with UIF layout. This allows sampling
from H265 10-bit frames exported by the video decoder on the Raspberry
Pi 4 devices.

When a DRM_FORMAT_MOD_BROADCOM_SAND128 is enabled with an imported P030
texture. The sand30 blit converts the Luma and Chroma planes to
a tiled P010 format that can be sampled using gallium YUV lowerings
without the interleaved 128-bytes-wide-columns.

This patch follows a similar approach to SAND8 blit but extracting luma
and chroma components from the DRM_FORMAT_P030 format. P030 is a two
plane YCbCr420 format where 3 10 bit components with 2 padding bits are
packed in 4 bytes.

index 0 = Y plane, [31:0] x:Y2:Y1:Y0 2:10:10:10 little endian
index 1 = Cr:Cb plane, [63:0] x:Cr2:Cb2:Cr1:x:Cb1:Cr0:Cb0
                       [2:10:10:10:2:10:10:10] little endian

After the sand30_blit is done, the shadow texture is an UIF tiled texture
with an R16_UNORM format for luma and R16G16_UNORM for chroma.

To reduce the number of texture-fetch operations during the blit, we
read pairs of 32-bit dwords. They include 6 10-bit unorm components.
And then we write 4 UNORM16 components from an uvec4 because our render
targets do not support writing to UNORM16 formats.

As sampling will be done using 16bpp (luma) and 32bpp (chroma), the
sand30_blit writes consider the different microtile layouts of UIF
format between 64, 32 and 16 bpp.

v2: Fixes save and recovery of constant buffers (Iago)
    Typo corrections. (Iago)
    Removed not needed return. (Iago)
    Added shader information about uniforms, ubos, inputs and outputs.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
2022-11-21 09:08:44 +00:00
Jose Maria Casanova Crespo 4ea4147935 gallium/dri: Add P030 format
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19639>
2022-11-21 09:08:44 +00:00
Samuel Pitoiset e253729e03 zink: require extendedDynamicState3ColorBlendEquation for full ds3
Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19851>
2022-11-21 08:43:56 +00:00
Tatsuyuki Ishi 390c4b337a radv: Support accelerationStructureCaptureReplay.
The address itself was already stable assuming that the memory itself was
allocated with capture/replay. Enable the feature flag and add an equality
check to return VK_ERROR_INVALID_OPAQUE_CAPTURE_ADDRESS_KHR on mismatch.

Tested with:
- dEQP-VK.ray_tracing_pipeline.capture_replay.*
- q2rtx gfxrecon replays correctly without major errors.
  * There are debug logs about VkBuffers missing opaque address
  for unknown reason, however the AS part is confirmed to be correctly
  captured.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19841>
2022-11-21 08:22:03 +00:00
Samuel Pitoiset 165ef452fd radv/ci: add one more pipeline barrier test as flake
With the new memory type, this test timeout most of the time but it
always pass.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
2022-11-21 07:55:24 +01:00
Samuel Pitoiset 5c5735fd68 radv: advertise VK_EXT_descriptor_buffer
Pass dEQP-VK.*descriptor_buffer*.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
2022-11-21 07:55:24 +01:00
Samuel Pitoiset 46e0c77582 radv: implement VK_EXT_descriptor_buffer
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
2022-11-21 07:55:24 +01:00
Samuel Pitoiset e3fae40e96 radv: always restore NULL descriptor sets for meta operations
A valid but NULL descriptor set indicates a descriptor buffer.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
2022-11-21 07:55:23 +01:00
Samuel Pitoiset a59be04ea5 radv: rework writing image/buffer/accel_struct descriptors slightly
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
2022-11-21 07:55:23 +01:00
Samuel Pitoiset e8cff91bd5 radv: avoid RMW operations in radv_make_texel_buffer_descriptor()
This would hurt performance depending on the memory type.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
2022-11-21 07:55:23 +01:00
Samuel Pitoiset fcd53eda0e radv: force 32-bit address-space for descriptor buffers usage
Descriptor pointers are passed through shaders with 32-bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
2022-11-21 07:55:23 +01:00
Samuel Pitoiset 94bea63936 radv: add 32-bit memory types for visible VRAM and cached GTT
These would be only exposed for descriptor buffers which need to be
CPU accessible and because descriptor pointers are 32-bit.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19808>
2022-11-21 07:55:23 +01:00
Vinson Lee d6d772d3d1 asahi: Fix memory leak on error path.
Fix defect reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable nresource going out of scope leaks the storage it points to.

Fixes: 7522f4f714 ("asahi: Make resource creation code modifier-aware")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19889>
2022-11-21 04:38:55 +00:00
Qiang Yu e3b1f26a2b ac/llvm: fix 16bit varying llvm compile error
Found when 16bit vec3 varying with llvm14 (not found
when llvm15), one 32bit vec4 slot is filled like this:
  vec3[0] | undef
  vec3[1] | undef
  vec3[2] | undef
  undef   | undef

LLVM error is for the elements with undef:
  %287 = insertelement float %280, half %279, i64 0

After this change, we get:
  %287 = insertelement <2 x half> %280, half %279, i64 0

Fixes: 279eea5bda ("amd/llvm: Transition to LLVM "opaque pointers"")
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19848>
2022-11-21 01:06:56 +00:00
Vinson Lee e8ff841e98 asahi: Fix memory leak on error path.
Fix defect reported by Coverity Scan.

Resource leak (RESOURCE_LEAK)
leaked_storage: Variable rsc going out of scope leaks the storage it points to.

Fixes: 01964625eb ("asahi: Implement agx_resource_from_handle")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19887>
2022-11-20 13:41:55 -08:00
Yusuf Khan 0803e39b71 mapi: update gles 1.1 extention packet link
Signed-off-by: Yusuf Khan <yusisamerican@gmail.com>
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19874>
2022-11-20 15:14:01 +00:00
Daniel Schürmann f1f33582e7 radv/rt: use explicitly named sbt entries in radv_pipeline_group_handle
This improves readability, makes it less error-prone and
allows for easier changes in future.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19850>
2022-11-20 11:30:16 +00:00
Eric Engestrom 2b99523a95 v3d(v): account for debug flags when using the cache
Signed-off-by: Eric Engestrom <eric@igalia.com>
Cc: mesa-stable
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19796>
2022-11-20 08:32:04 +00:00
Alyssa Rosenzweig cee2c4624d asahi: Advertise all supported renderable formats
Now that we have the new tilebuffer infrastructure in place, all renderable
formats should be working.

This reverts commit 32ab63b4fcaaaf832d549ddcf7b3a225c5f73df4.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-19 20:25:41 +00:00
Alyssa Rosenzweig 74e92274af asahi,agx: Use new tilebuffer infrastructure
Flag day change to replace the previous hardcoded background/end-of-tile shaders
and the API-style load/store_output in fragment shaders with the generated
shaders and lowered *_agx intrinsics. This gets us working non-UNORM8 render
targets and working MRT. It's also a step in the direction of working MSAA but
that needs a lot more work, since the multisampling programming model on AGX is
quite different from any of the APIs (including Metal).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-19 20:25:41 +00:00
Alyssa Rosenzweig c5c0ea39f6 asahi: Add new clear/reload/store infrastructure
With multiple render targets, it's not practical to generate all
variants of the background and end-of-tile programs at start up. Rather
than trying, add a hash table of meta program keys to background
programs, and compile variants as they're needed.

With the new infrastructure, it's sensible to handle clears with the
same code path as reloads. In addition to getting us closer to multiple
render target support, this gets us support for non-RGBA8 render
targets, as the u8norm tilebuffer format was baked into the hardcoded
clear shader and store shaders used before.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-19 20:25:41 +00:00
Alyssa Rosenzweig 4f96651f1e asahi: Use correct tib settings for USC
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-19 20:25:41 +00:00
Alyssa Rosenzweig 555447769d asahi: Extend texture descriptor packing for MSAA
Multisampling uses different values of the dimension enum in tandem with a new
samples field. Handle this in agx_pack_texture (split off here) so we can use
the new functionality for texture descriptors in reloads too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-19 20:25:41 +00:00
Alyssa Rosenzweig cc555e0c04 asahi: Remove some bogus asserts
Hitting in dEQP-GLES31

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-19 20:25:41 +00:00
Alyssa Rosenzweig bbe7d8e4f5 asahi: Implement texture_barrier trivially
For the advanced blending tests.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-19 20:25:41 +00:00
Alyssa Rosenzweig 03dc4bc3e8 asahi: Calculate tilebuffer layout per batch
It won't be fixed soon.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-19 20:25:41 +00:00