232 lines
8.3 KiB
C
232 lines
8.3 KiB
C
/*
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* Copyright © 2021 Valve Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Timur Kristóf
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*
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*/
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#include "nir.h"
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#include "nir_builder.h"
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typedef struct
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{
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struct hash_table *range_ht;
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const nir_opt_offsets_options *options;
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} opt_offsets_state;
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static nir_ssa_scalar
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try_extract_const_addition(nir_builder *b, nir_ssa_scalar val, opt_offsets_state *state, unsigned *out_const, uint32_t max)
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{
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val = nir_ssa_scalar_chase_movs(val);
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if (!nir_ssa_scalar_is_alu(val))
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return val;
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nir_alu_instr *alu = nir_instr_as_alu(val.def->parent_instr);
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if (alu->op != nir_op_iadd ||
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!alu->src[0].src.is_ssa ||
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!alu->src[1].src.is_ssa ||
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alu->src[0].negate || alu->src[0].abs ||
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alu->src[1].negate || alu->src[1].abs)
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return val;
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nir_ssa_scalar src[2] = {
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{alu->src[0].src.ssa, alu->src[0].swizzle[val.comp]},
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{alu->src[1].src.ssa, alu->src[1].swizzle[val.comp]},
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};
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/* Make sure that we aren't taking out an addition that could trigger
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* unsigned wrapping in a way that would change the semantics of the load.
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* Ignored for ints-as-floats (lower_bitops is a proxy for that), where
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* unsigned wrapping doesn't make sense.
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*/
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if (!alu->no_unsigned_wrap && !b->shader->options->lower_bitops) {
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if (!state->range_ht) {
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/* Cache for nir_unsigned_upper_bound */
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state->range_ht = _mesa_pointer_hash_table_create(NULL);
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}
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/* Check if there can really be an unsigned wrap. */
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uint32_t ub0 = nir_unsigned_upper_bound(b->shader, state->range_ht, src[0], NULL);
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uint32_t ub1 = nir_unsigned_upper_bound(b->shader, state->range_ht, src[1], NULL);
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if ((UINT32_MAX - ub0) < ub1)
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return val;
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/* We proved that unsigned wrap won't be possible, so we can set the flag too. */
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alu->no_unsigned_wrap = true;
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}
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for (unsigned i = 0; i < 2; ++i) {
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src[i] = nir_ssa_scalar_chase_movs(src[i]);
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if (nir_ssa_scalar_is_const(src[i])) {
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uint32_t offset = nir_ssa_scalar_as_uint(src[i]);
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if (offset + *out_const <= max) {
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*out_const += offset;
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return try_extract_const_addition(b, src[1 - i], state, out_const, max);
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}
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}
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}
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uint32_t orig_offset = *out_const;
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src[0] = try_extract_const_addition(b, src[0], state, out_const, max);
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src[1] = try_extract_const_addition(b, src[1], state, out_const, max);
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if (*out_const == orig_offset)
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return val;
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b->cursor = nir_before_instr(&alu->instr);
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nir_ssa_def *r =
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nir_iadd(b, nir_channel(b, src[0].def, src[0].comp),
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nir_channel(b, src[1].def, src[1].comp));
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return nir_get_ssa_scalar(r, 0);
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}
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static bool
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try_fold_load_store(nir_builder *b,
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nir_intrinsic_instr *intrin,
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opt_offsets_state *state,
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unsigned offset_src_idx,
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uint32_t max)
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{
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/* Assume that BASE is the constant offset of a load/store.
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* Try to constant-fold additions to the offset source
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* into the actual const offset of the instruction.
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*/
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unsigned off_const = nir_intrinsic_base(intrin);
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nir_src *off_src = &intrin->src[offset_src_idx];
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nir_ssa_def *replace_src = NULL;
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if (!off_src->is_ssa || off_src->ssa->bit_size != 32)
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return false;
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if (!nir_src_is_const(*off_src)) {
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uint32_t add_offset = 0;
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nir_ssa_scalar val = {.def = off_src->ssa, .comp = 0};
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val = try_extract_const_addition(b, val, state, &add_offset, max);
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if (add_offset == 0)
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return false;
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off_const += add_offset;
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b->cursor = nir_before_instr(&intrin->instr);
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replace_src = nir_channel(b, val.def, val.comp);
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} else if (nir_src_as_uint(*off_src) && off_const + nir_src_as_uint(*off_src) <= max) {
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off_const += nir_src_as_uint(*off_src);
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b->cursor = nir_before_instr(&intrin->instr);
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replace_src = nir_imm_zero(b, off_src->ssa->num_components, off_src->ssa->bit_size);
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}
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if (!replace_src)
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return false;
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nir_instr_rewrite_src(&intrin->instr, &intrin->src[offset_src_idx], nir_src_for_ssa(replace_src));
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nir_intrinsic_set_base(intrin, off_const);
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return true;
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}
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static bool
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try_fold_shared2(nir_builder *b,
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nir_intrinsic_instr *intrin,
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opt_offsets_state *state,
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unsigned offset_src_idx)
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{
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unsigned comp_size = (intrin->intrinsic == nir_intrinsic_load_shared2_amd ?
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intrin->dest.ssa.bit_size : intrin->src[0].ssa->bit_size) / 8;
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unsigned stride = (nir_intrinsic_st64(intrin) ? 64 : 1) * comp_size;
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unsigned offset0 = nir_intrinsic_offset0(intrin) * stride;
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unsigned offset1 = nir_intrinsic_offset1(intrin) * stride;
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nir_src *off_src = &intrin->src[offset_src_idx];
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if (!nir_src_is_const(*off_src))
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return false;
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unsigned const_offset = nir_src_as_uint(*off_src);
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offset0 += const_offset;
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offset1 += const_offset;
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bool st64 = offset0 % (64 * comp_size) == 0 && offset1 % (64 * comp_size) == 0;
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stride = (st64 ? 64 : 1) * comp_size;
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if (const_offset % stride || offset0 > 255 * stride || offset1 > 255 * stride)
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return false;
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b->cursor = nir_before_instr(&intrin->instr);
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nir_instr_rewrite_src(&intrin->instr, off_src, nir_src_for_ssa(nir_imm_zero(b, 1, 32)));
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nir_intrinsic_set_offset0(intrin, offset0 / stride);
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nir_intrinsic_set_offset1(intrin, offset1 / stride);
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nir_intrinsic_set_st64(intrin, st64);
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return true;
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}
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static bool
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process_instr(nir_builder *b, nir_instr *instr, void *s)
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{
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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opt_offsets_state *state = (opt_offsets_state *) s;
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nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(instr);
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switch (intrin->intrinsic) {
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case nir_intrinsic_load_uniform:
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return try_fold_load_store(b, intrin, state, 0, state->options->uniform_max);
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case nir_intrinsic_load_ubo_vec4:
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return try_fold_load_store(b, intrin, state, 1, state->options->ubo_vec4_max);
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case nir_intrinsic_load_shared:
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case nir_intrinsic_load_shared_ir3:
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return try_fold_load_store(b, intrin, state, 0, state->options->shared_max);
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case nir_intrinsic_store_shared:
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case nir_intrinsic_store_shared_ir3:
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return try_fold_load_store(b, intrin, state, 1, state->options->shared_max);
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case nir_intrinsic_load_shared2_amd:
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return try_fold_shared2(b, intrin, state, 0);
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case nir_intrinsic_store_shared2_amd:
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return try_fold_shared2(b, intrin, state, 1);
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case nir_intrinsic_load_buffer_amd:
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return try_fold_load_store(b, intrin, state, 1, state->options->buffer_max);
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case nir_intrinsic_store_buffer_amd:
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return try_fold_load_store(b, intrin, state, 2, state->options->buffer_max);
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default:
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return false;
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}
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unreachable("Can't reach here.");
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}
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bool
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nir_opt_offsets(nir_shader *shader, const nir_opt_offsets_options *options)
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{
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opt_offsets_state state;
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state.range_ht = NULL;
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state.options = options;
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bool p = nir_shader_instructions_pass(shader, process_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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&state);
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if (state.range_ht)
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_mesa_hash_table_destroy(state.range_ht, NULL);
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return p;
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}
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