234 lines
7.5 KiB
C
234 lines
7.5 KiB
C
/*
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* Copyright © 2020 Google, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#include "nir.h"
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#include "nir_builder.h"
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/* A pass to split intrinsics with discontinuous writemasks into ones
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* with contiguous writemasks starting with .x, ie:
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*
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* vec4 32 ssa_76 = vec4 ssa_35, ssa_35, ssa_35, ssa_35
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* intrinsic store_ssbo (ssa_76, ssa_105, ssa_106) (2, 0, 4, 0) // wrmask=y
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*
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* is turned into:
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*
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* vec4 32 ssa_76 = vec4 ssa_35, ssa_35, ssa_35, ssa_35
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* vec1 32 ssa_107 = load_const (0x00000001)
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* vec1 32 ssa_108 = iadd ssa_106, ssa_107
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* vec1 32 ssa_109 = mov ssa_76.y
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* intrinsic store_ssbo (ssa_109, ssa_105, ssa_108) (1, 0, 4, 0) // wrmask=x
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*
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* and likewise:
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*
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* vec4 32 ssa_76 = vec4 ssa_35, ssa_35, ssa_35, ssa_35
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* intrinsic store_ssbo (ssa_76, ssa_105, ssa_106) (15, 0, 4, 0) // wrmask=xzw
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*
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* is split into:
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*
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* // .x component:
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* vec4 32 ssa_76 = vec4 ssa_35, ssa_35, ssa_35, ssa_35
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* vec1 32 ssa_107 = load_const (0x00000000)
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* vec1 32 ssa_108 = iadd ssa_106, ssa_107
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* vec1 32 ssa_109 = mov ssa_76.x
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* intrinsic store_ssbo (ssa_109, ssa_105, ssa_108) (1, 0, 4, 0) // wrmask=x
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* // .zw components:
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* vec1 32 ssa_110 = load_const (0x00000002)
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* vec1 32 ssa_111 = iadd ssa_106, ssa_110
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* vec2 32 ssa_112 = mov ssa_76.zw
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* intrinsic store_ssbo (ssa_112, ssa_105, ssa_111) (3, 0, 4, 0) // wrmask=xy
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*/
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static int
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value_src(nir_intrinsic_op intrinsic)
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{
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switch (intrinsic) {
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case nir_intrinsic_store_output:
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case nir_intrinsic_store_per_vertex_output:
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case nir_intrinsic_store_ssbo:
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case nir_intrinsic_store_shared:
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case nir_intrinsic_store_global:
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case nir_intrinsic_store_scratch:
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return 0;
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default:
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return -1;
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}
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}
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static int
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offset_src(nir_intrinsic_op intrinsic)
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{
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switch (intrinsic) {
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case nir_intrinsic_store_output:
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case nir_intrinsic_store_shared:
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case nir_intrinsic_store_global:
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case nir_intrinsic_store_scratch:
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return 1;
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case nir_intrinsic_store_per_vertex_output:
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case nir_intrinsic_store_ssbo:
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return 2;
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default:
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return -1;
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}
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}
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static void
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split_wrmask(nir_builder *b, nir_intrinsic_instr *intr)
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{
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const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
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b->cursor = nir_before_instr(&intr->instr);
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assert(!info->has_dest); /* expecting only store intrinsics */
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unsigned num_srcs = info->num_srcs;
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unsigned value_idx = value_src(intr->intrinsic);
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unsigned offset_idx = offset_src(intr->intrinsic);
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unsigned num_comp = nir_intrinsic_src_components(intr, value_idx);
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unsigned wrmask = nir_intrinsic_write_mask(intr);
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while (wrmask) {
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unsigned first_component = ffs(wrmask) - 1;
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unsigned length = ffs(~(wrmask >> first_component)) - 1;
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nir_ssa_def *value = nir_ssa_for_src(b, intr->src[value_idx], num_comp);
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nir_ssa_def *offset = nir_ssa_for_src(b, intr->src[offset_idx], 1);
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/* swizzle out the consecutive components that we'll store
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* in this iteration:
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*/
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unsigned cur_mask = (BITFIELD_MASK(length) << first_component);
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value = nir_channels(b, value, cur_mask);
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/* and create the replacement intrinsic: */
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nir_intrinsic_instr *new_intr =
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nir_intrinsic_instr_create(b->shader, intr->intrinsic);
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nir_intrinsic_copy_const_indices(new_intr, intr);
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nir_intrinsic_set_write_mask(new_intr, BITFIELD_MASK(length));
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const int offset_units = value->bit_size / 8;
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if (nir_intrinsic_has_align_mul(intr)) {
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assert(nir_intrinsic_has_align_offset(intr));
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unsigned align_mul = nir_intrinsic_align_mul(intr);
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unsigned align_off = nir_intrinsic_align_offset(intr);
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align_off += offset_units * first_component;
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align_off = align_off % align_mul;
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nir_intrinsic_set_align(new_intr, align_mul, align_off);
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}
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/* if the instruction has a BASE, fold the offset adjustment
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* into that instead of adding alu instructions, otherwise add
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* instructions
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*/
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unsigned offset_adj = offset_units * first_component;
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if (nir_intrinsic_has_base(intr)) {
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nir_intrinsic_set_base(new_intr,
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nir_intrinsic_base(intr) + offset_adj);
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} else {
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offset = nir_iadd(b, offset,
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nir_imm_intN_t(b, offset_adj, offset->bit_size));
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}
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new_intr->num_components = length;
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/* Copy the sources, replacing value/offset, and passing everything
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* else through to the new instrution:
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*/
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for (unsigned i = 0; i < num_srcs; i++) {
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if (i == value_idx) {
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new_intr->src[i] = nir_src_for_ssa(value);
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} else if (i == offset_idx) {
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new_intr->src[i] = nir_src_for_ssa(offset);
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} else {
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new_intr->src[i] = intr->src[i];
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}
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}
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nir_builder_instr_insert(b, &new_intr->instr);
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/* Clear the bits in the writemask that we just wrote, then try
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* again to see if more channels are left.
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*/
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wrmask &= ~cur_mask;
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}
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/* Finally remove the original intrinsic. */
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nir_instr_remove(&intr->instr);
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}
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struct nir_lower_wrmasks_state {
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nir_instr_filter_cb cb;
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const void *data;
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};
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static bool
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nir_lower_wrmasks_instr(nir_builder *b, nir_instr *instr, void *data)
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{
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struct nir_lower_wrmasks_state *state = data;
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if (instr->type != nir_instr_type_intrinsic)
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return false;
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nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
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/* if no wrmask, then skip it: */
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if (!nir_intrinsic_has_write_mask(intr))
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return false;
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/* if wrmask is already contiguous, then nothing to do: */
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if (nir_intrinsic_write_mask(intr) == BITFIELD_MASK(intr->num_components))
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return false;
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/* do we know how to lower this instruction? */
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if (value_src(intr->intrinsic) < 0)
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return false;
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assert(offset_src(intr->intrinsic) >= 0);
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/* does backend need us to lower this intrinsic? */
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if (state->cb && !state->cb(instr, state->data))
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return false;
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split_wrmask(b, intr);
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return true;
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}
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bool
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nir_lower_wrmasks(nir_shader *shader, nir_instr_filter_cb cb, const void *data)
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{
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struct nir_lower_wrmasks_state state = {
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.cb = cb,
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.data = data,
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};
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return nir_shader_instructions_pass(shader,
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nir_lower_wrmasks_instr,
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nir_metadata_block_index |
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nir_metadata_dominance,
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&state);
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}
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