Commit Graph

155828 Commits

Author SHA1 Message Date
Alyssa Rosenzweig 4b7e337b45 pan/va: Mark last register reads
On Valhall, register reads may be marked as "last" [1]. Setting the last flag
promises the hardware that the value of the register is no longer required. This
may enable hardware optimizations. In particular, it may permit the hardware to
avoid register file writes if a write to the marked register is still in the
forwarding buffer. This may improve power efficiency.

In principle, this is trivial: run liveness analysis and mark killed sources,
like we would in an SSA-based register allocator. In practice, there are a few
wrinkles to avoid hazards around staging registers and 64-bit register pairs,
requiring some additional data flow analysis and fix ups. However, nothing here
is particularly "hard", and all the ideas are already in use for the Bifrost
scheduler and the Bifrost/Valhall scoreboard analyses.

[1] In Mesa's compiler, this is called discard for historical reasons.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig d4377e1255 pan/va: Use validate_register_pair for BLEND pack
Instead of open-coding. Noticed by inspection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig b48933d641 pan/va: Include BLEND for va_swap_12
This helps "contain the crazy" and avoids special casing BLEND in compiler
passes. The Valhall instruction is roughly the same as its Bifrost counterpart,
as long as we fix up the source order (as we already do for bitwise operations)
everything works out.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig 738a1572d2 pan/va: Move va_flow_is_wait_or_none to common
We want to use this helper in the "mark last" pass too.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig 1b29a99b7b pan/va: Add header guards to valhall_enums.h
Otherwise we can't #include in multiple places.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig c5a8736552 pan/bi: Constify bi_is_staging_src argument
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig 2075bff4e8 pan/bi: Mark bi_postra_liveness_ins as MUST_CHECK
Post-RA liveness relies on the caller updating the live variable with the
results of bi_postra_liveness_ins. It is not automatic, as with regular
liveness. This means ignoring the result of bi_postra_liveness_ins is surely an
error. Mark it as MUST_CHECK to catch that error at compile time.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig 43d00c2971 pan/va: Unit test barrier handling
Add a unit test for the quirk discovered in the previos commit, because this
will cause flakes (instead of fails) if we get it wrong. Better have a
deterministic fail mode.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig 8c6b9b9c92 pan/va: Workaround quirk of barrier handling
For some unknown reason, waiting for general slots (at least for memory stores)
doesn't work properly on a BARRIER instruction. We need to wait for all general
slots right before issuing the BARRIER in addition to the general wait on the
BARRIER itself. I don't know if this is a hardware bug or some hideous
gate-saving quirk, but I observe the Mali-G78 DDK using the same workaround,
which implies this really is necessary.

Fixes rare flakes in:

   dEQP-GLES31.functional.compute.shared_var.work_group_size.float_128_1_1

Note that the flakes from that test are extremely timing dependent. Without this
change, that test is racy but we almost always win the race. Reproducing the
issue reliably requires high system load (e.g. running the CTS in the
background) and simultaneously running that test a large number of times.

Minimal shader-db impact. In particular, no cycle count regressions.

total instructions in shared programs: 2699419 -> 2699458 (<.01%)
instructions in affected programs: 22014 -> 22053 (0.18%)
helped: 2
HURT: 25
helped stats (abs) min: 1.0 max: 1.0 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.12% max: 0.12% x̄: 0.12% x̃: 0.12%
HURT stats (abs)   min: 1.0 max: 3.0 x̄: 1.64 x̃: 1
HURT stats (rel)   min: 0.07% max: 2.82% x̄: 0.69% x̃: 0.49%
95% mean confidence interval for instructions value: 1.01 1.87
95% mean confidence interval for instructions %-change: 0.38% 0.88%
Instructions are HURT.

total cvt in shared programs: 14468.81 -> 14469.42 (<.01%)
cvt in affected programs: 221.33 -> 221.94 (0.28%)
helped: 2
HURT: 25
helped stats (abs) min: 0.015625 max: 0.015625 x̄: 0.02 x̃: 0
helped stats (rel) min: 0.18% max: 0.18% x̄: 0.18% x̃: 0.18%
HURT stats (abs)   min: 0.015625 max: 0.046875 x̄: 0.03 x̃: 0
HURT stats (rel)   min: 0.10% max: 4.44% x̄: 1.06% x̃: 0.79%
95% mean confidence interval for cvt value: 0.02 0.03
95% mean confidence interval for cvt %-change: 0.57% 1.36%
Cvt are HURT.

total quadwords in shared programs: 1462496 -> 1462528 (<.01%)
quadwords in affected programs: 4632 -> 4664 (0.69%)
helped: 0
HURT: 4
HURT stats (abs)   min: 8.0 max: 8.0 x̄: 8.00 x̃: 8
HURT stats (rel)   min: 0.35% max: 7.69% x̄: 4.03% x̃: 4.03%
95% mean confidence interval for quadwords value: 8.00 8.00
95% mean confidence interval for quadwords %-change: -2.71% 10.76%
Inconclusive result (%-change mean confidence interval includes 0).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig 7fa545528d pan/va: Simplify insert flow tests
Test cases for insert flow are necessarily the reference test cases with the
NOPs stripped out. That means we don't need to duplicate the test bodies.
Deduplicate.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Alyssa Rosenzweig 35fcf8d3d7 pan/va: Move VA_NUM_GENERAL_SLOTS to common
This definition is a hardware property. It's not specific to the flow control
insertion pass, so move it to common code where other passes can use it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17091>
2022-06-21 22:19:59 +00:00
Emma Anholt d9c03df584 ci: Remove the unused .test-manual
Everyone uses .test-manual-mr now, retire the one you don't want.

Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
2022-06-21 21:38:25 +00:00
Emma Anholt 5f09b1ebe9 ci/bare-metal: Add test phase timeouts to all boards.
This should help with "marge got stuck for an hour and all I got was this
failed job with no results/" when a system intermittently wedges.

This replaces the BM_POE_TIMEOUT ("did we get something on serial in the
last 3 minutes?") that rpi had, in favor of checking that the whole test
job gets through in 20 minutes.

Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
2022-06-21 21:38:25 +00:00
Emma Anholt cd3d9a7a92 ci/bare-metal: Add handling of netboot firmwares for servo boards.
My local trogdor has a netboot firmware and I want to be able to use it to
test the timeout code I'm working on.

Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
2022-06-21 21:38:25 +00:00
Emma Anholt 3f8114d1e0 ci/bare-metal: Get rid of servo's serial feed threads.
If the SerialBuffers can just feed the same line queue, then we don't need
the extra threads reading line queues into a new merged line queue.

Less python threading code is always better.  Plus, now we can pass args
to SerialBuffer.lines() for timeout/phase.

Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
2022-06-21 21:38:25 +00:00
Emma Anholt ca453714aa ci/bare-metal: Add per-boot-stage timeouts for fastboot and poe.
This should avoid the 1-hour timeouts if something goes wrong, and just
restart.

Fixes: #6682
Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
2022-06-21 21:38:25 +00:00
Emma Anholt 1e15ec1949 ci/bare-metal: Apply autopep8 to our python scripts.
My editor likes to pep8 as I edit, and I'm tired of carefully not
committing those changes.

Acked-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17096>
2022-06-21 21:38:25 +00:00
Danylo Piliaiev 909e7aaf57 tu: Reset xfb_used at the end of a renderpass
Otherwise xfb_used could be true until the end of command buffer,
which is not what we intended it to be.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17162>
2022-06-21 21:15:10 +00:00
Emma Anholt 086faecbba turnip: Document some fields about resolves.
I noticed the unk12 pattern, and cwabbott and danylo had figured out some
more details.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17126>
2022-06-21 19:40:58 +00:00
Emma Anholt d4c664a670 ci: Terminate capture-devcoredump before tarring up artifacts.
Every few weeks we'd get a flake where the script noticed the devcore
right as we were wrapping up, and then tar would exit because the file it
was tarring changed underneath it.  Just kill devcores before we do that
-- even if we kill it while it's working, it's so rare that it probably
won't bother anyone.

Fixes: #5867
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16820>
2022-06-21 17:46:05 +00:00
Lionel Landwerlin efc398c722 vulkan/wsi: fix crash with debug names on swapchain
If you set a name of on a swapchain object, because the base object
struct has not been initialized with a VkDevice,
vk_object_base_finish() will segfault when trying to free the object
name.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: cb1e0db23e ("vulkan/wsi: Make wsi_swapchain inherit from vk_object_base")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17165>
2022-06-21 17:05:10 +00:00
Lionel Landwerlin 4f10eddf77 anv: fix index buffer emission
In the following case :

  vkCmdBindPipeline(compute_pipeline);
  vkCmdDispatch(...);
  vkCmdBindPipeline(graphics_pipeline);
  vkCmdBindIndexBuffer(buffer)
  vkCmdDraw(...);

We're emitting the 3DSTATE_INDEX_BUFFER instruction while the HW is
still in GPGPU mode, because we're dealing the pipeline selection to
vkCmdDraw().

Found while debugging Age Of Empire 4, HW is hung on
3DSTATE_INDEX_BUFFER instruction.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17153>
2022-06-21 16:24:10 +00:00
Timur Kristóf 21ea19d504 zink: Always enable depth clamping, make depth clipping independent.
Enabling depth clamping ensures that the Vulkan driver respects
the depth range that zink sets on viewport objects in zink_draw.

When depth clipping is required, use VK_EXT_depth_clip_enable to
enable that independently of depth clamping.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16929>
2022-06-21 15:44:54 +00:00
Timur Kristóf 82e08f6b1e zink: Enable the VK_EXT_depth_clip_enable extension.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16929>
2022-06-21 15:44:54 +00:00
Timur Kristóf 810135fb42 gallium/u_blitter: Fix depth.
Fix the transform to make sure it doesn't disturb the depth range
of the blitted image. Set the Z coordinates of the vertices
by hand instead of relying on the transform to do it.

This is a pre-requisite to Zink always enabling depth clamping.

Fixes: 26c6640835
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16929>
2022-06-21 15:44:54 +00:00
Sarah Walker ee491967c3 pvr: Update for firmware 1.17@6256262
Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17139>
2022-06-21 15:09:10 +00:00
Erik Faye-Lund ee9c3d2625 docs: set language to english
It seems recent versions of Sphinx has started issuing a warning when
language isn't set to a recognized value. Since we're building with
warnings as errors on CI, this causes issues for people.

We're writing English docs, so we should set this to English. I probably
confused this setting with the highlight_language setting or something
when I set this up initially.

Fixes: 00cd1346bf ("docs: use sphinx")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6711
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17159>
2022-06-21 13:54:28 +00:00
Danylo Piliaiev 48540caec9 tu: Disable sample counting for 3d blits during occlusion query
Per Vulkan spec only "Draw" commands should be counted towards
occlusion query.

Apparently RB_SAMPLE_COUNT_CONTROL::UNK0 bool controls whether
sample counting is enabled, so we could use it to disable
sample counting for 3d blits which are sometimes used for
clear/copy/blit/gmem-store/resolve operations.

Fixes GL CTS tests running through Zink:
 dEQP-GLES3.functional.occlusion_query.depth_clear
 dEQP-GLES3.functional.occlusion_query.depth_clear_stencil_clear
 dEQP-GLES3.functional.occlusion_query.scissor_depth_clear_stencil_clear
 dEQP-GLES3.functional.occlusion_query.scissor_stencil_clear
 dEQP-GLES3.functional.occlusion_query.stencil_clear

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6559

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17138>
2022-06-21 13:13:36 +00:00
Gert Wollny 0c3fae4e6e virgl: Don't let ntt optimize the register allocation
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15995>
2022-06-21 11:24:09 +00:00
Martin Roukala (né Peres) 677a42378b ci/radv: add a missing flake
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
2022-06-21 13:11:05 +03:00
Martin Roukala (né Peres) f86e12743c ci/radv: move a test from the fail list to the flake list
The test was misidentified as a "fail", when it actually has a very
high failure rate (>95%). The test happened to pass twice within the
last week, so let's mark this test as a flake.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
2022-06-21 13:10:51 +03:00
Boris Brezillon d232f5a026 dzn: Fix the 2DMSArray case in dzn_image_get_dsv_desc()
Texture2DMSArray element is not initialized, making 2DMSArray DS
views buggy.

Reported-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17158>
2022-06-21 08:39:40 +00:00
Samuel Pitoiset 6cab999d6a radv,aco: rename radv_prolog_binary/radv_shader_prolog to shader_part
The same structures and functions will be re-used for PS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17084>
2022-06-21 08:04:50 +00:00
Christian Gmeiner 5cce02325c ir3: Create at least one thread for async shader compile
On a single core CPU system we end with num_threads being 0 and we do
_NOT_ create any async compile threads in util_queue_init(..).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17124>
2022-06-21 07:18:56 +00:00
Christian Gmeiner 3196bde941 freedreno: Wait for async compile jobs to finish
initial_variants_synchronous(..) allows initial shader variant
compilation asynchronously if debug.debug_message == NULL. If the
debug callback gets changed it seems like a good idea to wait until
all async shader compiles are done.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17124>
2022-06-21 07:18:56 +00:00
Vinson Lee 081b1eeacd microsoft/compiler: Fix assert.
Fix defect reported by Coverity Scan.

Side effect in assertion (ASSERT_SIDE_EFFECT)
assignment_where_comparison_intended: Assignment var->type =
glsl_int_type() has a side effect. This code will work differently in a
non-debug build.

Fixes: afb64e10c1 ("microsoft/compiler: Move d3d12_fix_io_uint_type() to dxil_nir.c")
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17097>
2022-06-21 06:54:18 +00:00
Vinson Lee 2b87073133 radv: Remove unnecessary null check.
Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking subpass suggests that it may be null,
but it has already been dereferenced on all paths leading to the check.

Fixes: 779e09639b ("radv: configure DB_Z_INFO.NUM_SAMPLES correctly on GFX11")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17100>
2022-06-21 04:00:46 +00:00
David Heidelberg 9cf3608952 ci: Uprev apitrace to 790380e05854
Better context error reporting, fix crash for replaying PlagueIncEvolved

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17136>
2022-06-20 21:51:28 +02:00
Filip Gawin 6cbb19110b r300: prefer old not native swizzle in constant folding
r300 and r400 have strict rules with swizzles, so we
will need to convert swizzle back.

Operating on 0, 1, H in this case unnecessarily makes
rest of r300 overly complicated.
(also it's not currently able to handle this)

helps with:
deqp-gles2@functional@shaders@random@exponential@fragment@24

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17117>
2022-06-20 19:10:00 +00:00
Alyssa Rosenzweig b6a30b72ab panfrost: Implement provoking vertices on Valhall
Starting with Valhall, the provoking vertex state is specified per-framebuffer
(batch) instead of per-draw. We use the pan_tristate infrastructure to translate
between desktop OpenGL's per-draw semantics to Valhall's per-framebuffer
semantic. This is notably not required for GLES or Vulkan.

If the provoking vertex is unset when the tiler context is generated, it could
be set (incompatibly) later in the batch, and the tiler context's provoking
vertex field would no longer match the framebuffer's. That would violate a
hardware invariant. To ensure that doesn't happen, we make sure to set provoking
vertexes *before* generating the tiler context so it can't change after.

Fixes arb-provoking-vertex-render on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
2022-06-20 18:38:16 +00:00
Alyssa Rosenzweig 9cdd32257f panfrost: Add tristate_is_defined helper
This is useful to ensure that the tri-state has been set. It could be inlined,
but the tri-state structure is designed to be opaque so this matches better.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
2022-06-20 18:38:16 +00:00
Alyssa Rosenzweig 950d27f9bf panfrost: Fix batch state changes on Valhall
If we need to change batch state (currently just point coord origins), not only
do we need to flush the old batch, but also set the desired state on the new
batch. That second step was missing. Fix that so this mechanism works as
intended.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Fixes: 3641dfe436 ("panfrost: Flip point coords in hardware")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
2022-06-20 18:38:16 +00:00
Alyssa Rosenzweig e9190c45d5 panfrost: Disable QUADS on Valhall
Even with the fixes in the rest of the series, arb-provoking-vertex-render is
still failing on Valhall for a single subcase (involving QUADS). It seems likely
that QUADS support is broken on Valhall, given it's not used in any of the APIs
for which Arm ships drivers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
2022-06-20 18:38:16 +00:00
Marcin Ślusarz 008163f382 intel/compiler: vectorize task payload loads/stores
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17000>
2022-06-20 17:38:20 +00:00
Marcin Ślusarz 97b53ad759 nir/opt_load_store_vectorize: handle task payloads
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17000>
2022-06-20 17:38:20 +00:00
Karmjit Mahil fad7e858f2 pvr: Extend hard coding infra to allow per stage per device coding.
This commit extends the graphics hard coding infrastructure to
allow the independent hard coding of stages, i.e. hard code fragment
stage and vertex stage separately instead of having to hard code
everything.

It also extends the infrastructure to allow per device hard coding.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
2022-06-20 16:59:01 +00:00
Karmjit Mahil c6933cc9de pvr: Enable 33.15.11.3 (AXE-1-16M).
This commit adds 33.15.11.3 in the supported BVNCs and addresses
differences in the descriptor limits between devices so that the
physical device limit is accurate.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
2022-06-20 16:59:01 +00:00
Frank Binns 62cc9bba06 pvr: Add TI AM62 as a supported device.
The AM62 platform contains an IMG AXE-1-16M GPU.

Co-Authored-By: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
2022-06-20 16:59:01 +00:00
David Heidelberg 57ad38c2fc ci/freedreno: disable non-existing trace
Never existed in the repository.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17137>
2022-06-20 16:36:10 +00:00
Juan A. Suarez Romero c0626a6bd2 v3dv/ci: Update expected results
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17141>
2022-06-20 15:37:39 +00:00