Commit Graph

56917 Commits

Author SHA1 Message Date
Kenneth Graunke bbf86712f8 i965: Add #defines for the pipeline statistics counter registers.
These come from the Ivybridge PRM, Volume 1, Part 3.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-05-20 13:03:18 -07:00
Kenneth Graunke e32cd5ffbb i965: Rely on hardware contexts for query objects on Gen6+.
Hardware contexts greatly simplify the query object code.  The pipeline
statistics counters get saved and restored with the context, which means
that we don't need to worry about other workloads polluting them.

This means that we can simply write a single pair of values (one at
BeginQuery and one at EndQuery) rather than a series of pairs.  This
also means we don't need to worry about the BO getting full.  We also
don't need to delay BO allocation and starting snapshot until the first
draw.

The generation split here is a little off: technically, Ironlake can also
support hardware contexts.  However, the kernel currently doesn't, and
even if it were to do so someday, we'd need to wait a while before
bumping the kernel requirement to take advantage of it.

v2: Incorporate Paul's feedback.
- Clarify which functions are Gen4/5-only via assertions and comments.
- Change how driver hook initialization happens.
- Update comments.
- Squash a bug fix from a later commit here where it belongs.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net> [v1]
Acked-by: Paul Berry <stereotype441@gmail.com>
2013-05-20 13:03:18 -07:00
Kenneth Graunke 72b1e440dd i965: Disable pixel statistics in BLORP.
BLORP is used for operations like glClear, glCopyTexImage, and
glBlitFramebuffer which aren't supposed to contribute fragments toward
occlusion queries.

This prevents Piglit tests from breaking in the next commit.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-05-20 13:03:17 -07:00
Kenneth Graunke 92d2f5acfa i965: Require hardware contexts (and thus Kernel 3.6) on Gen6+.
Hardware contexts are necessary to reasonably support OpenGL 3.2.
In particular, we currently maintain software counters for transform
feedback buffer offsets and counters, which relies on knowing the number
of primitives generated.  Geometry shaders violate that assumption.

At the time of writing, Debian has moved to Kernel 3.8, which means most
people probably have a newer kernel by now.  It's also worth noting that
this patch won't land until Mesa 10 which is currently targeted for
September.  By that point, even more people will have a newer kernel.

Also, don't bother trying to allocate contexts on pre-Gen6, as it
currently will always fail, and if this changes in the future, we'll
need to reevaluate our hw_ctx/gen checks.

This patch leaves the code for flagging BRW_NEW_CONTEXT on new
batchbuffers if hw_ctx == NULL since that still occurs pre-Gen6.

Also remove the Gen7+ check for kernel 3.3, since it's now redundant.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-05-20 13:03:17 -07:00
Kenneth Graunke 50e60bf8da i965: Bump kernel requirement to 3.3 on Ivybridge.
Kernel 3.3 introduced the SOL reset execbuf parameter, needed for GL 3.0
on Ivybridge.  Bumping the requirement will give an obvious error
message rather than simply reporting GL 2.1.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2013-05-20 13:03:17 -07:00
Vincent Lejeune 9fd7ea786c r600g/llvm: fix cubemap lod/bias 2013-05-20 20:23:19 +02:00
Vincent Lejeune 9a95fb1605 r600g/llvm: Fix texelFetchOffset-2D 2013-05-20 20:23:14 +02:00
Vincent Lejeune 32c9cbb38f r600g/llvm: Fix cubearray textureSize 2013-05-20 20:23:09 +02:00
Vincent Lejeune 9c2943601e r600g/llvm: Factorize code loading from const buffer. 2013-05-20 20:23:04 +02:00
Kenneth Graunke 01b79b2e3b i965: Add cases for ir_triop_vector_insert that assert.
brw_link_shader() unconditionally calls lower_vector_insert() with true
as the second parameter.  This means that both constant and variable
indexed expressions will get lowered, so we should never see this in the
backend.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-05-20 10:19:48 -07:00
Kenneth Graunke e1e8876797 i965: Add cases for ir_binop_vector_extract that assert.
do_vec_index_to_swizzle() should remove any vector extract operations
with a constant index.  It's unconditionally called from
do_common_optimization().

do_vec_index_to_cond_assign() should remove the rest, and it is
unconditionally called from brw_link_shader().  This means that we
should never see ir_binop_vector_extract in the backend.

Silences compiler warnings.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2013-05-20 10:19:30 -07:00
Roland Scheidegger f6beb4c6b6 llvmpipe: enable z32s8x24 format
Now that we can handle it both for sampling and as depth/stencil enable it.
Passes nearly all additional piglit tests which are now performed, with two
exceptions (one being a framebuffer blit which fails for all other formats
including stencil too as we don't support stencil blits, the other reporting
a unexpected GL error so doesn't look to be llvmpipe's fault).
2013-05-18 00:32:45 +02:00
Roland Scheidegger 070a9afb54 llvmpipe: handle z32s8x24 depth/stencil format
We need to split up the depth and stencil values in this case, and there's
some new logic required to handle float depth and stencil simultaneously.
Also make sure we get the 64bit zs clear values and masks propagated
correctly.
2013-05-18 00:32:33 +02:00
Roland Scheidegger f3ad716e8f llvmpipe: get rid of unused tiled/linear logic
We do rendering to linear color buffers for quite some time, and since
switching to linear depth buffers all the tiled/linear logic was unused.
So get rid of (most) of it - there's still some LAYOUT_NONE things and
late allocation of resources which probably could be simplified.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-18 00:32:27 +02:00
Roland Scheidegger 87978518e9 llvmpipe: fix bogus handling of first_layer when setting up texture sampling
The code avoided first_layer parameter in the sampler interface (and needing
to do another calculation at runtime) by fixing up the base texture pointer
instead. Unfortunately, this didn't actually work as we have mip-first
texture layout so fixing up the base ptr by a fixed amount is very wrong if
there are mipmaps present. The wrong offsets caused misrendering and crashes.
Fix this by just adjusting the individual mip level offsets instead.
Spotted by Jose.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-18 00:32:18 +02:00
Roland Scheidegger d7e811c0b0 gallivm: handle z32s8x24 format for sampling
Since we can only sample either depth or stencil but not both only load
the required bits which makes things a bit easier (it requires special
handling since the format doesn't fit into 32bit).
The logic for deciding if depth or stencil should be sampled is a bit odd,
but seems to be what other drivers and statetrackers do: if it's a format with
both depth and stencil (or just with depth) then sample depth, for sampling
stencil a sampler view format with only stencil is required.
Also while here fix up stencil sampling for other formats as well, though
this isn't supported by mesa (ARB_stencil_texturing), and while blits would
use it they don't work neither since they'd also need stencil export.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2013-05-18 00:31:49 +02:00
Roland Scheidegger 0346e9b3bb st/mesa: fix weird UCMP opcode use for bool ubo load
I don't know what this code was trying to do but whatever it was it couldn't
have worked since negation of integer boolean inputs while not specified as
outright illegal (not yet at least) won't do anything since it doesn't affect
the result of comparison with zero at all. In fact it looks like the whole
instruction can just be omitted.

Reviewed-by: Marek Olšák <maraeo@gmail.com>
2013-05-18 00:31:49 +02:00
Eric Anholt a5b0452400 mesa: Make FinishRenderTexture just take the renderbuffer being finished.
Now that the rb has a reference to the teximage, we didn't need anything
else out of the attachment.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-17 13:04:05 -07:00
Eric Anholt e98c39c109 mesa: Track the TexImage being rendered to in the gl_renderbuffer.
We keep having to pass the attachments around with our gl_renderbuffers
because that's the only way to find what the gl_renderbuffer actually
refers to.  This is a step toward removing that (though drivers still need
the Zoffset as well).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-17 13:04:05 -07:00
Eric Anholt 7b085d1bfa radeon: Remove dead radeon_wrap_texture().
I should have killed this in my previous cleanup.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-17 13:04:04 -07:00
Eric Anholt c810e67c55 mesa: Make gl_renderbuffers backed by EGL images use FinishRenderTexture.
This is the opportunity that radeon and intel drivers rely on for flushing
render targets that may get reused as textures.  Before EGL, that only
happened for GL_TEXTURE attachments.

Fixes piglits:
KHR_gl_renderbuffer_image/renderbuffer-texture
OES_EGL_image/renderbuffer-texture

NOTE: This is a candidate for the 9.1 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-17 13:04:04 -07:00
José Fonseca 6166ffeaf7 gallivm: Eliminate 8.8 fixed point intermediates from AoS sampling path.
This change was meant as a stepping stone to use PMADDUBSW SSSE3
instruction, but actually this refactoring by itself yields a 10%
speedup on texture intensive shaders (e.g, Google Earth's ocean water
w/o S3TC on a Ivy Bridge machine), while giving yielding exactly the
same results, whereas PMADDUBSW only gave an extra 5%, at the expense of
2bits of precision in the interpolation.

I belive that the speedup of this change comes from the reduced register
pressure (as 8.8 fixed point intermediates take twice the space of 8bit
unorm).

Also, not dealing with 8.8 simplifies lp_bld_sample_aos.c code
substantially -- it's no longer necessary to have code duplicated for
low and high register halfs.

Note about lp_build_sample_mipmap(): the path for num_quads > 1 is never
executed (as it is faster on AVX to split the 256bit wide texture
computation into two 128bit chunks, in order to leverage integer
opcodes).  This path might be useful in the future, so in order to
verify this change did not break that path I had to apply this change:

  @@ -1662,11 +1662,11 @@ lp_build_sample_soa(struct gallivm_state *gallivm,
         /*
          * we only try 8-wide sampling with soa as it appears to
          * be a loss with aos with AVX (but it should work).
          * (It should be faster if we'd support avx2)
          */
  -      if (num_quads == 1 || !use_aos) {
  +      if (/* num_quads == 1 || ! */ use_aos) {

            if (num_quads > 1) {
               if (mip_filter == PIPE_TEX_MIPFILTER_NONE) {
                  LLVMValueRef index0 = lp_build_const_int32(gallivm, 0);
                  /*

and then run texfilt mesademo:

  LP_NATIVE_VECTOR_WIDTH=256 ./texfilt

Ran whole piglit without regressions.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-17 20:23:00 +01:00
José Fonseca 5aaa4bafe0 gallivm: Add and use lp_build_lerp_3d.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2013-05-17 20:22:50 +01:00
Tom Stellard e230d9debb radeon/llvm: Run standard optimization passes on conpute shader modules
The SROA and function inliner passes are espically important, because
they optimize away unsupported features: functions and indirect
private memory access.
2013-05-17 07:38:01 -07:00
Kenneth Graunke ccb041fe8e intel: Don't spam "intelReadPixels: fallback to swrast" in non-PBO case.
When an application is using PBOs, we attempt to use the BLT engine to
perform ReadPixels.  If that fails due to some restrictions, it's useful
to raise a performance warning.

In the non-PBO case, we always use a CPU mapping since getting the data
into client memory requires a CPU-side copy.  This is a very common case,
so raising a performance warning is annoying.  In particular, apitrace's
image dumping code hits this path, causing it to print hundreds of
thousands of performance warnings via ARB_debug_output.  This tends to
obscure actual errors or other important messages.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-05-16 22:35:01 -07:00
Paul Berry 46ea804107 intel: Do a depth resolve before copying images between miptrees.
When intel_finalize_mipmap_tree() calls intel_miptree_copy_teximage()
to reassemble a depth miptree that has been broken apart into pieces
(to deal with misalignment of levels/layers within the miptree), it
just copies the depth data, not the HiZ data.  This is reasonable,
since the alignment restrictions of HiZ are a large part of the reason
why the miptree had to be broken apart in the first place.  However,
in order for the depth copy to be sufficient, we need to do a depth
resolve first, to make sure any deferred depth writes that are in the
HiZ buffer get performed.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=64662 and
https://bugs.freedesktop.org/show_bug.cgi?id=64659.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
2013-05-16 14:42:54 -07:00
Niels Ole Salscheider 7e17e72cb7 r600g: fixup for MSAA texture support checking
Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
2013-05-16 12:03:47 -07:00
José Fonseca 4f518e1738 llvmpipe: Temporary workaround to prevent segfault on array textures. 2013-05-16 15:14:10 +01:00
José Fonseca cb9913cdab gallivm: Support pointers in lp_build_print_value().
Trivial.
2013-05-16 15:14:10 +01:00
Chia-I Wu 435aea6f32 ilo: emit 3DSTATE_STENCIL_BUFFER on GEN7+
Whether HiZ is enalbed or not, separate stencil is supported and enforced on
GEN7+.  Now that we support separate stencil resources, we know how to emit
3DSTATE_STENCIL_BUFFER.
2013-05-16 18:33:59 +08:00
Chia-I Wu 6b894e6900 ilo: add support for stencil resources on GEN7+
For allocations, we need to support stencil-only and separate stencil
resources.  For mapping, we need to support software tiling and
packing/unpacking for separate stencil resources.
2013-05-16 18:20:17 +08:00
Chia-I Wu 5c9b69d259 winsys/intel: test for and expose address swizzling
Without knowing whether addresses are swizzled or not, we cannot manipulate a
tiled surface in CPU.
2013-05-16 11:24:59 +08:00
Marek Olšák 639d0f73c1 st/mesa: handle texture_from_pixmap and other surface-based textures correctly
There were 2 issues with it:
1) The texture format which should be used for texturing was only set
   in gl_texture_image::TexFormat, which wasn't used for sampler views.
2) Textures are sometimes reallocated under some circumstances
   in st_finalize_texture, which is unacceptable if the texture comes
   from a window system.

The issues are resolved as follows:
1) If surface_based is true (texture_from_pixmap, etc.), store the format
   in a new variable st_texture_object::surface_format.
2) Don't reallocate a surface-based texture in st_finalize_texture.

Also don't use st_ChooseTextureFormat is st_context_teximage, because
the format is dictated by the caller.

This fixes the glx-tfp piglit test.

Reviewed-by: Adam Jackson <ajax@redhat.com>
2013-05-15 20:22:48 +02:00
Marek Olšák 5a3fac4d26 r600g: cleanup MSAA texture support checking
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-15 20:20:32 +02:00
Marek Olšák 61c995bc47 r600g: rewrite FMASK allocation, fix FMASK texturing with 2 and 4 samples
This fixes and enables texturing with compressed MSAA colorbuffers
on Evergreen and Cayman. For the first time, multisample textures work
on Cayman.

This requires the libdrm flag RADEON_SURF_FMASK.

v2: require libdrm_radeon 2.4.45

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2013-05-15 20:19:45 +02:00
Eric Anholt 61506257f6 i965: Fill in brw_format_for_mesa_format for some non-rendering formats.
This should have no change on driver operation, but it means that when you
wonder why some format isn't supported natively, you can just look at the
table above, instead of wondering if maybe there's an appropriate entry in
the surface formats table that is already supported.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-15 09:43:46 -07:00
Eric Anholt 9db9bc3aa1 i965: Use native RGB_FLOAT16 support when available.
Previously we would expand it to RGBA_FLOAT16.  This format now comes out
as framebuffer incomplete, but it seems worth the memory savings if that's
what people are asking for (and GL3 does list it under "texture-only"
color formats)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-15 09:43:46 -07:00
Eric Anholt 645b610b62 intel: Add support for blitting 6 byte-per-pixel formats.
The next commit introduces what is apparently our first one, which tripped
over this in glReadPixels.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-15 09:43:45 -07:00
Eric Anholt 028c11e8e3 i965: Use the Mesa surface formats for float RGB surfaces.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-15 09:43:45 -07:00
Eric Anholt 2e057076a8 i965: Use the new XRGB UNORM formats.
This is a step on the way to removing some of our code for forcing alpha
to 1, but I want easy bisecting so I'll add groups of formats separately.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2013-05-15 09:43:45 -07:00
José Fonseca 2a43dfda95 draw: More defensive coding in DRAW_GET_IDX.
Doesn't make a difference ATM, but just in case.
2013-05-15 16:59:28 +01:00
José Fonseca 1883e1d3e9 draw: Fix vsplit regression when the ib can be used directly.
`ib` no longer is offseted by `istart`.

Trivial.
2013-05-15 16:57:44 +01:00
Chris Forbes 53a5f11f0d mesa: Stop clamping stencil reference value at specification time
All drivers now clamp this to the appropriate range for the bound
stencil buffer when emitting stencil state.

NOTE: This is a candidate for stable branches.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-15 22:04:53 +12:00
Chris Forbes 978f91b829 swrast: Use accessor for stencil reference values
NOTE: This is a candidate for stable branches.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-15 22:04:53 +12:00
Chris Forbes db8a84de87 st: Use accessor for stencil reference values
NOTE: This is a candidate for stable branches.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-15 22:04:53 +12:00
Chris Forbes c411f40cba radeon: Use accessor for stencil reference values
V2: Drop spurious mask with 0xff.

NOTE: This is a candidate for stable branches.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-15 22:04:34 +12:00
Chris Forbes 7bbe9b78ae nouveau: Use accessor for stencil reference values
NOTE: This is a candidate for stable branches.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Acked-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-15 22:01:08 +12:00
Chris Forbes f819ec46d5 intel: Use accessor for stencil reference values
NOTE: This is a candidate for stable branches.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-15 22:01:06 +12:00
Chris Forbes 96a1bf1ba3 mesa: Use accessor for stencil reference values in glGet
NOTE: This is a candidate for stable branches.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-15 22:01:03 +12:00
Chris Forbes 38f65162af mesa: add accessor for effective stencil ref
Clamps the stencil reference value to the range representable in the
currently-bound draw framebuffer's stencil attachment.

V2: Add spec quote.

NOTE: This is a candidate for stable branches.

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2013-05-15 22:00:55 +12:00