Commit Graph

92005 Commits

Author SHA1 Message Date
Marek Olšák e24d094d70 gallium/u_threaded: drop and ignore all non-async debug callbacks
This is necessary to comply with OpenGL.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-15 13:01:33 +02:00
Marek Olšák 4c98afb241 gallium/radeon: add threaded context counter monitoring for HUD
"tc" will be initialized by the next commit.

v2: rename stuff according to v2 changes in u_threaded_context

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák 7166773f90 radeonsi: implement replace_buffer_storage for the threaded context
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák 04299f7e5d gallium/radeon: subclass and handle threaded_query
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák b40d8026fa gallium/radeon: subclass threaded_transfer
v2: use assert on rtransfer->b.staging

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák b4fc399c08 gallium/radeon: subclass threaded_resource
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák 93d549b2af gallium/radeon: handle other map buffer flags from the threaded context
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák e11f7e1d59 gallium/radeon: handle TC_TRANSFER_MAP_THREADED_UNSYNC
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák 8b5485957e gallium/radeon: unwrap a context if we get a wrapped one
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák 42fe45b451 gallium/radeon: require both WRITE and FLUSH_EXPLICIT in buffer_flush_region
spotted randomly.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák b8e552424e gallium/util: add threaded_context as a pipe_context wrapper
v2: - rename num_calls -> num_call_slots (for tc_call)
    - rename num_calls -> num_total_call_slots (for tc_batch)
    - rename num_offloaded/direct_calls -> num_offloaded/direct_slots
    - declare slot[0] instead of slot[1]
    - remove no-op leftover code from tc_draw_vbo
    - use tc_set_resource_reference to fill threaded_transfer
    - fix map flags for sparse buffers
    - cosmetic changes

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák dca19b1d42 gallium/u_upload: add u_upload_clone
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák 8559fa505d gallium: add flag PIPE_CONTEXT_PREFER_THREADED
State trackers can set this to tell the driver when u_threaded_context is
desirable.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2017-05-15 13:01:33 +02:00
Marek Olšák 7622181cad radeonsi/gfx9: add support for Raven
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-15 13:00:26 +02:00
Marek Olšák efdb378c36 amd/addrlib: import Raven support
Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-05-15 13:00:26 +02:00
Eric Anholt c98f03c6eb renderonly: Initialize fields of struct winsys_handle.
vc4 was rejecting renderonly's import, because the offset field was
nonzero.

Fixes: 848b49b288 ("gallium: add renderonly library")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2017-05-15 06:38:45 +02:00
Rob Clark 12f9fa564a Revert "freedreno: use bypass if only clears"
Causing issues with stk on a4xx.. still probably a good idea, but seems
some debugging is needed first.

This reverts commit 3ab072d3c8.
2017-05-14 15:10:08 -04:00
Rob Clark e4ad86952a freedreno: fix crash when flush() but no rendering
If we haven't created a batch, just bail in pipe->flush(), since there
is nothing to do.

Fixes crash in warsow, which creates a whole bunch of contexts used for
nothing but texture uploads.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-14 15:10:08 -04:00
Rob Clark 06a51fb4e5 freedreno: fix indexbuffer upload
My fault for not having time to test Marek's patches while they were on
list.

Fixes: 330d0607 ("gallium: remove pipe_index_buffer and set_index_buffer")
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-14 15:10:08 -04:00
Bas Nieuwenhuizen d4e4c36c7c radv: Save descriptor set even if vertex buffers are not saved.
Totally independent.

Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Fixes: 0e6d532d32 "radv/meta: add support for save/restore meta without vertex data."
2017-05-13 23:05:25 +02:00
Rob Clark 8efaae3e19 freedreno/a5xx: hw binning support
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-13 13:25:26 -04:00
Rob Clark c61417e8be freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-13 13:12:36 -04:00
Rob Clark 3ab072d3c8 freedreno: use bypass if only clears
Some things trigger batches that only contain a clear (like glmark2
startup).  No point to use GMEM for this.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-05-13 13:12:36 -04:00
Pierre Moreau 840f6beb81 nv50/ir: Report wrong prog types using proper var
Coverity caught the use of the uninitialised variable `type`.
However, it was `info->type`, which is initialised, which was meant to
be used.

CID: 1406000
Reported-by: Ilia Mirkin <imirkin@alum.mit.edu>
Fixes: b490ca9a38 ("nv50/ir: Fail if encountering unknown shader type")
Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-05-13 16:26:09 +02:00
Timothy Arceri 812ff333bf mesa: fix KHR_no_error SSO support
Fixes: 00c5119a5e ("mesa: add KHR_no_error support for glUseProgramStages()")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-05-13 20:56:34 +10:00
Andres Gomez 752a6384af docs: update calendar, add news item and link release notes for 17.0.6
Signed-off-by: Andres Gomez <agomez@igalia.com>
2017-05-13 02:20:32 +03:00
Andres Gomez 05e833dfda docs: add sha256 checksums for 17.0.6
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 6a680243fcef4509372941d5c4c50b82c3aaa8ed)
2017-05-13 02:16:11 +03:00
Andres Gomez a2ca97eaca docs: add release notes for 17.0.6
Signed-off-by: Andres Gomez <agomez@igalia.com>
(cherry picked from commit 08abf3a2a2ca8733fb75277d41f2196fe899f129)
2017-05-13 02:16:08 +03:00
Andres Gomez b7af0ddfef bin/get-fixes-pick-list.sh: bring back the warning
We warn again if there are more than one line with the "fixes:" tag.

The warning is silenced when the commit has already landed or each
fixes tag reference a commit that is in branch.

v2:
 - Warn if any of the fixes tags has not landed (Emil)

v3:
 - Remove unnecessary head command
 - Clarify commit message (Emil)
 - Skip already picked commits sooner (Emil)

Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-05-13 00:52:34 +03:00
Andres Gomez 0dead448dd docs: extend until the end of August
Completed the 17.1 cycle and added the beginning of the 17.2 one.

Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-05-13 00:00:41 +03:00
Andres Gomez 19db5072aa docs: update "Release manager" column
Cc: Emil Velikov <emil.velikov@collabora.com>
Cc: Juan A. Suarez Romero <jasuarez@igalia.com>
Signed-off-by: Andres Gomez <agomez@igalia.com>
Reviewed-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-05-13 00:00:34 +03:00
Nicolai Hähnle 5c92b1bf07 glsl: include image qualifiers when printing IR
v2:
- fix copy&paste errors noted by Samuel
- rebase

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-05-12 10:46:07 +02:00
Nicolai Hähnle a16ae77185 radeonsi: get rid of secondary input/output word
By keeping track of fewer generics, everything can fit into 64 bits.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-12 10:46:06 +02:00
Nicolai Hähnle 0dd8aa44b3 radeonsi: reduce the number of generics for shader IO unique indices
This is a high as possible while still allowing to merge the bitfields
with the next commit.

For OpenGL, 32 would be sufficient. Nine apparently uses (much!) higher
indices than. Indices that are out of bound don't hurt for VS-PS
pipelines, except that the VS output kill optimization is not applied.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-12 10:46:06 +02:00
Nicolai Hähnle 90339fabd7 radeonsi: at most 8 sets of texture coordinates are supported
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-12 10:46:05 +02:00
Nicolai Hähnle cfe6e30f1b radeonsi: skip generic out/in indices without a shader IO index
OpenGL uses at most 32 generic outputs/inputs in any stage, and they always
have a shader IO index and therefore fit into the outputs_written/
inputs_read/kill_outputs fields.

However, Nine uses semantic indices more liberally. We support that
in VS-PS pipelines, except that the optimization of killing outputs
must be skipped.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-12 10:46:05 +02:00
Nicolai Hähnle 7091fe887b radeonsi: use SI_MAX_IO_GENERIC instead of magic values
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-05-12 10:46:04 +02:00
Samuel Pitoiset 4aa4e17f4e glsl: order indices for images inside a struct array
ARB_bindless_texture allows images to be declared inside
structures. This is similar to samplers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-05-12 10:30:37 +02:00
Samuel Pitoiset f87416f62d glsl: add parcel_out_uniform_storage::set_opaque_indices() helper
In order to sort indices for images inside a struct array we
need to do something similar to samplers.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-05-12 10:30:30 +02:00
Rafael Antognolli 70251e3631 i965: Port 3DSTATE_VF_TOPOLOGY on gen8+ to genxml.
With this last state ported, we can get rid of gen8_draw_upload.c.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-05-11 21:27:38 -07:00
Rafael Antognolli 5bbcbabd86 i965: Port 3DSTATE_INDEX_BUFFER to genxml.
Also make the brw_get_index_type() function not shift its return, since that
is genxml's job now.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-05-11 21:27:38 -07:00
Rafael Antognolli 71bfb44005 i965: Port brw_cs_state tracked state to genxml.
Emit the respective commands using genxml code.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-05-11 21:27:38 -07:00
Rafael Antognolli d9b4a81672 genxml: Add alias for MOCS.
Use an alias for this field on 3DSTATE_INDEX_BUFFER on gen6+, so we can set
the same value as the defines.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-05-11 21:27:38 -07:00
Rafael Antognolli c93b17be19 i965/genxml: Mostly style fixes for emit_vertices code.
Several issues were caught on review after the original patch landed.
This commit fixes them.

v2:
   - Fix padding (Topi)
   - Remove .DestinationElementOffset change from this patch (Topi)

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-05-11 21:27:38 -07:00
Glenn Kennard fa105214d3 r600g: Add defines for per-shader engine settings
Acked-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
2017-05-12 12:20:04 +10:00
Glenn Kennard 123ae18f29 r600g: Add instruction encoding defines for MEM_RD
Acked-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
2017-05-12 12:19:55 +10:00
Glenn Kennard 8260c4648a r600g: Add scratch ring register defines
Acked-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Glenn Kennard <glenn.kennard@gmail.com>
2017-05-12 12:19:46 +10:00
Kenneth Graunke b361af6bbe i965: Drop brw_context::viewport_transform_enable.
This was used by the meta fast clear code.  Now that we've switched
back to BLORP, it's always true.

We might want it back when we add a RECTLIST extension to GL, but
that's someday in the future...

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2017-05-11 16:53:28 -07:00
Kenneth Graunke f790d6e0b4 i965: Port Gen4-5 VS_STATE to genxml.
It's actually not that much code.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-05-11 16:52:59 -07:00
Kenneth Graunke 4933c3d16e i965: Change GEN_GEN < 7 to GEN_GEN == 6 in 3DSTATE_VS code.
This whole code is surrounded in #if GEN_GEN >= 6, and this code only
applies on Sandybridge.  So, use GEN_GEN == 6 to reduce the delta in
the next patch, when we add Gen4-5 support.

Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-05-11 16:34:04 -07:00