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amd/addrlib: import Raven support 

Cc: 17.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-02-27 22:25:43 +01:00
parent c98f03c6eb
commit efdb378c36
3 changed files with 72 additions and 3 deletions
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57
src/amd/addrlib/gfx9/gfx9addrlib.cpp
View File

@ -1193,6 +1193,20 @@ ChipFamily Gfx9Lib::HwlConvertChipFamily(
m_settings.depthPipeXorDisable = 1;
break;
case FAMILY_RV:
m_settings.isArcticIsland = 1;
m_settings.isRaven = ASICREV_IS_RAVEN(uChipRevision);
if (m_settings.isRaven)
{
m_settings.isDcn1 = 1;
}
m_settings.metaBaseAlignFix = 1;
m_settings.depthPipeXorDisable = 1;
break;
default:
ADDR_ASSERT(!"This should be a Fusion");
break;
@ -2734,6 +2748,35 @@ BOOL_32 Gfx9Lib::IsValidDisplaySwizzleMode(
break;
}
}
else if (m_settings.isDcn1)
{
switch (swizzleMode)
{
case ADDR_SW_4KB_D:
case ADDR_SW_64KB_D:
case ADDR_SW_VAR_D:
case ADDR_SW_64KB_D_T:
case ADDR_SW_4KB_D_X:
case ADDR_SW_64KB_D_X:
case ADDR_SW_VAR_D_X:
support = (pIn->bpp == 64);
break;
case ADDR_SW_LINEAR:
case ADDR_SW_4KB_S:
case ADDR_SW_64KB_S:
case ADDR_SW_VAR_S:
case ADDR_SW_64KB_S_T:
case ADDR_SW_4KB_S_X:
case ADDR_SW_64KB_S_X:
case ADDR_SW_VAR_S_X:
support = (pIn->bpp <= 64);
break;
default:
break;
}
}
else
{
ADDR_NOT_IMPLEMENTED();
@ -3195,6 +3238,20 @@ ADDR_E_RETURNCODE Gfx9Lib::HwlGetPreferredSurfaceSetting(
// DCE12 does not support display surface to be _T swizzle mode
prtXor = FALSE;
}
else if (m_settings.isDcn1)
{
// _R is not supported by Dcn1
if (pIn->bpp == 64)
{
swType = ADDR_SW_D;
}
else
{
swType = ADDR_SW_S;
}
blockSet.micro = FALSE;
}
else
{
ADDR_NOT_IMPLEMENTED();

8
src/amd/addrlib/gfx9/gfx9addrlib.h
View File

@ -54,11 +54,13 @@ struct Gfx9ChipSettings
// Asic/Generation name
UINT_32 isArcticIsland : 1;
UINT_32 isVega10 : 1;
UINT_32 reserved0 : 30;
UINT_32 isRaven : 1;
UINT_32 reserved0 : 29;
// Display engine IP version name
UINT_32 isDce12 : 1;
UINT_32 reserved1 : 31;
UINT_32 isDcn1 : 1;
UINT_32 reserved1 : 29;
// Misc configuration bits
UINT_32 metaBaseAlignFix : 1;
@ -201,7 +203,7 @@ protected:
if (IsXor(swizzleMode))
{
if (m_settings.isVega10)
if (m_settings.isVega10 || m_settings.isRaven)
{
baseAlign = GetBlockSize(swizzleMode);
}

10
src/amd/common/amdgpu_id.h
View File

@ -49,6 +49,7 @@ enum {
FAMILY_CZ,
FAMILY_PI,
FAMILY_AI,
FAMILY_RV,
FAMILY_LAST,
};
@ -185,4 +186,13 @@ enum {
#define ASICREV_IS_VEGA10_P(eChipRev) \
((eChipRev) >= AI_VEGA10_P_A0 && (eChipRev) < AI_UNKNOWN)
/* RV specific rev IDs */
enum {
RAVEN_A0 = 0x01,
RAVEN_UNKNOWN = 0xFF
};
#define ASICREV_IS_RAVEN(eChipRev) \
((eChipRev) >= RAVEN_A0 && (eChipRev) < RAVEN_UNKNOWN)
#endif /* AMDGPU_ID_H */