Commit Graph

125521 Commits

Author SHA1 Message Date
Connor Abbott 1288613f1c freedreno/a6xx: use firstIndex field
Analogous to the turnip change.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
2020-06-26 10:05:24 +00:00
Connor Abbott ba5e1c5310 tu: Pass firstIndex directly to CP_DRAW_INDX_OFFSET
Saves some minor overhead, cleans things up a bit, and removes one more
unknown. We now program the internal registers in the same way between
direct/indirect draws.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
2020-06-26 10:05:24 +00:00
Connor Abbott 259d07a2ff freedreno/registers: Label firstIndex field in CP_DRAW_INDX_OFFSET
Based on comparing the implementations of CP_DRAW_INDX_OFFSET and
CP_DRAW_INDIRECT, this is what this field is for.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
2020-06-26 10:05:24 +00:00
Connor Abbott a32fb2f9d0 freedreno: On a5xx+ INDX_SIZE is MAX_INDICES
This was already done correctly for the indirect variants, and turnip
was setting the correct value, but it seems freedreno missed the change
in the non-indirect variant. Also, fix a misspelling of "indices" and
add a type to INDX_SIZE.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5644>
2020-06-26 10:05:24 +00:00
Connor Abbott 1dd24bf27b freedreno: Share constlen between different stages properly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Connor Abbott d9dd989d2a freedreno: Refactor ir3_cache shader compilation
Use an array, which makes it more like turnip and makes implementing the
const limits easier.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Connor Abbott 8ad65609da tu: Share constlen between different stages properly
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Connor Abbott 48b1602b50 ir3: Add ir3_trim_constlen()
This provides the policy for how to handle reducing constlen for some
stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Connor Abbott 9edff0cfd4 ir3: Support variants with different constlen's
This provides the mechanism for compiling variants with a reduced
constlen. The next patch provides the policy for choosing which to
reduce.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Connor Abbott 4554b946c3 ir3: Include ir3_compiler from ir3_shader
I wanted to access the ir3_compiler from a small helper inside
ir3_shader.h, which currently isn't possible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Connor Abbott 2841bb1fac ir3, freedreno: Round up constlen earlier
Prevents problems when calculating whether we overflow the shared limit.
Note that on a6xx, the macros handle the assert for us.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5607>
2020-06-26 09:34:33 +00:00
Iago Toral Quiroga 4845f184d7 v3d/compiler: don't rewrite unused temporaries to point to NOP register
This was assuming that unused temporaries are written but never read,
since the NOP register can only be used as a destination register,
but we can end up here also for temporaries that are read once but
never written.

This was found with a graphicsfuzz test that has a switch with
cases that have unreachable discards. In that test, NIR genrates
code like this:

decl_reg vec3 32 r19
...
r20 = mov r19.z
r21 = mov r19.y
r22 = mov r19.x

Where r19.xyz would generate 3 temporary registers that are read but
never written, so we would rewrite them to point to the NOP register
as QPU instruction sources, which is not allowed and would hit an
assert that expect magic reads to be from [r0,r5] only.

Fixes:
dEQP-VK.graphicsfuzz.unreachable-switch-case-with-discards

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5645>
2020-06-26 08:57:32 +00:00
Neil Roberts 3b1c511b09 v3d: Use stvpmd for non-uniform offsets in GS
The offset for the VPM write for storing outputs from the geometry
shader isn’t necessarily uniform across all the lanes. This can happen
if some of the lanes don’t emit some of the vertices. In that case the
offset for the subsequent vertices will be different in each lane. In
that case we need to use the stvpmd instruction instead of stvpmv
because it will scatter the values out.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3150

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5621>
2020-06-26 09:36:15 +02:00
Neil Roberts dab8a9169c v3d: Add missing macro for stvpmd instruction
stvpmd is like stvpmv but it scatters the output. It can be used with
non-dynamically uniform offsets.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5621>
2020-06-26 09:36:15 +02:00
Marek Olšák 71794567f9 radeonsi: remove tabs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 0cdec11d95 radeonsi: clear per-context buffers at the end of si_create_context
We don't want any packets before CONTEXT_CONTROL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák da78d50bc8 radeonsi: make si_pm4_cmd_begin/end static and simplify all usages
There is no longer the confusing trailing si_pm4_cmd_end call.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 7b2a0f880b radeonsi: disallow adding BOs into si_pm4_state except 1 shader BO per state
The si_shader pointer is already there, so use it and remove the array
of BOs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 3b1e42d2c2 radeonsi: make wait_mem_scratch unmappable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 428360662f radeonsi: don't add the tess ring buffers into the cs_preamble state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 1c1d34a67a radeonsi: rename init_config states to cs_preamble states
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák bbc0a2d51d radeonsi: don't add the border color buffer into the init_config state
We might have to replace init_config for preemption.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák c7680625c3 ac,winsys/amdgpu: align IBs the same as the kernel
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Marek Olšák 556f4458fe amd: add proper definitions for NOP packets
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603>
2020-06-26 07:02:57 +00:00
Samuel Pitoiset 276e6d7bbc gitlab-ci: attach the Fossilize log file as artifact on failure
It might be help.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>
2020-06-26 06:45:23 +00:00
Samuel Pitoiset 4954df417c gitlab-ci: append Fossilize stdout/stderr to a file to reduce spam
Fossilize is really verbose and it's easy to reach the buffer
limit in GitLab CI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>
2020-06-26 06:45:23 +00:00
Samuel Pitoiset b24b415013 gitlab-ci: set the number of Fossilize threads to 4
The shared runners are set up for concurrent jobs ~= CPUs / 4 (x86)
or 8 (ARM).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5627>
2020-06-26 06:45:23 +00:00
Icecream95 be5d06106f panfrost: Only copy resources when they are in a pending batch
Fixes a performance regression in alacritty, and rendering is still
fine in GLQuake ports.

Fixes: 361fb38662 ("panfrost: Copy resources when mapping to avoid waiting for readers")
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5642>
2020-06-26 06:32:34 +00:00
Rafael Antognolli 66df2ffa36 anv: Align "used" attribute to 64 bits.
This is a 64 bits value that might not be aligned on 32 bit plaforms.
Since it's used with atomics, let's make sure it gets properly aligned
to avoid any potential performance loss.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>
2020-06-25 22:11:36 -07:00
Rafael Antognolli 293221ddda iris: Align last_seqnos to 64 bits.
last_seqnos is used in atomic operations. Specially on 32 bit platorms,
it tends to be slower if it's not aligned to 64 bits (see
cdc331c6f9). This fixes a small regression
on Bioshock.

Fixes: aba3aed96e ("iris: fix export of GEM handles")
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5637>
2020-06-25 22:11:08 -07:00
Eric Anholt 2fd746e98e ci: Remove a stray "always" on the freedreno traces job.
This was making it so that the CI would error if the set of files modified
or the pipeline involvd meant the jobs we depend on weren't enabled.  It
was just some misplaced debug leftovers of mine.

Fixes: b88c46fa11 ("ci: Add a freedreno a630 tracie run.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5653>
2020-06-25 23:45:48 +00:00
Eric Anholt 50e20cb036 freedreno/a6xx: Add support for polygon fill mode (as long as front==back).
Unlike a4xx, we don't seem to have separate back vs front fields any more.
Still, this improves desktop GL conformance (and one of the traces in
traces-db).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
2020-06-25 13:46:30 -07:00
Eric Anholt 72c0522db2 turnip: Add support for polygon fill modes.
Passes the new tests in dEQP-VK.rasterization.culling.*

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
2020-06-25 13:46:30 -07:00
Eric Anholt daee177ca0 freedreno/a6xx: Define the register fields for polygon fill mode.
Produced by comparing the traces of:
dEQP-VK.rasterization.culling.front_triangles
dEQP-VK.rasterization.culling.front_triangles_point
dEQP-VK.rasterization.culling.front_triangles_line

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
2020-06-25 13:46:28 -07:00
Eric Anholt b88c46fa11 ci: Add a freedreno a630 tracie run.
This job runs in about one minute on the current set of traces, and has
successfully revealed some bugs in our current rendering.  Takes about 7
minutes currently.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
2020-06-25 17:33:28 +00:00
Eric Anholt b5f727afeb ci/tracie: Fix apitrace dump using "less" which isn't in the ARM rootfs.
You would get no output during the "find the last frame" step of the trace
replay.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
2020-06-25 17:33:28 +00:00
Eric Anholt 9f1412cf3e ci/tracie: Print the path if the trace isn't found.
I hit this a few times while setting up CI.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
2020-06-25 17:33:28 +00:00
Rohan Garg 7406d627c8 ci: Include trace replay support in ARM rootfses.
Builds the renderdoc and apitrace programs so we can replay GL traces on
DUTs.

[Separated out from 5472's commit that also enabled the jobs in LAVA,
dropped unnecessary python packages from arm_build, fixed up arm64_test
build, traces-db in baremetal, new commit message by anholt]

Signed-off-by: Rohan Garg <rohan.garg@collabora.com>
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
2020-06-25 17:33:28 +00:00
Eric Anholt acf9d8b75d ci/bare-metal: Don't include dev packages in arm*test.
We just need these to build our rootfs, clean them out afterwards.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
2020-06-25 17:33:28 +00:00
Eric Anholt 9079b53987 ci/bare-metal: Skip setting of unset variables at startup.
It's silly to be setting (and logging the setting of!) all the env vars we
*didn't* set in a job.

Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
2020-06-25 17:33:28 +00:00
Tomeu Vizoso 21b2dac793 ci: Move ARM rootfses to stable
We build in Debian buster but were currently testing in bullseye-based
ramdisks. This has started being a problem since Python 3.7 was removed
from bullseye.

[ Also bumped arm_test containers, by anholt ]

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
2020-06-25 17:33:28 +00:00
Tomeu Vizoso a04672a105 ci: Don't call renderdoc's ReplayController.Shutdown()
If we do, Renderdoc will call eglDestroyContext twice, causing crashes
within Mesa.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5433>
2020-06-25 17:33:28 +00:00
Jonathan Marek 62de79ac44 turnip: implement VK_KHR_shader_draw_parameters
Note: going by the blob, VFD_INDEX_OFFSET/FD_INSTANCE_START_OFFSET seem
completely unused by indirect draws, so this changes them to only be set
for non-indirect draws (and moves them to the vs_params draw state).

Passes dEQP-VK.draw.shader_draw_parameters.*

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5635>
2020-06-25 15:57:45 +00:00
Jonathan Marek 16a9e233da freedreno/ir3: add support for load_draw_id
This is part of adding VK_KHR_shader_draw_parameters for turnip.

IR3_DP_VTXID_BASE/IR3_DP_VTXCNT_MAX offsets are changed to match what
CP_DRAW_INDIRECT_MULTI requires.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5635>
2020-06-25 15:57:45 +00:00
Jonathan Marek 01799b3448 freedreno/registers: add CP_DRAW_INDIRECT_MULTI
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5635>
2020-06-25 15:57:45 +00:00
Samuel Pitoiset 7e98f2534c gitlab-ci: add a list of expected failures for RADV/ACO on NAVI14
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5647>
2020-06-25 14:15:49 +00:00
Daniel Schürmann 63e1e7209c radv: enable ACO by default
No more dragons have been seen, caution is still required...

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5445>
2020-06-25 15:16:30 +02:00
Daniel Schürmann db0afb3800 radv: change use_aco -> use_llvm
We are about to make ACO the default backend.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5445>
2020-06-25 15:16:28 +02:00
Daniel Schürmann b78f64507e radv: introduce RADV_DEBUG=llvm option
This option enables the LLVM compiler backend to be used
for shader compilation

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5445>
2020-06-25 15:16:23 +02:00
Mike Blumenkrantz 37e7a5e746 zink: unify code for setting resource barriers
no functional changes, this code was just duplicated

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5615>
2020-06-25 12:50:21 +00:00