turnip: implement VK_KHR_shader_draw_parameters
Note: going by the blob, VFD_INDEX_OFFSET/FD_INSTANCE_START_OFFSET seem completely unused by indirect draws, so this changes them to only be set for non-indirect draws (and moves them to the vs_params draw state). Passes dEQP-VK.draw.shader_draw_parameters.* Signed-off-by: Jonathan Marek <jonathan@marek.ca> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5635>
This commit is contained in:
Jonathan Marek
Marge Bot
parent
16a9e233da
commit
62de79ac44
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@ -919,6 +919,7 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
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tu_cs_emit_write_reg(cs, REG_A6XX_SP_UNKNOWN_AB00, 0x5);
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tu_cs_emit_write_reg(cs, REG_A6XX_VPC_GS_SIV_CNTL, 0x0000ffff);
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/* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
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tu_cs_emit_write_reg(cs, REG_A6XX_VFD_ADD_OFFSET, A6XX_VFD_ADD_OFFSET_VERTEX);
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tu_cs_emit_write_reg(cs, REG_A6XX_RB_UNKNOWN_8811, 0x00000010);
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tu_cs_emit_write_reg(cs, REG_A6XX_PC_MODE_CNTL, 0x1f);
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@ -2973,46 +2974,6 @@ tu6_emit_consts(struct tu_cmd_buffer *cmd,
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return tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
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}
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static VkResult
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tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
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uint32_t first_instance,
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struct tu_cs_entry *entry)
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{
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/* TODO: fill out more than just base instance */
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const struct tu_program_descriptor_linkage *link =
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&cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
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const struct ir3_const_state *const_state = &link->const_state;
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struct tu_cs cs;
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if (const_state->offsets.driver_param >= link->constlen) {
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*entry = (struct tu_cs_entry) {};
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return VK_SUCCESS;
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}
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VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 8, &cs);
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if (result != VK_SUCCESS)
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return result;
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tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
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tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(const_state->offsets.driver_param) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
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CP_LOAD_STATE6_0_NUM_UNIT(1));
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, 0);
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STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, first_instance);
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tu_cs_emit(&cs, 0);
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*entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
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return VK_SUCCESS;
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}
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static struct tu_cs_entry
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tu6_emit_vertex_buffers(struct tu_cmd_buffer *cmd,
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const struct tu_pipeline *pipeline)
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@ -3156,9 +3117,7 @@ static VkResult
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tu6_draw_common(struct tu_cmd_buffer *cmd,
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struct tu_cs *cs,
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bool indexed,
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uint32_t vertex_offset,
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uint32_t first_instance,
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/* note: draw_count count is 0 for indirect */
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/* note: draw_count is 0 for indirect */
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uint32_t draw_count)
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{
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const struct tu_pipeline *pipeline = cmd->state.pipeline;
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@ -3171,10 +3130,6 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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/* TODO lrz */
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tu_cs_emit_regs(cs,
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A6XX_VFD_INDEX_OFFSET(vertex_offset),
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A6XX_VFD_INSTANCE_START_OFFSET(first_instance));
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tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0(
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.primitive_restart =
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pipeline->ia.primitive_restart && indexed,
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@ -3225,11 +3180,6 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS)
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cmd->state.vertex_buffers_ib = tu6_emit_vertex_buffers(cmd, pipeline);
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struct tu_cs_entry vs_params;
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result = tu6_emit_vs_params(cmd, first_instance, &vs_params);
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if (result != VK_SUCCESS)
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return result;
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bool has_tess =
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pipeline->active_stages & VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT;
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struct tu_cs_entry tess_consts = {};
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@ -3269,7 +3219,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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tu_cs_emit_sds_ib(cs, TU_DRAW_STATE_DESC_SETS, cmd->state.desc_sets_ib);
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tu_cs_emit_sds_ib(cs, TU_DRAW_STATE_DESC_SETS_LOAD, cmd->state.desc_sets_load_ib);
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tu_cs_emit_sds_ib(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers_ib);
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tu_cs_emit_sds_ib(cs, TU_DRAW_STATE_VS_PARAMS, vs_params);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
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for (uint32_t i = 0; i < ARRAY_SIZE(cmd->state.dynamic_state); i++) {
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_DYNAMIC + i,
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@ -3306,7 +3256,7 @@ tu6_draw_common(struct tu_cmd_buffer *cmd,
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tu_cs_emit_sds_ib(cs, TU_DRAW_STATE_DESC_SETS_LOAD, cmd->state.desc_sets_load_ib);
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if (cmd->state.dirty & TU_CMD_DIRTY_VERTEX_BUFFERS)
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tu_cs_emit_sds_ib(cs, TU_DRAW_STATE_VB, cmd->state.vertex_buffers_ib);
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tu_cs_emit_sds_ib(cs, TU_DRAW_STATE_VS_PARAMS, vs_params);
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tu_cs_emit_draw_state(cs, TU_DRAW_STATE_VS_PARAMS, cmd->state.vs_params);
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}
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tu_cs_sanity_check(cs);
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@ -3352,6 +3302,68 @@ tu_draw_initiator(struct tu_cmd_buffer *cmd, enum pc_di_src_sel src_sel)
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return initiator;
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}
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static uint32_t
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vs_params_offset(struct tu_cmd_buffer *cmd)
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{
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const struct tu_program_descriptor_linkage *link =
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&cmd->state.pipeline->program.link[MESA_SHADER_VERTEX];
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const struct ir3_const_state *const_state = &link->const_state;
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if (const_state->offsets.driver_param >= link->constlen)
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return 0;
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/* this layout is required by CP_DRAW_INDIRECT_MULTI */
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STATIC_ASSERT(IR3_DP_DRAWID == 0);
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STATIC_ASSERT(IR3_DP_VTXID_BASE == 1);
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STATIC_ASSERT(IR3_DP_INSTID_BASE == 2);
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/* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
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assert(const_state->offsets.driver_param != 0);
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return const_state->offsets.driver_param;
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}
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static struct tu_draw_state
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tu6_emit_vs_params(struct tu_cmd_buffer *cmd,
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uint32_t vertex_offset,
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uint32_t first_instance)
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{
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uint32_t offset = vs_params_offset(cmd);
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struct tu_cs cs;
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VkResult result = tu_cs_begin_sub_stream(&cmd->sub_cs, 3 + (offset ? 8 : 0), &cs);
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if (result != VK_SUCCESS) {
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cmd->record_result = result;
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return (struct tu_draw_state) {};
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}
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/* TODO: don't make a new draw state when it doesn't change */
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tu_cs_emit_regs(&cs,
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A6XX_VFD_INDEX_OFFSET(vertex_offset),
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A6XX_VFD_INSTANCE_START_OFFSET(first_instance));
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if (offset) {
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tu_cs_emit_pkt7(&cs, CP_LOAD_STATE6_GEOM, 3 + 4);
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tu_cs_emit(&cs, CP_LOAD_STATE6_0_DST_OFF(offset) |
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CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS) |
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CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT) |
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CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER) |
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CP_LOAD_STATE6_0_NUM_UNIT(1));
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, 0);
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tu_cs_emit(&cs, vertex_offset);
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tu_cs_emit(&cs, first_instance);
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tu_cs_emit(&cs, 0);
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}
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struct tu_cs_entry entry = tu_cs_end_sub_stream(&cmd->sub_cs, &cs);
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return (struct tu_draw_state) {entry.bo->iova + entry.offset, entry.size / 4};
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}
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void
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tu_CmdDraw(VkCommandBuffer commandBuffer,
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uint32_t vertexCount,
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@ -3362,7 +3374,9 @@ tu_CmdDraw(VkCommandBuffer commandBuffer,
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TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
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struct tu_cs *cs = &cmd->draw_cs;
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tu6_draw_common(cmd, cs, false, firstVertex, firstInstance, vertexCount);
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cmd->state.vs_params = tu6_emit_vs_params(cmd, firstVertex, firstInstance);
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tu6_draw_common(cmd, cs, false, vertexCount);
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tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 3);
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tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
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@ -3381,7 +3395,9 @@ tu_CmdDrawIndexed(VkCommandBuffer commandBuffer,
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TU_FROM_HANDLE(tu_cmd_buffer, cmd, commandBuffer);
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struct tu_cs *cs = &cmd->draw_cs;
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tu6_draw_common(cmd, cs, true, vertexOffset, firstInstance, indexCount);
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cmd->state.vs_params = tu6_emit_vs_params(cmd, vertexOffset, firstInstance);
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tu6_draw_common(cmd, cs, true, indexCount);
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tu_cs_emit_pkt7(cs, CP_DRAW_INDX_OFFSET, 7);
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tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
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@ -3403,13 +3419,25 @@ tu_CmdDrawIndirect(VkCommandBuffer commandBuffer,
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TU_FROM_HANDLE(tu_buffer, buf, _buffer);
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struct tu_cs *cs = &cmd->draw_cs;
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tu6_draw_common(cmd, cs, false, 0, 0, 0);
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cmd->state.vs_params = (struct tu_draw_state) {};
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for (uint32_t i = 0; i < drawCount; i++) {
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tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT, 3);
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tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
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tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset + stride * i);
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}
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tu6_draw_common(cmd, cs, false, 0);
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/* workaround for a firmware bug with CP_DRAW_INDIRECT_MULTI, where it
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* doesn't wait for WFIs to be completed and leads to GPU fault/hang
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* TODO: this could be worked around in a more performant way,
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* or there may exist newer firmware that has been fixed
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*/
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if (cmd->device->physical_device->gpu_id != 650)
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tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
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tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 6);
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tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_INDEX));
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tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL) |
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A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
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tu_cs_emit(cs, drawCount);
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tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
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tu_cs_emit(cs, stride);
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tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
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}
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@ -3425,15 +3453,27 @@ tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer,
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TU_FROM_HANDLE(tu_buffer, buf, _buffer);
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struct tu_cs *cs = &cmd->draw_cs;
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tu6_draw_common(cmd, cs, true, 0, 0, 0);
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cmd->state.vs_params = (struct tu_draw_state) {};
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for (uint32_t i = 0; i < drawCount; i++) {
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tu_cs_emit_pkt7(cs, CP_DRAW_INDX_INDIRECT, 6);
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tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
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tu_cs_emit_qw(cs, cmd->state.index_va);
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tu_cs_emit(cs, A5XX_CP_DRAW_INDX_INDIRECT_3_MAX_INDICES(cmd->state.max_index_count));
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tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset + stride * i);
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}
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tu6_draw_common(cmd, cs, true, 0);
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/* workaround for a firmware bug with CP_DRAW_INDIRECT_MULTI, where it
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* doesn't wait for WFIs to be completed and leads to GPU fault/hang
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* TODO: this could be worked around in a more performant way,
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* or there may exist newer firmware that has been fixed
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*/
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if (cmd->device->physical_device->gpu_id != 650)
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tu_cs_emit_pkt7(cs, CP_WAIT_FOR_ME, 0);
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tu_cs_emit_pkt7(cs, CP_DRAW_INDIRECT_MULTI, 9);
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tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_DMA));
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tu_cs_emit(cs, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED) |
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A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd)));
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tu_cs_emit(cs, drawCount);
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tu_cs_emit_qw(cs, cmd->state.index_va);
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tu_cs_emit(cs, cmd->state.max_index_count);
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tu_cs_emit_qw(cs, buf->bo->iova + buf->bo_offset + offset);
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tu_cs_emit(cs, stride);
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tu_bo_list_add(&cmd->bo_list, buf->bo, MSM_SUBMIT_BO_READ);
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}
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@ -3450,7 +3490,9 @@ void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer,
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TU_FROM_HANDLE(tu_buffer, buf, _counterBuffer);
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struct tu_cs *cs = &cmd->draw_cs;
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tu6_draw_common(cmd, cs, false, 0, firstInstance, 0);
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cmd->state.vs_params = tu6_emit_vs_params(cmd, 0, firstInstance);
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tu6_draw_common(cmd, cs, false, 0);
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tu_cs_emit_pkt7(cs, CP_DRAW_AUTO, 6);
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tu_cs_emit(cs, tu_draw_initiator(cmd, DI_SRC_SEL_AUTO_XFB));
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@ -590,8 +590,8 @@ tu_GetPhysicalDeviceFeatures(VkPhysicalDevice physicalDevice,
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.sampleRateShading = true,
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.dualSrcBlend = true,
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.logicOp = true,
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.multiDrawIndirect = false,
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.drawIndirectFirstInstance = false,
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.multiDrawIndirect = true,
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.drawIndirectFirstInstance = true,
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.depthClamp = true,
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.depthBiasClamp = false,
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.fillModeNonSolid = false,
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@ -636,6 +636,22 @@ tu_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
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vk_foreach_struct(ext, pFeatures->pNext)
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{
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switch (ext->sType) {
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES:
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*((VkPhysicalDeviceVulkan11Features*) ext) = (VkPhysicalDeviceVulkan11Features) {
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.storageBuffer16BitAccess = false,
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.uniformAndStorageBuffer16BitAccess = false,
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.storagePushConstant16 = false,
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.storageInputOutput16 = false,
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.multiview = false,
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.multiviewGeometryShader = false,
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.multiviewTessellationShader = false,
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.variablePointersStorageBuffer = false,
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.variablePointers = false,
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.protectedMemory = false,
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.samplerYcbcrConversion = true,
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.shaderDrawParameters = true,
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};
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break;
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
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VkPhysicalDeviceVariablePointersFeatures *features = (void *) ext;
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features->variablePointersStorageBuffer = false;
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@ -653,7 +669,7 @@ tu_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice,
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
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VkPhysicalDeviceShaderDrawParametersFeatures *features =
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(VkPhysicalDeviceShaderDrawParametersFeatures *) ext;
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features->shaderDrawParameters = false;
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features->shaderDrawParameters = true;
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break;
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}
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case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
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@ -81,6 +81,7 @@ EXTENSIONS = [
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Extension('VK_EXT_filter_cubic', 1, 'device->gpu_id == 650'),
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Extension('VK_EXT_index_type_uint8', 1, True),
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Extension('VK_EXT_vertex_attribute_divisor', 1, True),
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Extension('VK_KHR_shader_draw_parameters', 1, True),
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]
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MAX_API_VERSION = VkVersion(MAX_API_VERSION)
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@ -815,6 +815,8 @@ struct tu_cmd_state
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struct tu_cs_entry desc_sets_ib, desc_sets_load_ib;
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struct tu_cs_entry ia_gmem_ib, ia_sysmem_ib;
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struct tu_draw_state vs_params;
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/* Index buffer */
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uint64_t index_va;
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uint32_t max_index_count;
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@ -48,6 +48,7 @@ tu_spirv_to_nir(struct ir3_compiler *compiler,
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.caps = {
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.transform_feedback = true,
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.tessellation = true,
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.draw_parameters = true,
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},
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};
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const nir_shader_compiler_options *nir_options =
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