KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

freedreno/a6xx: Add support for polygon fill mode (as long as front==back). 

Unlike a4xx, we don't seem to have separate back vs front fields any more.
Still, this improves desktop GL conformance (and one of the traces in
traces-db).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5650>
This commit is contained in:
Eric Anholt 2020-06-10 13:11:21 -07:00
parent 72c0522db2
commit 50e20cb036
3 changed files with 18 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
.gitlab-ci/traces-baremetal.yml
View File

@ -40,10 +40,8 @@ traces:
checksum: 86d678c70b8adf27095ace1a6bbfe2d2
- path: gputest/plot3d.trace
expectations:
# Actually incorrect rendering, it's supposed to be a mesh but
# we're not doing polygon modes apparently.
- device: freedreno-a630
checksum: 8ec42780bfd9df16c49d876aa2f4cb8a
checksum: 67a9eb692e694b11107860bbcd47d493
# Note: Requires GL4 for tess.
- path: gputest/tessmark.trace
expectations:

2
src/gallium/drivers/freedreno/a6xx/fd6_emit.c
View File

@ -1194,9 +1194,7 @@ fd6_emit_restore(struct fd_batch *batch, struct fd_ringbuffer *ring)
WRITE(REG_A6XX_VPC_UNKNOWN_9210, 0);
WRITE(REG_A6XX_VPC_UNKNOWN_9211, 0);
WRITE(REG_A6XX_VPC_UNKNOWN_9602, 0);
WRITE(REG_A6XX_PC_POLYGON_MODE, POLYMODE6_TRIANGLES);
WRITE(REG_A6XX_PC_UNKNOWN_9E72, 0);
WRITE(REG_A6XX_VPC_POLYGON_MODE, POLYMODE6_TRIANGLES);
WRITE(REG_A6XX_SP_TP_SAMPLE_CONFIG, 0);
/* NOTE blob seems to (mostly?) use 0xb2 for SP_TP_UNKNOWN_B309
* but this seems to kill texture gather offsets.

18
src/gallium/drivers/freedreno/a6xx/fd6_rasterizer.c
View File

@ -39,7 +39,7 @@ struct fd_ringbuffer *
__fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
const struct pipe_rasterizer_state *cso, bool primitive_restart)
{
struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 14 * 4);
struct fd_ringbuffer *ring = fd_ringbuffer_new_object(ctx->pipe, 18 * 4);
float psize_min, psize_max;
if (cso->point_size_per_vertex) {
@ -94,6 +94,22 @@ __fd6_setup_rasterizer_stateobj(struct fd_context *ctx,
.primitive_restart = primitive_restart,
));
enum a6xx_polygon_mode mode = POLYMODE6_TRIANGLES;
switch (cso->fill_front) {
case PIPE_POLYGON_MODE_POINT:
mode = POLYMODE6_POINTS;
break;
case PIPE_POLYGON_MODE_LINE:
mode = POLYMODE6_LINES;
break;
default:
assert(cso->fill_front == PIPE_POLYGON_MODE_FILL);
break;
}
OUT_REG(ring, A6XX_VPC_POLYGON_MODE(.mode = mode));
OUT_REG(ring, A6XX_PC_POLYGON_MODE(.mode = mode));
return ring;
}