Commit Graph

84 Commits

Author SHA1 Message Date
Leo Liu 130d1f456b radeon/uvd: reconstruct MJPEG bitstream
The current tier 1 mjpeg firmware only supports at the bitstream
level, the later tier 2 support will be at the buffers level with
newer hardware.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 3fe713ce3d radeon/uvd: add MJPEG support
There is no need of dpb buffer for mjpeg codec

v2: check dpb_size instead of format

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 2b1eacabfa radeon/uvd: get the target buffer pitch correct for different format
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Boyuan Zhang cb8b84e3d0 radeon/uvd: set correct vega10 db pitch alignment
Create new function to get correct alignment based on Asics, and change
the corresponding decode message buffer and dpb buffer size calculations

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-03-30 14:44:33 +02:00
Leo Liu c89e771c9c radeon/uvd: clear message buffer when reuse
As required by firmware

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-03-30 14:44:33 +02:00
Leo Liu c836f2ce28 radeon/uvd: adapt gfx9 surface to uvd
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-03-30 14:44:33 +02:00
Leo Liu 9d5db4e8f4 radeon/uvd: add uvd soc15 register
Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-03-30 14:44:33 +02:00
Marek Olšák ba2e7c68ce gallium/radeon: move pre-GFX9 radeon_surf.* members to radeon_surf.u.legacy.*
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-30 14:44:33 +02:00
Christian König 88f3451083 radeon/uvd: enable 10bit HEVC decode v2
Just use whatever the state tracker allocated.

v2: fix msb mode

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13 08:51:29 +01:00
Christian König 3e1e441aa0 radeon/UVD: fix the decoding target pitch calculation
The firmware expects the value in pixel not bytes. Didn't made a difference
so far because we only used 8bpp surfaces.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Mark Thompson <sw@jkqxz.net>
2017-03-13 08:51:25 +01:00
Boyuan Zhang c29191eea8 radeon/uvd: add h264 constrained baseline support
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-02-01 14:32:32 -05:00
Marek Olšák e9c76eeeaa gallium/radeon: remove radeon_surf_level::pitch_bytes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-11-01 22:33:13 +01:00
Nicolai Hähnle dfc1afda83 winsys/radeon: add buffer_get_reloc_offset
Really fix the bug that was supposed to be fixed by commits 3e7cced4b and
a48bf02d: even when virtual addresses are used, the legacy relocation-based
method with offsets relative to the kernel's buffer object are used for
video submissions.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97969
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-10-04 16:37:44 +02:00
Nicolai Hähnle 3e7cced4b9 radeon/uvd: adjust the buffer offset when relocation is used
We don't plan to use sub-allocated buffers with UVD, but just in case one
slips through, this increases the chances of things working out anyway.

Reviewed-by: Christian König <christian.koenig@amd.com>
2016-09-30 12:38:52 +02:00
Nicolai Hähnle e703f71ebd gallium/radeon: add RADEON_USAGE_SYNCHRONIZED
This is really the behavior we want most of the time, but having a
SYNCHRONIZED flag instead of an UNSYNCHRONIZED one has the advantage that
OR'ing different flags together always results in stronger guarantees.

The parent BOs of sub-allocated buffers will be added unsynchronized.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-09-27 16:45:02 +02:00
Christian König 3e1ad846f9 radeon/uvd: add session context buffer for polaris 10/11 v2
This way we have unlimited UVD sessions.

v2: only enable it when kernel supports it as well.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-18 17:13:17 +02:00
Marek Olšák 33eddde4a7 radeon/uvd: fail to create a decoder if RUVD_MSG_CREATE submission fails
This is the bare minimum for reporting the error to the user.

Reviewed-by: Christian König <christian.koenig@amd.com>
2016-07-14 22:00:54 +02:00
Christian König 64ac4aef27 radeon/uvd: simplify sending context buffer message
Just send it whenever it is allocated.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:32 +02:00
Christian König 6b474e06a2 radeon/uvd: fix contex buffer destruction in the error path
Destroying a not allocated buffer is harmless.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:32 +02:00
Christian König 36df04dac4 radeon/uvd: move polaris fw check into radeon_video.c v2
It's actually not very clever to claim to support H.264
and then fail to create a decoder.

v2: prefix FW macro with UVD_.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2016-07-08 21:03:31 +02:00
Indrajit Das 51227b41c6 radeon/uvd: fix overflow error while calculating bit stream buffer size
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-07-04 11:38:05 +02:00
sonjiang b928ff6f62 radeon/uvd: fix a h265 context size bug
Signed-off-by: sonjiang <sonny.jiang@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-06-29 15:30:25 -04:00
sonjiang 5c80354a23 radeon/uvd: seperate uvd context buffer from DPB
Signed-off-by: sonjiang <sonny.jiang@amd.com>
Cc: "12.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-06-29 15:30:20 -04:00
Marek Olšák 7db10093d3 gallium/radeon: boolean -> bool, TRUE -> true, FALSE -> false
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-06-25 23:13:42 +02:00
Nicolai Hähnle c23273532e gallium/radeon: use radeon_emit
Mostly generated using a sed-script, with manual fix-up for multi-line
statements.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-05-17 15:28:38 -05:00
Leo Liu 8f4340c5e6 radeon/uvd: fix tonga feedback buffer size
This only applies to tonga

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Cc: "11.1 11.2" <mesa-stable@lists.freedesktop.org>
2016-04-14 19:33:44 -04:00
Boyuan Zhang 1c7ba7f156 radeon/uvd: alignment fix for decode message buffer
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2016-04-11 19:30:47 -04:00
Marek Olšák 8140154ae9 gallium/radeon: remove old CS tracing
Cons:
- it was only integrated in r600g
- it doesn't work with GPUVM
- it records buffer contents at the end of IBs instead of at the beginning,
  so the replay isn't exact
- it lacks an IB parser and user-friendliness

A better solution is apitrace in combination with gallium/ddebug, which
has a complete IB parser and can pinpoint hanging CP packets.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-03-20 00:56:35 +01:00
Boyuan Zhang 8be9efcce7 radeon/uvd: handle HEVC main 10 decode
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2016-03-11 22:33:56 -05:00
Marek Olšák 79d0082c64 radeon/uvd: silence a warning 2016-02-10 20:16:17 +01:00
Marek Olšák cf811faeff gallium/radeon: remove radeon_winsys_cs_handle
"radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf".

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Boyuan Zhang f55f134a03 radeon/uvd: uv pitch separation for stoney
v2: set the behaviour default for future ASICs.

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-11-23 17:34:43 -05:00
Boyuan Zhang 6bad554d98 radeon/uvd: fix VC-1 simple/main profile decode v2
We just needed to set the extra width/height fields to get this working.

v2 (chk): rebased, CC stable added, commit message added, fixed coding style

Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Cc: "10.6 11.0" <mesa-stable@lists.freedesktop.org>
2015-11-06 20:07:23 +01:00
Boyuan Zhang 38c3d7cfc4 radeon/uvd: implement and add flag for VAAPI HEVC decode
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-10-27 19:09:55 -04:00
Marek Olšák 93641f4341 gallium/radeon: stop using "reloc" in a few places
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-03 22:06:07 +02:00
Marek Olšák 2edb060639 gallium/radeon: tell the winsys the exact resource binding types
Use the priority flags and expand them.
This information will be used for debugging.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-03 22:06:07 +02:00
Grazvydas Ignotas 97f5d00648 radeon/uvd: remove unused variables
Recent commits introduced new unused variable warnings, fix them.

Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-18 14:11:48 +02:00
Boyuan Zhang 839bf82606 radeon/uvd: implement HEVC support
add context buffer to fix H265 uvd decode issue.
fix H265 corruption issue caused by incorrect assigned ref_pic_list.

v2: disable interlace for HEVC
    add CZ sps flag workaround
    fix coding style

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
2015-08-14 15:02:31 +02:00
Leo Liu 22f71dbf79 radeon/uvd: make 30M as minimum for MPEG4 dpb buffer size
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu baecc518c9 radeon/uvd: recalculate dbp buffer size
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-14 15:02:30 +02:00
Leo Liu 261ed77547 gallium/radeon: add h264 performance HW decoder support
v2: -make tonga use new h264 performance HW decoder;
    -integrate it scaling buffer to msg_fb buffer

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-14 15:02:30 +02:00
Christian König 0248c13a8b gallium/radeon: use VM for UVD
v2: (leo) add checking for driver backend
v3: (leo) change variable name from use_amdgpu to use_vm
v4: rebase by Marek

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-08-14 15:02:30 +02:00
Marek Olšák 42d9f6323a winsys/radeon: add an interface for contexts
Same idea as in libdrm_amdgpu.

A command stream can only be created for a specific context and it's always
submitted to that context.

This will mainly be used by amdgpu and it's required by the GPU reset status
query too.
(radeon only has a basic version of the query and thus doesn't need this)

Reviewed-by: Christian König <christian.koenig@amd.com>
2015-08-07 00:06:52 +02:00
Marek Olšák a582b22c63 winsys/radeon: add a private interface for radeon_surface 2015-04-29 21:51:40 +02:00
Marek Olšák dcfbc006b6 winsys/radeon: move radeon_winsys.h to drivers/radeon 2015-04-29 21:51:40 +02:00
Christian König 6327b58415 radeon/uvd: use PIPE_USAGE_STAGING for msg&fb buffers
That better matches the actual userspace use case, the
kernel will force it to VRAM if the hardware requires it.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11 15:06:09 +02:00
Christian König 4dfdcdb4b3 radeon/video: use the hw to initial clear the buffers
Less CPU overhead and avoids contention over CPU accessible memory on startup.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11 15:06:03 +02:00
Christian König 4bc0059229 radeon/video: use more of the common buffer code v2
In preparation to using buffers clears with the hw engine(s).

v2: split out flipping to using hw buffer clears.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2014-09-11 15:05:55 +02:00
Emil Velikov a131263a2f gallium/radeon: cleanup header inclusion
- Add top_srcdir/src/gallium/winsys to GALLIUM_DRIVER_C{XXFLAGS}.
 - Remove top_srcdir/src/gallium/drivers/radeon from the includes.

As a result:
 - Common radeon headers are prefixed with 'radeon/'
 - Winsys header inclusion is prefixed 'radeon/drm'

Cc: Marek Olšák <marek.olsak@amd.com>
Cc: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-08-28 21:24:37 +01:00
Michel Dänzer 07c65b85ea r600g/radeonsi: Use write-combined CPU mappings of some BOs in GTT
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-07-23 18:55:50 +09:00