b58dd252aa
lavapipe: Use the common BindVertexBuffers wrapper
...
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611 >
2022-05-20 02:12:37 +00:00
a299e5efbb
radv: Use the common CmdBindVertexBuffers wrapper
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611 >
2022-05-20 02:12:37 +00:00
50a00f889c
radv: Add a sqtt entrypoint for CmdBindVertexBuffers2
...
Fixes: b262284300https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611 >
2022-05-20 02:12:37 +00:00
c24aa449d0
vulkan,anv,turnip: Add a common CmdBindVertexBuffers wrapper
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16611 >
2022-05-20 02:12:37 +00:00
cc4d5b1666
radeonsi: lower nir_intrinsic_sparse_residency_code_and
...
This is required by lower_tg4_offsets which split one
sparseTextureGatherOffsetsARB call to four sparseTextureGatherOffsetARB
calls and merge their resisident results into one.
Fixes: ee040a6b63https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16599 >
2022-05-20 01:45:12 +00:00
2fbbb8ad63
zink: update radv baseline
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16622 >
2022-05-19 23:51:38 +00:00
d6b943adde
egl: Fix EGL_EXT_platform_xcb name string to match the registry
...
Signed-off-by: Nicolas Caramelli <caramelli.devel@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16609 >
2022-05-19 23:21:15 +00:00
e6981d6da2
docs: update calendar and link releases notes for 22.0.4
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16617 >
2022-05-19 22:38:46 +00:00
f0e3c71c96
docs: Extend calendar entries for 22.0 by 1 releases.
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16617 >
2022-05-19 22:38:46 +00:00
569553f7c4
docs: add sha256sum to 22.0.4 notes
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16617 >
2022-05-19 22:38:46 +00:00
3cfcb3a1e0
docs: add release notes for 22.0.4
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16617 >
2022-05-19 22:38:46 +00:00
c6cddd2e17
lavapipe: Use the correct ICD path on Win32
...
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16612 >
2022-05-19 21:53:06 +00:00
27314718a3
intel: Drop Wa_1409226450 (stall before instruction cache invalidation)
...
Production Tigerlake and DG1 hardware shouldn't need this workaround.
It was only needed on the very first steppings which never went public.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16575 >
2022-05-19 21:31:45 +00:00
7938ce4af3
freedreno/ir3: Lower texture instructions used only for f2f16 to 16-bit.
...
2.5% improvement in gfxbench vk-5-normal. No obvious change on
gl-5-normal.
shader-db on Rob's android shaders:
total instructions in shared programs: 770644 -> 770595 (<.01%)
instructions in affected programs: 14880 -> 14831 (-0.33%)
total nops in shared programs: 167784 -> 167860 (0.05%)
nops in affected programs: 3351 -> 3427 (2.27%)
total non-nops in shared programs: 602860 -> 602735 (-0.02%)
non-nops in affected programs: 10523 -> 10398 (-1.19%)
total mov in shared programs: 19313 -> 19286 (-0.14%)
mov in affected programs: 365 -> 338 (-7.40%)
total cov in shared programs: 18075 -> 17978 (-0.54%)
cov in affected programs: 566 -> 469 (-17.14%)
total dwords in shared programs: 1612848 -> 1612596 (-0.02%)
dwords in affected programs: 13882 -> 13630 (-1.82%)
total last-baryf in shared programs: 56144 -> 55975 (-0.30%)
last-baryf in affected programs: 482 -> 313 (-35.06%)
total full in shared programs: 36094 -> 36092 (<.01%)
full in affected programs: 10 -> 8 (-20.00%)
total sstall in shared programs: 66986 -> 66923 (-0.09%)
sstall in affected programs: 1392 -> 1329 (-4.53%)
total systall in shared programs: 91244 -> 91072 (-0.19%)
systall in affected programs: 1194 -> 1022 (-14.41%)
total (sy) in shared programs: 4316 -> 4321 (0.12%)
(sy) in affected programs: 19 -> 24 (26.32%)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
1cf0736f1c
freedreno/ir3: Add support for 16-bit nir_texop_lod.
...
Same basic path, just do the rescaling in half float.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
a28d2e87d3
turnip: Make RelaxedPrecision-decorated ALU ops 16-bit.
...
Improves gfxbench vk-5-normal performance 5.5%.
Fixes : #6346
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
260559050a
spirv_to_nir: Cast RelaxedPrecision ALU op dests to mediump.
...
This is controlled by spirv_to_nir_options.relaxed_precision_alu, because
some drivers don't want it.
This gets us mostly 16-bit math on turnip in vk-5-normal.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
87d7431198
spirv: Use nir_vec_scalars() to simplify matrix transpose.
...
This should emit fewer instructions that need to be copy-propagated away.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
633cf4eca1
freedreno/ir3: Fix 16-bit bit_count.
...
No need to do the 16-bit lowering if it already is.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465 >
2022-05-19 19:43:36 +00:00
1c077ca9c0
u_trace/anv/iris: drop cs argument for recording traces
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16605 >
2022-05-19 19:04:28 +00:00
12773d4070
docs/u_trace: document u_trace usage
...
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16579 >
2022-05-19 17:57:36 +00:00
8cabf134a8
svga: fix aa point
...
Use in_prim from current geometry shader to check for point prim type
when determine if aa point is enabled or not.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16598 >
2022-05-19 17:17:12 +00:00
8cbcdb4f10
svga: add need_texcoord_semantic to tgsi_add_point_sprite & tgsi_add_aa_point
...
Since PIPE_CAP_TGSI_TEXCOORD is now set in SVGA vgpu10 driver,
we need to add a new parameter need_texcoord_semantic to
tgsi_add_point_sprite and tgsi_add_aa_point
to allow setting texcoords using tgsi texcoord semantic.
Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16598 >
2022-05-19 17:17:12 +00:00
5398c9183e
intel/ds: fix compilation
...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6518
Fixes: efc2782f97https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16601 >
2022-05-19 16:42:41 +00:00
9565ea5640
docs: Add calendar entries for 22.1 release.
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610 >
2022-05-19 16:37:15 +00:00
35e3aea0b2
relnotes: Add sha256sum and fix minor formatting issues
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610 >
2022-05-19 16:37:15 +00:00
5944b9ab83
docs: add release notes for 22.1.0
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610 >
2022-05-19 16:37:15 +00:00
e84de9c04f
docs: update calendar and link releases notes for 22.1.0
...
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610 >
2022-05-19 16:37:15 +00:00
d6ece34d0c
pan/va: Use ^ instead of ` to indicate last-use
...
This syncs the ISA syntax with other Valhall ISA users. It's also somewhat
easier to read.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
9fb8ca1851
pan/va: Remove DISCARD.f32 destination
...
It doesn't actually write anything. This is a pointless divergence from Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
444469d64e
pan/va: Handle 2-src blend in lower_split_src
...
Fixes assertion fail in shaders/dolphin/smg.1.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
0576cad958
pan/bi: Validate vector widths
...
Now that our IR is much more strongly typed, and RA code quality depends on
correct typing, add a validation pass to make sure we didn't screw it up. This
pass found a massive number of bugs in early versions of this series.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
4c1bb23a86
pan/bi: Validate preload constraints are satisfied
...
We tightened the rules around preloading substantially and take advantage of the
rules in RA. The safe helpers it introduced should ensure the rules are
followed, but just in case, add a validation pass to check our work. This pass
found (multiple) bugs in early versions of this series.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
3636cddde1
pan/bi: See through splits for var_tex fusion
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
1f25f78a9f
pan/bi: Optimize split of collect
...
Required to get decent codegen from UBO pushing.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
4a8bde2190
pan/bi: Don't propagate discard
...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
d81b872465
pan/bi: Remove liveness metadata tracking
...
We don't use it for anything, and with no pass infrastructure it's just an
accident waiting to happen.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
3df5446cbd
pan/bi: Simplify register precolouring in the IR
...
In the current IR, any register may be preloaded by reading it anywhere, and any
register may be precoloured by writing it anywhere. This is convenient for
instruction selection, but requires the register allocator to do considerable
gymnastics to ensure it doesn't clobber precoloured registers. It also breaks
the purity of our SSA representation, which complicates optimization passes
(e.g. copyprop).
Let's trade some instruction selection complexity for simplifying register
allocation by constraining how register precolouring works. Under the new model:
* Registers may only be preloaded at the start of the program.
* Precoloured destinations are handled explicitly by RA.
Internally, a stronger invariant is placed for preloading: registers may only be
preloaded by MOV.i32 instructions at the beginning of the block, and these moves
must be unique. These invariants ensure RA can trivially coalesce the moves.
A bi_preload helper is added as a safe version of bi_register respecting these
invariants, allowing a smooth transition for instruction selection.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
dab5b62ecf
pan/bi: Remove bi_word and bi_word_node
...
They are no longer used, as offsets are no longer used for normal values (only for
FAU). Keep it like that.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
f0184cf218
pan/bi: Scalarize copyprop
...
Reduces memory footprint.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
c6349278f9
pan/bi: Scalarize modifier propagation
...
Reduces memory footprint.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
e332e2edc1
pan/bi: Scalarize bi_opt_cse
...
Reduces memory footprint.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
187dd382cb
pan/bi: Scalarize bi_lower_swizzle
...
Reduces memory footprint.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
5b1c642cee
pan/va: Don't use bi_word in FAU unit test
...
It will be removed shortly, as the FAU construction helper should be used
instead.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
67569b3c23
pan/va: Use split for 64-bit lowering
...
Written in this way, this pass looks pretty silly...
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
5febeae58e
pan/bi: Emit collect and split
...
..Rather than using offsets during instruction selection.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
4731e9e55a
pan/bi: Simplfy BLEND emit
...
We don't need to collect anything, now that Valhall handles this case correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
7bfaa119f4
pan/bi: Lift split/collect cache from AGX
...
Design based on ACO (and fruitful discussions with Daniel).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
8fdb01b96f
pan/bi: Create COLLECT during isel
...
This transitions us away from the fake SSA we currently use for vectors.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
5c0977d230
pan/bi: Expand MAX_DESTS to 4
...
For splits.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585 >
2022-05-19 16:08:26 +00:00
Jason Ekstrand
Qiang Yu
Mike Blumenkrantz
Nicolas Caramelli
Dylan Baker
Kenneth Graunke
Emma Anholt
Lionel Landwerlin
Danylo Piliaiev
Charmaine Lee
Alyssa Rosenzweig