Commit Graph

101087 Commits

Author SHA1 Message Date
Ian Romanick ae21b52e1d nir/algebraic: Add missing 16-bit extract_[iu]8 patterns
No shader-db changes on any Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
2019-03-28 15:35:52 -07:00
Ian Romanick cbad201c2b nir/algebraic: Add missing 64-bit extract_[iu]8 patterns
No shader-db changes on any Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
2019-03-28 15:35:52 -07:00
Ian Romanick bc17f5a2a3 nir/algebraic: Remove redundant extract_[iu]8 patterns
No shader-db changes on any Intel platform.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-28 15:35:52 -07:00
Ian Romanick c152672e68 nir/algebraic: Fix up extract_[iu]8 after loop unrolling
Skylake, Broadwell, and Haswell had similar results. (Skylake shown)
total instructions in shared programs: 15256840 -> 15256837 (<.01%)
instructions in affected programs: 4713 -> 4710 (-0.06%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.06% max: 0.08% x̄: 0.06% x̃: 0.06%

total cycles in shared programs: 372286583 -> 372286583 (0.00%)
cycles in affected programs: 198516 -> 198516 (0.00%)
helped: 1
HURT: 1
helped stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10
helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
HURT stats (abs)   min: 10 max: 10 x̄: 10.00 x̃: 10
HURT stats (rel)   min: 0.01% max: 0.01% x̄: 0.01% x̃: 0.01%

No changes on any other Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
2019-03-28 15:35:52 -07:00
Dave Airlie b779baa9bf nir/deref: fix struct wrapper casts. (v3)
llvm/spir-v spits out some struct a { struct b {} }, but it
doesn't deref, it casts (struct a) to (struct b), reconstruct
struct derefs instead of casts for these.

v2: use ssa_def_rewrite uses, rework the type restrictions (Jason)
v3: squish more stuff into one function, drop unused temp (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-29 08:10:50 +10:00
Rafael Antognolli 8e0469f629 i965/blorp: Remove unused parameter from blorp_surf_for_miptree.
It seems pretty useless nowadays.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-28 14:38:23 -07:00
Anuj Phogat 9c421d6b47 iris/icl: Add WA_2204188704 to disable pixel shader panic dispatch
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-28 19:59:59 +00:00
Anuj Phogat e0f4359ec1 iris/icl: Set Enabled Texel Offset Precision Fix bit
h/w specification requires this bit to be always set.
See Mesa commit 5eb173304b.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-28 19:59:59 +00:00
Rob Clark 78825ca2d0 freedreno/ir3: align const size to vec4
This is no longer true since PIPE_CAP_PACKED_UNIFORMS was enabled.

Fixes: 3c8779af32 freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-28 14:36:24 -04:00
Rob Clark 26e2906382 freedreno/ir3: reads/writes to unrelated arrays are not dependent
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-28 14:36:24 -04:00
Rob Clark d71ce69d9c freedreno/ir3: sched fix
Not sure why new-style frag inputs start triggering this.  But we
probably shouldn't consider src's from other blocks.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-28 14:36:24 -04:00
Rob Clark c557fcaf2b freedreno/a6xx: small cleanup
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-28 14:36:23 -04:00
Kenneth Graunke ee8370c766 iris: Fix blits with S8_UINT destination
For depth and stencil blits, we always want the main mask to be Z, and
the secondary pass mask to be S.  If asked to blit Z+S to S, we should
handle the blit in the second pass which properly gets the stencil
resources.

Before, we were trying to handle S as the main mask, and accidentally
blitting a Z source to a S destination, which doesn't work out well.

Fixes Piglit's "framebuffer-blit-levels {draw,read} stencil" tests.
2019-03-28 10:47:26 -07:00
Kenneth Graunke ce89c19b88 st/mesa: Fix blitting from GL_DEPTH_STENCIL to GL_STENCIL_INDEX
Fixes assertion failures in Piglit's "framebuffer-blit-levels
{draw,read} stencil" tests on iris.  Also fixes assert failures in
frameretrace, which tries to ReadPixels the stencil values (only)
from a Z24S8 depth/stencil attachment.

Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2019-03-28 10:47:23 -07:00
Kristian H. Kristensen 107a8ec3b3 freedreno/ir3: Add workaround for VS samgq
This instruction needs a workaround when used from vertex shaders.

Fixes:

  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler2dshadow_vertex
  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_fixed_vertex
  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_float_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler2dshadow_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_fixed_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_float_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.sampler2dshadow_vertex

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-28 10:26:32 -07:00
Kristian H. Kristensen f30d4a1cca freedreno/ir3: Don't access beyond available regs
emit_cat5() needs to check if the last optional reg is there before it
accesses it.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-28 10:26:32 -07:00
Eric Engestrom 7fefa4610d util/disk_cache: close fd in the fallback path
There are multiple `goto path_fail` with an open fd, but none that go to
`fail:` without going through `path_fail:` first, so let's just move the
`close(fd)` there.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 16:41:27 +00:00
Samuel Pitoiset 6596eb2b30 radv: skip updating depth/color metadata for conditional rendering
I don't think we should update metadata when conditional rendering
is enabled. For some reasons, some CTS breaks only on SI.

This fixes the following CTS on SI:
dEQP-VK.conditional_rendering.draw_clear.clear.depth.*

Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 17:37:12 +01:00
Kenneth Graunke 1d72de3bcc st/nir: Free the GLSL IR after linking.
i965 does this, and st's tgsi path does this.  st/nir did not.

Cuts 138MB of memory from a DiRT Rally trace, which is about 44%
of the total GLSL IR memory.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-03-28 09:31:12 -07:00
Samuel Pitoiset 227b191206 radv: enable VK_AMD_gpu_shader_int16
This extension allows 16-bit support to Frexp/FrexpStruct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 13:02:53 +01:00
Samuel Pitoiset 8a6e61cc52 radv: do not lower frexp_exp and frexp_sig
Hardware has two instructions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 13:02:51 +01:00
Samuel Pitoiset 52c02d921f ac: add ac_build_frex_exp() helper ans 16-bit/32-bit support
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 13:02:48 +01:00
Samuel Pitoiset 1bf9311c59 ac: add ac_build_frexp_mant() helper and 16-bit/32-bit support
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 13:02:46 +01:00
Kenneth Graunke de783a6897 iris: Actually advertise some modifiers
I neglected to fill out this driver function, causing us to advertise
0 modifiers.  Now we advertise the various tilings and let the driver
pick them.  I've verified that X tiling works with Weston (by hacking
the list to skip Y tiling).

Y+CCS doesn't work yet because it's multiplane and the Gallium dri
state tracker isn't really prepared for that.  Leave it off for now.
2019-03-27 21:27:54 -07:00
Toni Lönnberg 505854f84b intel/genxml: Media instructions and structures for gen11
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    - fix missing type
    - fix *_FQM_*/*_QM_* commands
    - shorten some media structs using groups
    - factor out memory attributes
    - switch MI_FLUSH_DW fields to bool

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Toni Lönnberg 4dccf2edef intel/genxml: Media instructions and structures for gen10
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    - fix missing type
    - fix *_FQM_*/*_QM_* commands
    - shorten some media structs using groups
    - factor out memory attributes
    - switch MI_FLUSH_DW fields to bool

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Toni Lönnberg 8e74cacdad intel/genxml: Media instructions and structures for gen9
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    - fix missing type
    - fix *_FQM_*/*_QM_* commands
    - shorten some media structs using groups
    - factor out memory attributes
    - switch MI_FLUSH_DW fields to bool

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Toni Lönnberg 2f075c5ccc intel/genxml: Media instructions and structures for gen8
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    - switch MI_FLUSH_DW fields to bool

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Toni Lönnberg 2bf89a05f4 intel/genxml: Media instructions and structures for gen7.5
v2: Fixed MI_WAIT_FOR_EVENT to be for video also

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Toni Lönnberg 416e1567ee intel/genxml: Media instructions and structures for gen7
v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Toni Lönnberg 9e6ffe3741 intel/genxml: Media instructions and structures for gen6
v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Toni Lönnberg b6f7b40d81 intel/genxml: Only handle instructions meant for render engine when generating
headers

v2: Fixed the check for engine

v3: Changed engine into an argument given to the scripts

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Dave Airlie ce6faa57ae softpipe: add indirect store buffer/image unit
The code to handle image unit indirect was missing

Fixes piglit tests/spec/arb_arrays_of_arrays/execution/image_store/basic-imageStore-mixed-const-non-const-uniform-index.shader_test

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-03-28 14:13:08 +10:00
Dave Airlie 9f9d9c948d softpipe/draw: fix vertex id in soft paths.
This fixes the vertex id fetch in the non-llvm drawing paths.

This vertex id in elt mode comes from the elts not just a linear
value.

Note we don't bad basevertex in the elts case as it's already included
in the elts by the looks of it (at least tests fail if I add it)

Fixes piglit end-primitive tests and some others.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2019-03-28 14:13:08 +10:00
Kristian H. Kristensen 893425a607 freedreno/ir3: Push UBOs to constant file
We have a rather big constant file and it seems that the best way to
use it is to upload all UBOs and lower UBO access the load_uniform.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-27 13:26:02 -07:00
Kristian H. Kristensen 3c8779af32 freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
This commit turns on the gallium cap and adds a pass to lower the
load_ubo intrinsics for block 0 back to load_uniform intrinsics and
adjust the backend where the cap switches units from vec4s to dwords.

As we stop using ir3_glsl_type_size() for uniform layout, this also
corrects an issue where we would allocate a vec4 slot for samplers in
uniforms, fixing:

  dEQP-GLES3.functional.shaders.struct.uniform.sampler_array_fragment
  dEQP-GLES3.functional.shaders.struct.uniform.sampler_array_vertex
  dEQP-GLES3.functional.shaders.struct.uniform.sampler_nested_fragment
  dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_vertex
  dEQP-GLES2.functional.shaders.struct.uniform.sampler_nested_fragment

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-27 13:26:02 -07:00
Kristian H. Kristensen 56b4bc292f st/glsl_to_nir: Calculate num_uniforms from NumParameterValues
We don't need to determine the number of uniform slots here, it's
already available as prog->Parameters->NumParameterValues.  The way we
previously determined the number of slots was also broken for
PackedDriverUniformStorage, where we would add loc (in dwords) and
type_size() (in vec4s).

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-27 13:26:02 -07:00
Anuj Phogat a583f86305 intel: Add Elkhart Lake device info
V2: Fix L3 bank count (Vivek)
    Fix simulator_id and num_eu_per_subslice (Lionel)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-27 19:34:48 +00:00
Leo Liu f8ef8b56a6 radeon/vcn: add H.264 constrained baseline support
VCN supports this profile as well as UVD, so add it

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
CC: <mesa-stable@lists.freedesktop.org>
2019-03-27 14:33:55 -04:00
Gurchetan Singh ac839bbf79 egl/android: chose node type based on swrast and preprocessor flags
kms_swrast can work with primary nodes out of the box, but also
with rendernodes if the build environment specifies the
EGL_FORCE_RENDERNODE flag.

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2019-03-27 17:26:21 +00:00
Gurchetan Singh a87096b79e egl/android: use software rendering when appropriate
Now the init logic fallbacks to or forces software rendering.

v2: simplify flow (@eric)

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-27 17:26:21 +00:00
Gurchetan Singh d4e7982b6e egl/android: use swrast option in droid_load_driver
Load the kms_swrast driver when specified.
Doesn't work with drm_gralloc.

v2: remove unneeded line (@eric)
v3: Remove swrast_loader_extensions (@evelikov)

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-27 17:26:21 +00:00
Gurchetan Singh f90fc102ed egl/android: plumb swrast option
It's good to have options.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-27 17:26:21 +00:00
Gurchetan Singh 7d9719db83 egl/android: refactor droid_load_driver a bit
This way, we can use primary nodes with kms_swrast too.
Also fix up some whitespace issues.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-27 17:26:21 +00:00
Gurchetan Singh f1dd1be0c2 egl/android: droid_open_device_drm_gralloc --> droid_open_device
Makes things easier to follow.

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-27 17:26:21 +00:00
Gurchetan Singh 95ad1744c1 egl/android: move droid_open_device_drm_gralloc down a bit
1) Removes a forward declaration.
2) Makes next patch easier.

Suggested-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-27 17:26:21 +00:00
Gurchetan Singh 49d52539fb egl/android: move droid_image_loader_extension down a bit
This removes some #ifdefs.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-03-27 17:26:21 +00:00
Jason Ekstrand ce47999cee Revert "anv/radv: release memory allocated by glsl types during spirv_to_nir"
This reverts commit 4e1bbb000c.  It turns
out that some DXVK apps due to some implementation detail of DXVK or
other create and destroy instances in an interleaved way.  Freeing the
glsl_type memory without being a bit more careful causes use-after-free
issues.  Looks like we need to try again.
2019-03-27 11:24:58 -05:00
Tomeu Vizoso b817d00278 panfrost: Wait for last job to finish in force_flush_fragment
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-27 17:03:34 +01:00
Tomeu Vizoso 53ab812230 panfrost: Pass the context BOs to the kernel so they aren't unmapped while in use
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-03-27 17:03:34 +01:00