KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

anv/icl: Set Enabled Texel Offset Precision Fix bit 

h/w specification requires this bit to be always set.

Suggested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Anuj Phogat 2018-08-27 16:16:58 -07:00
parent afb7c6b301
commit 5eb173304b
2 changed files with 19 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
src/intel/genxml/gen11.xml
View File

@ -3640,4 +3640,9 @@
<field name="Headerless Message for Pre-emptable Contexts Mask" start="21" end="21" type="bool"/>
</register>
<register name="HALF_SLICE_CHICKEN7" length="1" num="0x0e194">
<field name="Enabled Texel Offset Precision Fix" start="1" end="1" type="bool"/>
<field name="Enabled Texel Offset Precision Fix Mask" start="17" end="17" type="bool"/>
</register>
</genxml>

14
src/intel/vulkan/genX_state.c
View File

@ -172,6 +172,20 @@ genX(init_device_state)(struct anv_device *device)
lri.RegisterOffset = GENX(SAMPLER_MODE_num);
lri.DataDWord = sampler_mode;
}
/* Bit 1 "Enabled Texel Offset Precision Fix" must be set in
* HALF_SLICE_CHICKEN7 register.
*/
uint32_t half_slice_chicken7;
anv_pack_struct(&half_slice_chicken7, GENX(HALF_SLICE_CHICKEN7),
.EnabledTexelOffsetPrecisionFix = true,
.EnabledTexelOffsetPrecisionFixMask = true);
anv_batch_emit(&batch, GENX(MI_LOAD_REGISTER_IMM), lri) {
lri.RegisterOffset = GENX(HALF_SLICE_CHICKEN7_num);
lri.DataDWord = half_slice_chicken7;
}
#endif
/* Set the "CONSTANT_BUFFER Address Offset Disable" bit, so