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freedreno/ir3: align const size to vec4 

This is no longer true since PIPE_CAP_PACKED_UNIFORMS was enabled.

Fixes: 3c8779af32 freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
Signed-off-by: Rob Clark <robdclark@gmail.com>
This commit is contained in:
Rob Clark 2019-03-28 13:33:30 -04:00
parent 26e2906382
commit 78825ca2d0
1 changed files with 5 additions and 4 deletions
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9
src/gallium/drivers/freedreno/ir3/ir3_gallium.c
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@ -229,7 +229,11 @@ emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
if (constbuf->enabled_mask & (1 << index)) {
struct pipe_constant_buffer *cb = &constbuf->cb[index];
unsigned size = align(cb->buffer_size, 4) / 4; /* size in dwords */
/* size in dwords, aligned to vec4. (This works at least
* with mesa/st, which seems to align constant buffer to
* 16 bytes)
*/
unsigned size = align(cb->buffer_size, 16) / 4;
/* in particular, with binning shader we may end up with
* unused consts, ie. we could end up w/ constlen that is
@ -239,9 +243,6 @@ emit_user_consts(struct fd_context *ctx, const struct ir3_shader_variant *v,
*/
uint32_t max_const = MIN2(v->num_uniforms, v->constlen);
// I expect that size should be a multiple of vec4's:
assert(size == align(size, 4));
/* and even if the start of the const buffer is before
* first_immediate, the end may not be:
*/