Commit Graph

66508 Commits

Author SHA1 Message Date
Chris Forbes adefccd12a i965: Handle nested uniform array indexing
When converting a uniform array reference to a pull constant load, the
`reladdr` expression itself may have its own `reladdr`, arbitrarily
deeply. This arises from expressions like:

   a[b[x]]     where a, b are uniform arrays (or lowered const arrays),
               and x is not a constant.

Just iterate the lowering to pull constants until we stop seeing these
nested. For most shaders, there will be only one pass through this loop.

Fixes the piglit test:
tests/spec/glsl-1.20/linker/double-indirect-1.shader_test

Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2014-11-24 21:07:29 +13:00
Dave Airlie c88385603a r600g: do all CUBE ALU operations before gradient texture operations (v2.1)
This moves all the CUBE section above the gradients section,
so that the gradient emission happens on one block which
is what sb/hardware expect.

v2: avoid changes to bytecode by using spare temps
v2.1: shame gcc, oh the shame. (uninit var warnings)

Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-24 13:33:07 +10:00
Dave Airlie 38ec184419 r600: fix texture gradients instruction emission (v2)
The piglit tests were failing, and it appeared to be SB
optimising out things, but Glenn pointed out the gradients
are meant to be clause local, so we should emit the texture
instructions in the same clause. This moves things around
to always copy to a temp and then emit the texture clauses
for H/V.

v2: Glenn pointed out we could get another ALU fetch in
the wrong place, so load the src gpr earlier as well.

Fixes at least:
./bin/tex-miplevel-selection textureGrad 2D

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-24 10:41:30 +10:00
Ilia Mirkin fecae4625c nv50,nvc0: buffer resources can be bound as other things down the line
res->bind is not an indicator of how the resource is currently bound.
buffers can be rebound across different binding points without changing
underlying storage.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
2014-11-23 15:43:28 -05:00
Ilia Mirkin e80a0a7d9a nv50,nvc0: actually check constbufs for invalidation
The number of vertex buffers has nothing to do with the number of bound
constbufs.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
2014-11-23 15:43:27 -05:00
Ilia Mirkin 7d07083cfd nv50/ir: set neg modifiers on min/max args
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=86618
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "10.4 10.3" <mesa-stable@lists.freedesktop.org>
2014-11-23 15:43:27 -05:00
Chris Forbes 89b9ef937c mesa: Fix function name in GetActiveUniformName error
Signed-off-by: Chris Forbes <chrisf@ijw.co.nz>
2014-11-23 15:04:15 +13:00
Stéphane Marchesin 3d9c1a9dd6 i915g: Fallback copy_render for ZS formats
These don't work out of the box, need more work, maybe with a proxy
format?

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:41 -08:00
Stéphane Marchesin 90207340c7 i915g: Add back 4444 and 5551 formats
Now that we have the transfers working, we can re-add those formats.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:40 -08:00
Stéphane Marchesin 1e47510df7 i915g: Don't limit blitter to POT textures
Now that we have NPOT support for u_blitter, there is no reason to
limit this any longer.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:40 -08:00
Stéphane Marchesin e30c799da9 i915g: Align all texture dimensions to the next POT
This creates a usable layout for all NPOT textures. Of course these
still have lots of limitations, but at least we can render to a
level.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:40 -08:00
Stéphane Marchesin 675019584c i915g: Fix typos
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:40 -08:00
Stéphane Marchesin 2ed24b2c31 i915g: Fix maxlod computation.
Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:39 -08:00
Stéphane Marchesin 0220a428d7 i915g: Fix offset for level != 0
For NPOT texture layouts, we want to be able to access texture levels
other than 0 directly. Since the hw doesn't support that, We do it by
adding the offset directly.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:39 -08:00
Stéphane Marchesin a9b0787076 i915g: Don't write constants past I915_MAX_CONSTANT
This happens with glsl-convolution-1, where we have 64 constants. This
doesn't make the test pass (we don't have 64 constants anyway, only
32) but this prevents it from crashing.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:39 -08:00
Stéphane Marchesin 5f61744adb i915g: Don't hardcode array size for phase count
This is an array of temp registers, so use I915_MAX_TEMPORARY for the size.

Signed-off-by: Stéphane Marchesin <marcheu@chromium.org>
2014-11-22 00:13:39 -08:00
David Heidelberg 25b00f4617 draw: allow LLVM use on non-SSE2 X86 cpus
This patch remove workaround related to LLVM < 3.2 bug.

Original bug has been closed as fixed in 2011.
At this moment gallium requires LLVM 3.3 (2013).

LLVM has been tested without SSE2 support in commit
ca70de9bd2 and removed after requiring
LLVM 3.3 in commit 013ff2fae1

Original LLVM bug: http://llvm.org/bugs/show_bug.cgi?id=6960

Signed-off-by: David Heidelberg <david@ixit.cz>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-11-22 04:29:00 +00:00
Emil Velikov 7d854c9771 docs: add news item and link release notes for mesa 10.3.4
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
2014-11-22 04:26:06 +00:00
Emil Velikov 34616bc922 docs: Add sha256 sums for the 10.3.4 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 72c27d7a3acc40b8a77a277f7cd975fb8e60dca5)
2014-11-22 04:24:32 +00:00
Emil Velikov 9e168ad903 Add release notes for the 10.3.4 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit 26c8ecd85dade7be5759c4de0b3916fbc186dc43)
2014-11-22 04:24:29 +00:00
Kenneth Graunke a746be259d i965: Make Gen4-5 push constants call _mesa_load_state_parameters too.
In commit 5e37a2a4a8, I made the pull constant code stop calling
_mesa_load_state_parameters() when there were no pull parameters.

This worked fine on Gen6+ because the push constant code also called
it if there were any push constants.  However, the Gen4-5 push constant
code wasn't doing this.  This patch makes it do so, like the Gen6+ code.

A better long term solution would be to make core Mesa just handle this
for us when necessary.

Fixes around 8766 Piglit tests on Ironlake, and probably Gen4 as well.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
2014-11-21 16:25:17 -08:00
Ben Widawsky 88fea85f09 i965/vec4/gen8: Handle the MUL dest hazard exception
Fix one of the few cases where we can't reliable touch the destination hazard
bits. I am explicitly doing this patch individually so it is easy to backport. I
was tempted to do this patch before the previous patch which reorganized the
code, but I believe even doing that first, this is still easy to backport.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-21 12:08:46 -08:00
Ben Widawsky 156f565f9e i965/vec4: Extract depctrl hazards
Move this to a separate function so that we can begin to add other little
caveats without making too big a mess.

NOTE: There is some desire to improve this function eventually, but we need to
fix a bug first.

v2:
Use const for the inst for the hazard check (Matt)
Invert safe logic to get rid of the double negative (Matt)
Add PRM reference for predicates (Matt)
Add note about empirical evidence for math (Matt)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-21 12:08:46 -08:00
Matt Turner 40c0d79d29 i965/fs: Remove is_valid_3src().
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-11-21 10:26:44 -08:00
Matt Turner 0777775274 i965/fs: Remove is_valid_3src() checks from emit_lrp.
The visitor emits MOVs to temporary registers for immediates, so these
never trigger. For further proof, check case ir_triop_fma.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-11-21 10:26:44 -08:00
Matt Turner 1fdc75fde4 i965/fs: Remove unused apply_stride().
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-11-21 10:26:44 -08:00
Matt Turner 279c1c80b6 i965/fs: Move ip_record class to its one use.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2014-11-21 10:26:44 -08:00
Matt Turner d9432af45a i965: Move common fields into backend_instruction.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-21 10:26:42 -08:00
Matt Turner bd50213929 i965: Combine offset/texture_offset fields.
texture_offset was only used by some texturing operations, and offset
was only used by spill/unspill and some URB operations. These fields are
never used at the same time.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-21 10:26:38 -08:00
Marek Olšák 645b471d61 radeonsi: use minnum and maxnum LLVM intrinsics for MIN and MAX opcodes
So far it has been compiled into pretty ugly code (8 instructions or so
for either opcode).

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2014-11-21 12:15:58 +01:00
Eric Anholt 21577571b3 vc4: Update for new kernel ABI with async execution and waits.
Our submits now return immediately and you have to manually wait for
things to complete if you want to (like a normal driver).
2014-11-20 13:07:07 -08:00
Ville Syrjälä 390799c496 i915: Only use TEXCOORDTYPE_VECTOR with cube maps on gen2
Check that the target is GL_TEXTURE_CUBE_MAP before emitting
TEXCOORDTYPE_VECTOR texture coordinates.

I'm not sure if the hardware would like CARTESIAN coordinates
with cube maps, and as I'm too lazy to find out just emit the
VECTOR coordinates for cube maps always. For other targets use
CARTESIAN or HOMOGENOUS depending on the number of texture
coordinates provided.

Fixes rendering of the "electric" background texture in chromium-bsu
main menu. We appear to be provided with three texture coordinates
there (I'm guessing due to the funky texture matrix rotation it does).
So the code would decide to use TEXCOORDTYPE_VECTOR instead of
TEXCOORDTYPE_CARTESIAN even though we're dealing with a 2D texure.
The results weren't what one might expect.

demos/cubemap still works, which hopefully indicates that this doesn't
break things.

Also tested with:
 bin/glean -o -v -v -v -t +texCube --quick
 bin/cubemap -auto
from piglit.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-20 21:58:57 +02:00
Ben Widawsky ca39c46c3b i965/disasm: Properly decode branch_ctrl (gen8+)
Add support for decoding the new branch control bit. I saw two things wrong with
the existing code.

1. It didn't bother trying to decode the bit.
-  While we do not *intentionally* emit this bit today, I think it's interesting
   to see if we somehow ended up with the bit set. It may also be useful in the
   future.

2. It seemed to be the wrong bit.
-  The docs are pretty poor wrt which bit this actually occupies. To me, it
   /looks/ like it should be bit 28. I am not sure where Ken got 30 from. I
   verified it should be 28 by looking at the simulator code.

I also added the most basic support for GOTO simply so we don't need to remember
to change the function in the future.

v2:
Move the branch_ctrl check out of the if gen >= 6 check to make it more
readable. (Matt)
ENDIF doesn't have branch_ctrl (Matt + Ken)

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2014-11-20 09:45:23 -08:00
José Fonseca 56bf948e11 rtasm,translate: Re-enable SSE on Mingw64.
This reverts f4dd099171.

The src/gallium/tests/unit/translate_test.c gives the same results on
MinGW 64-bits as on Linux 64-bits.  And since MinGW is often used for
development/testing due to its convenience, it's better not to have this
sort of differences relative to MSVC.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2014-11-20 14:11:36 +00:00
Kenneth Graunke 5e37a2a4a8 i965: Skip _mesa_load_state_parameters when there are zero parameters.
Saves a tiny bit of CPU overhead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Acked-by: Eric Anholt <eric@anholt.net>
2014-11-20 01:56:54 -08:00
Marek Olšák 6f7371619c radeonsi: remove unused variable si_state_dsa::db_render_control 2014-11-19 21:42:14 +01:00
Roland Scheidegger 763fc526c7 llvmpipe: enable PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
No changes required in the driver itself, all handled by draw.

piglit results in a quick run:
skip->pass 7
skip->fail 2
(The new failures in the ARB_fragment_layer_viewport group are expected,
we fail the same if gs doesn't write these outputs regardless of the vs.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-11-19 18:35:30 +01:00
Roland Scheidegger 4b6d6642d2 draw: fixes for vertex shaders outputting layer or viewport index
Mostly add a couple cases so we don't just check gs for this.
There's only one gotcha, the built-in vp transform in the llvm vs can't
handle it (this would be fixable though non-trivial due to vp index being
non-constant for the SoA outputs, but we don't use it if there's a gs
neither - the whole clip/vp transform integration there is suboptimal).

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2014-11-19 18:35:30 +01:00
Michael Varga 9460cd39e8 st/va: surface: render subpicture
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-19 09:29:11 -05:00
Michael Varga 7523db174e st/va: subpicture implementation
added BGRA format
create/destroy
set image
associate/deassociate

Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-19 09:29:11 -05:00
Michael Varga 05e225b558 st/va: added internal storage for VAImage and BGRA format
When calling vaCreateImage() an internal copy of VAImage is maintained
since the allocation of "image" may not be guaranteed to live long enough.

Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-19 09:29:11 -05:00
Michael Varga 7b4f233c1f st/va: added some calls to handle_table_remove()
In a few locations handles were being added but not removed.

Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-19 09:29:10 -05:00
Chad Versace b69c7c5dac i965: Fix segfault in WebGL Conformance on Ivybridge
Fixes regression of WebGL Conformance test texture-size-limit [1] on
Ivybridge Mobile GT2 0x0166 with Google Chrome R38.

Regression introduced by

    commit 6c04423153
    Author: Kenneth Graunke <kenneth@whitecape.org>
    Date:   Sun Feb 2 02:58:42 2014 -0800

        i965: Bump GL_MAX_CUBE_MAP_TEXTURE_SIZE to 8192.

The test regressed because the pointer offset arithmetic in
intel_miptree_map_gtt() overflows for large textures. The pointer
arithmetic is not 64-bit safe.

[1] 52f0dc240f/sdk/tests/conformance/textures/texture-size-limit.html

Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=78770
Fixes: Intel CHRMOS-1377
Reported-by: Lu Hua <huax.lu@intel.com>
Reviewed-by: Ian Romanic <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2014-11-18 19:16:45 -08:00
Siavash Eliasi 80bffde0a2 mesa/main: Fix tmp_row memory leak in texstore_rgba_integer.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-18 14:55:39 -08:00
Jason Ekstrand d76be6bd60 docs/GL3: Mark GL_ARB_direct_state_access as being started by Laura 2014-11-18 14:54:12 -08:00
Dave Airlie 1830138cc0 r600g: limit texture offset application to specific types (v2)
For 1D and 2D arrays we don't want the other coordinates being
offset and affecting where we sample. I wrote this patch 6 months
ago but lost it.

Fixes:
./bin/tex-miplevel-selection textureLodOffset 1DArray
./bin/tex-miplevel-selection textureLodOffset 2DArray
./bin/tex-miplevel-selection textureOffset 1DArray
./bin/tex-miplevel-selection textureOffset 1DArrayShadow
./bin/tex-miplevel-selection textureOffset 2DArray
./bin/tex-miplevel-selection textureOffset(bias) 1DArray
./bin/tex-miplevel-selection textureOffset(bias) 2DArray

v2: rewrite to handle more cases and be consistent with code
above.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-19 08:22:13 +10:00
Dave Airlie d4c342f67e r600g: geom shaders: always load texture src regs from inputs
Otherwise we seem to lose the split_gs_inputs and try and
pull from an uninitialised register.

fixes 9 texelFetch geom shader tests.

Reviewed-by: Glenn Kennard <glenn.kennard@gmail.com>
Cc: "10.3 10.4" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2014-11-19 08:21:40 +10:00
Eric Anholt 82e919d33b vc4: Emit semaphore instructions for new kernel ABI.
Previously, the kernel would dispatch thread 0, wait, then dispatch thread
1.  By insisting that the thread contents use semaphores in the right
place, the kernel can sleep for longer by dispatching both threads at
once.
2014-11-18 12:46:55 -08:00
Eric Anholt 05f165b62d vc4: Mark a big array as const.
Drops 1kb of code from this inner loop, in exchange for 2.5k of data.
2014-11-18 12:42:52 -08:00
Andres Gomez 1398ed724a glsl_compiler: Add binding hash tables to avoid SIGSEVs on linking stage
When using the stand alone compiler, if we try to link a shader with vertex
attributes it will segfault on linking as the binding hash tables are not
included in the shader program. Obviously, we cannot make the linking stage
succeed without the bound attributes but we can prevent the crash and just
let the linker spit its own error.

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-11-18 08:47:04 -07:00