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i965/vec4/gen8: Handle the MUL dest hazard exception 

Fix one of the few cases where we can't reliable touch the destination hazard
bits. I am explicitly doing this patch individually so it is easy to backport. I
was tempted to do this patch before the previous patch which reorganized the
code, but I believe even doing that first, this is still easy to backport.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=84212
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>
This commit is contained in:
Ben Widawsky 2014-11-21 10:47:41 -08:00
parent 156f565f9e
commit 88fea85f09
2 changed files with 19 additions and 2 deletions
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20
src/mesa/drivers/dri/i965/brw_vec4.cpp
View File

@ -841,9 +841,25 @@ vec4_visitor::move_push_constants_to_pull_constants()
}
/* Conditions for which we want to avoid setting the dependency control bits */
static bool
is_dep_ctrl_unsafe(const vec4_instruction *inst)
bool
vec4_visitor::is_dep_ctrl_unsafe(const vec4_instruction *inst)
{
#define IS_DWORD(reg) \
(reg.type == BRW_REGISTER_TYPE_UD || \
reg.type == BRW_REGISTER_TYPE_D)
/* From the destination hazard section of the spec:
* > Instructions other than send, may use this control as long as operations
* > that have different pipeline latencies are not mixed.
*/
if (brw->gen >= 8) {
if (inst->opcode == BRW_OPCODE_MUL &&
IS_DWORD(inst->src[0]) &&
IS_DWORD(inst->src[1]))
return true;
}
#undef IS_DWORD
/*
* mlen:
* In the presence of send messages, totally interrupt dependency

1
src/mesa/drivers/dri/i965/brw_vec4.h
View File

@ -390,6 +390,7 @@ public:
bool opt_cse();
bool opt_algebraic();
bool opt_register_coalesce();
bool is_dep_ctrl_unsafe(const vec4_instruction *inst);
void opt_set_dependency_control();
void opt_schedule_instructions();