Commit Graph

66508 Commits

Author SHA1 Message Date
José Fonseca 13849f327c st/wgl: Implement WGL_EXT_create_context_es/es2_profile.
Derived from st/glx's GLX_EXT_create_context_es/es2_profile implementation.

Tested with an OpenGL ES 2.0 ApiTrace.

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-11-14 23:29:59 +00:00
José Fonseca d5d41112cb st/xlib: Generate errors as specified.
Tested with piglit glx tests.

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-11-14 23:29:59 +00:00
Rob Clark 82103206fe freedreno/ir3: move some helpers
Split out a few helpers from fd3_program so we don't have to duplicate
for fd4_program.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-11-14 13:59:54 -05:00
Rob Clark e091c08089 freedreno: rename draw->draw_vbo
Gets rid of a namespace conflict w/ a4xx which wants an fd4_draw()
version of fd_draw()..

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-11-14 13:59:31 -05:00
Rob Clark 2f024d2b10 freedreno/a3xx: missing u_upload_destroy
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-11-14 12:07:57 -05:00
Rob Clark 28b2269ee0 freedreno: fix borked check for a320.0
Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-11-14 12:07:39 -05:00
Rob Clark 8b898c1174 freedreno/ir3: half vs full reg in standalone compiler output
Handle hrN.c in printing outputs/inputs.

Signed-off-by: Rob Clark <robclark@freedesktop.org>
2014-11-14 12:02:43 -05:00
José Fonseca 7037793f6b st/dri: Support EGL_CONTEXT_OPENGL_DEBUG_BIT_KHR/GLX_CONTEXT_DEBUG_BIT_ARB on ES contexts.
The latest version of the specs explicitly allow it, and given that Mesa
universally supports KHR_debug we should definitely support it.

Totally untested.  (Just happened to noticed this while implementing
GLX_EXT_create_context_es2_profile for st/xlib.)

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2014-11-14 16:10:22 +00:00
Marek Olšák 363b53f000 egl: remove egl_gallium from the loader
Acked-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Informally acked-by: Jose Fonseca
2014-11-14 16:16:12 +01:00
Marek Olšák c46c551c56 configure.ac: remove enable flags for EGL and GBM Gallium state trackers
Acked-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
Informally acked-by: Jose Fonseca
2014-11-14 16:16:12 +01:00
Kenneth Graunke bd20fad316 i965/vec4: Combine all the math emitters.
17 insertions(+), 102 deletions(-).  Works just as well.

v2: Make emit_math take const references (suggested by Matt),
    drop redundant WRITEMASK_XYZW setting (Matt and Curro).

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-13 20:55:41 -08:00
Kenneth Graunke dba683cf16 i965/vec4: Use const references in emit() functions.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-13 20:55:41 -08:00
Kenneth Graunke 0efc53a96c i965: Use macros to create prototypes for emitter helpers.
We do this almost everywhere else; this should make it easier to modify.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2014-11-13 20:55:41 -08:00
Ben Widawsky f14a35f9dc i965: Always enable VF statistics
Every other unit in the geometry pipeline automatically enables
statistics gathering. This part of the pipe has been controlled by the
DEBUG_STATS variable, but this is asymmetric. This dates back to the
original implementation, and I am not sure if there is a reason for it.

I need access to these stats to implement ARB_pipeline_statistics_query.

Eric wrote it, and Ken touched it last. Do you have any opposition?

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=86145
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
2014-11-13 10:48:24 -08:00
Ville Syrjälä 0d924738d9 i915: Emit 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE
According to gen2 BSpec the pipeline must be flushed at least up to the
windower before changing the scissor rect enable field. Emitting the
3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient
to do that.

gen3 BSpec no longer has that piece of text, but let's make the same
change there too for symmetry. The spec does still say that the scissor
rectangle must be defined before enabling it, so the new order does seem
more in line with the spec.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-13 19:13:27 +02:00
Ville Syrjälä 81c31e560f i915: Don't call _mesa_meta_glsl_Clear() on gen2
Gen2 doesn't have fragment shaders so we shouldn't be calling
_mesa_meta_glsl_Clear() on gen2. Restore the appropriate
ARB_fragment_shader check to the clear path which was lost in:

 commit 94f22fbe78
 Author: Tapani Pälli <tapani.palli@intel.com>
 Date:   Wed Aug 8 20:46:45 2012 +0300

    intel: use _mesa_meta_Clear with OpenGL ES 1.1 v2

v2: Fix spelling in commit message

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-13 19:13:27 +02:00
Ville Syrjälä 4747b2638c i915: Protect macro argument for TEXTURE_SET()
TEXTURE_SET() is the only register macro that forgets to wrap the
argument evaluation in parens. Only simple integers are passed to this
macro so there's no bug but sitll it seems prudent to add the
parens.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-13 19:13:27 +02:00
Ville Syrjälä 3746ff89bc i915: Kill intel_context::hw_stencil
ctx.hw_stencil is not used anywhere so kill it.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-13 19:13:27 +02:00
Ville Syrjälä dafae910d4 i915: Accept GL_DEPTH_STENCIL GL_DEPTH_COMPONENT formats for renderbuffers
Gen2 doesn't support depth/stencil textures, and since

 commit c1d4d49993
 Author: Ville Syrjälä <ville.syrjala@linux.intel.com>
 Date:   Thu Apr 24 14:11:43 2014 +0300

    i915: Don't advertise Z formats in TextureFormatSupported on gen2

depth/stencil formats are no longer accepted as texture formats.
However we still want depth/stencil renderbuffers, so add explicit
format checks to intel_alloc_renderbuffer_storage() to allow such
things.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-13 19:13:27 +02:00
Ville Syrjälä a071425817 i915: Override mip filter to nearest with aniso
gen2 doesn't supporte linear mip filter with anisotropic min/mag
filtering. The hardware would automagically downgrade the min/mag
filters to linear in such cases, which IMO looks worse than forcing
the mip filter to nearest.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-13 19:13:27 +02:00
Ville Syrjälä 40a08e0d6a i915: Use L8A8 instead of I8 to simulate A8 on gen2
Gen2 doesn't support the A8 texture format. Currently the driver
substitutes it with I8, but that results in incorrect RGB values.
Use A8L8 instead. We end up wasting a bit of memory, but at least
we should get the correct results.

v2: Handle the fallback in _mesa_choose_tex_format() and also
    do it for all alpha formats that currently accept A8

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72819
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=80050
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38873
Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-13 19:13:27 +02:00
Ville Syrjälä 7988ff2fd1 i915: Fix GL_DOT3_RGBA a bit
The spec says using DOT4 for alpha is undefined unless DOT4 is also used
for color. It seems to do the right thing anyway, but better safe than sorry.

Also override numAlphaArgs to 2 for DOT4 since that's what it wants.
This migth fix something in case the specified alpha mode has only one
argument. Also avoids emitting a needless 3DSTATE_MAP_BLEND_ARG if
the specified alpha mode has three arguments.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
2014-11-13 19:13:27 +02:00
Neil Roberts 352f8f2d13 linker: Add a missing space in an error message
Reviewed-by: Brian Paul <brianp@vmware.com>
2014-11-13 16:46:12 +00:00
José Fonseca d5b1731178 llvmpipe: Call pipe_thread_wait() on Linux.
To address http://lists.freedesktop.org/archives/mesa-dev/2014-November/070569.html

In short, revert 706ad3b649 for non-Windows
OSes.
2014-11-13 15:01:19 +00:00
Kenneth Graunke 2b6e703863 i915g: we also have more than 0 viewports!
See 546d6c8d for the corresponding fix in freedreno.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Stephane Marchesin <stephane.marchesin@gmail.com>
Cc: "10.3" <mesa-stable@lists.freedesktop.org>
2014-11-12 20:59:28 -08:00
Eric Anholt b3d269f5ae vc4: Avoid reusing a pointer from c->outputs[] after add_output().
add_output() can resize the qreg array, so we might use a stale pointer.
2014-11-12 18:24:10 -08:00
Eric Anholt acc1cca7ae vc4: Fix assumption of TGSI OUT[0] being POSITION in the VS.
All the shaders we've received so far had this be the case, but with
nir-to-tgsi that changed.

I might decide to make nir-to-tgsi keep the outputs in the same order, for
debugging sanity, but I'm not sure.
2014-11-12 18:23:40 -08:00
Ilia Mirkin 22543dd8a1 nvc0: remove unused mm_VRAM_fe0
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
2014-11-12 15:24:15 -05:00
José Fonseca 9247509a8d st/glx: Implement GLX_EXT_create_context_es2_profile.
apitrace now supports it, and it makes it much easier to test
tracing/replaying on OpenGL ES contexts since
GLX_EXT_create_context_{es2,es}_profile are widely available.

Reviewed-by: Brian Paul <brianp@vmware.com>
2014-11-12 19:03:50 +00:00
Tom Stellard 0cae7ea271 Revert "clover: Fix build after llvm r221375"
This reverts commit cd93d82ba9.

llvm r221375 was reverted, so this commit needs to be too.
2014-11-12 12:30:08 -05:00
José Fonseca 977b18e486 gallivm: Fix build with LLVM 3.6 (r221751).
Tested with LLVM 3.3, 3.4, 3.5, and 3.6.

Trivial.
2014-11-12 11:08:07 +00:00
Matt Turner 7a82961b71 i965/cfg: Remove if_block/else_block.
I used these in the SEL peephole, but they require extra tracking and
fix ups. The SEL peephole can pretty easily find the blocks it needs
without these.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-11 09:41:06 -08:00
Matt Turner 4001181ba3 i965/fs: Don't use if_block/else_block in SEL peephole.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2014-11-11 09:41:06 -08:00
Chia-I Wu 20a061d2b4 ilo: clean up gen6_3DSTATE_SF()
Make the helpers fill out valid Gen7 3DSTATE_SF and 3STATE_SBE.  This
prevents the helpers from having to do

  dw[0] = GEN7_SBE_DW1_x; // setting DW1 value to dw[0]!?

and simplifies gen7_3DSTATE_{SF,SBE}().

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 16:04:18 +08:00
Chia-I Wu 239dca78b1 ilo: clean up gen7_3DSTATE_STREAMOUT()
Render stream and render enable are independent from so enable.  Having a
single return point makes it easier to see that.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:26 +08:00
Chia-I Wu eab595d573 ilo: rework gen7_3DSTATE_SO_DECL_LIST()
Started to make pipe_stream_output_info mandatory, but ended up adding support
for stream id and making a workaround Gen7-specific.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:26 +08:00
Chia-I Wu c637075ea2 ilo: add 3DSTATE_SO_BUFFER variants
Add gen7_disable_3DSTATE_SO_BUFFER() to disable SO buffers.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:25 +08:00
Chia-I Wu 2ff88ce4be ilo: add gen6_3dstate_constant()
It replaces gen6_fill_3dstate_constant().  gen6_3DSTATE_CONSTANT_{VS,GS,PS}
are made wrappers of the new function.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:25 +08:00
Chia-I Wu 31372f2d2c ilo: add variants of 3DSTATE_{HS,DS}
Rename them to gen7_disable_3DSTATE_{HS,DS}() to reflect the fact.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:25 +08:00
Chia-I Wu 421b565b3b ilo: add variants of 3DSTATE_GS
Add gen6_so_3DSTATE_GS(), gen6_disable_3DSTATE_GS(), and
gen7_disable_3DSTATE_GS() to do SO on GEN6 or to disable GS.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:52:22 +08:00
Chia-I Wu 63ded78e1c ilo: add variants of 3DSTATE_VS
Add gen6_disable_3DSTATE_VS() to disable VS.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:51:36 +08:00
Chia-I Wu 9087239df8 ilo: add variants of 3DSTATE_PS
Add gen7_disable_3DSTATE_PS() to disable PS.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:51:31 +08:00
Chia-I Wu 8ebb86325b ilo: add variants of 3DSTATE_WM
Add gen6_hiz_3DSTATE_WM() and gen7_hiz_3DSTATE_WM() for HiZ ops without
dispatching.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:51:28 +08:00
Chia-I Wu 703ae84ac2 ilo: add variants of 3DSTATE_CLIP
Add gen6_disable_3DSTATE_CLIP to disable clipping.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 13:51:21 +08:00
Chia-I Wu 8abf4976c6 ilo: prefix 3DSTATE_VF with gen75
3DSTATE_VF is Gen7.5+ only.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
2014-11-11 09:11:56 +08:00
Michael Varga 9d6253cf82 st/va: MPEG4 call vlVaDecoderFixMPEG4Startcode()
If the VOP and GOV headers were truncated they will be regenerated.

Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga d335f5ffa6 st/va: MPEG4 generate GOV and VOP header
Also, Implemented a small locally used interface for writing bits to a buffer.

Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga fa9e461967 st/va: MPEG4 populate the SPS structure
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga 92350a65c4 st/va: MPEG4 populate the iq matrix buffers
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00
Michael Varga 9f1ee1b5c9 st/va: MPEG4 populate the PPS structure
Signed-off-by: Michael Varga <Michael.Varga@amd.com>
2014-11-10 10:24:07 -05:00