nvc0/ir: add initial code to support GK110 ISA encoding

src/gallium/drivers/nv50/codegen/nv50_ir_driver.h

@@ -93,6 +93,11 @@ struct nv50_ir_prog_symbol
    uint32_t offset;
 };
 
+#define NVISA_GF100_CHIPSET_C0 0xc0
+#define NVISA_GF100_CHIPSET_D0 0xd0
+#define NVISA_GK104_CHIPSET    0xe0
+#define NVISA_GK110_CHIPSET    0xf0
+
 struct nv50_ir_prog_info
 {
    uint16_t target; /* chipset (0x50, 0x84, 0xc0, ...) */

src/gallium/drivers/nv50/codegen/nv50_ir_inlines.h

@@ -73,6 +73,31 @@ static inline unsigned int typeSizeof(DataType ty)
    }
 }
 
+static inline unsigned int typeSizeofLog2(DataType ty)
+{
+   switch (ty) {
+   case TYPE_F16:
+   case TYPE_U16:
+   case TYPE_S16:
+      return 1;
+   case TYPE_F32:
+   case TYPE_U32:
+   case TYPE_S32:
+      return 2;
+   case TYPE_F64:
+   case TYPE_U64:
+   case TYPE_S64:
+      return 3;
+   case TYPE_B96:
+   case TYPE_B128:
+      return 4;
+   case TYPE_U8:
+   case TYPE_S8:
+   default:
+      return 0;
+   }
+}
+
 static inline DataType typeOfSize(unsigned int size,
                                   bool flt = false, bool sgn = false)
 {

src/gallium/drivers/nv50/codegen/nv50_ir_ra.cpp

@@ -1907,6 +1907,7 @@ RegAlloc::InsertConstraintsPass::visit(BasicBlock *bb)
             texConstraintNVC0(tex);
             break;
          case 0xe0:
+         case NVISA_GK110_CHIPSET:
             texConstraintNVE0(tex);
             break;
          default:

src/gallium/drivers/nv50/codegen/nv50_ir_target.cpp

@@ -121,6 +121,7 @@ Target *Target::create(unsigned int chipset)
    case 0xc0:
    case 0xd0:
    case 0xe0:
+   case NVISA_GK110_CHIPSET:
       return getTargetNVC0(chipset);
    case 0x50:
    case 0x80:

src/gallium/drivers/nvc0/Makefile.sources

@@ -16,6 +16,7 @@ C_SOURCES := \
 	nvc0_query.c
 
 CPP_SOURCES := \
+	codegen/nv50_ir_emit_gk110.cpp \
 	codegen/nv50_ir_emit_nvc0.cpp \
 	codegen/nv50_ir_lowering_nvc0.cpp \
 	codegen/nv50_ir_target_nvc0.cpp

src/gallium/drivers/nvc0/codegen/nv50_ir_emit_nvc0.cpp

@@ -2298,6 +2298,13 @@ SchedDataCalculator::recordRd(const Value *v, const int ready)
    }
 }
 
+bool
+calculateSchedDataNVC0(const Target *targ, Function *func)
+{
+   SchedDataCalculator sched(targ);
+   return sched.run(func, true, true);
+}
+
 void
 CodeEmitterNVC0::prepareEmission(Function *func)
 {
@@ -2305,10 +2312,8 @@ CodeEmitterNVC0::prepareEmission(Function *func)
 
    CodeEmitter::prepareEmission(func);
 
-   if (targ->hasSWSched) {
-      SchedDataCalculator sched(targ);
-      sched.run(func, true, true);
-   }
+   if (targ->hasSWSched)
+      calculateSchedDataNVC0(targ, func);
 }
 
 CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
@@ -2321,11 +2326,19 @@ CodeEmitterNVC0::CodeEmitterNVC0(const TargetNVC0 *target)
 }
 
 CodeEmitter *
-TargetNVC0::getCodeEmitter(Program::Type type)
+TargetNVC0::createCodeEmitterNVC0(Program::Type type)
 {
    CodeEmitterNVC0 *emit = new CodeEmitterNVC0(this);
    emit->setProgramType(type);
    return emit;
 }
 
+CodeEmitter *
+TargetNVC0::getCodeEmitter(Program::Type type)
+{
+   if (chipset >= NVISA_GK110_CHIPSET)
+      return createCodeEmitterGK110(type);
+   return createCodeEmitterNVC0(type);
+}
+
 } // namespace nv50_ir

src/gallium/drivers/nvc0/codegen/nv50_ir_lowering_nvc0.cpp

@@ -157,7 +157,7 @@ private:
    const Instruction *recurseDef(const Instruction *);
 
 private:
-   LValue *r63;
+   LValue *rZero;
    const bool needTexBar;
 };
 
@@ -467,8 +467,8 @@ NVC0LegalizePostRA::visit(Function *fn)
    if (needTexBar)
       insertTextureBarriers(fn);
 
-   r63 = new_LValue(fn, FILE_GPR);
-   r63->reg.data.id = 63;
+   rZero = new_LValue(fn, FILE_GPR);
+   rZero->reg.data.id = prog->getTarget()->getFileSize(FILE_GPR);
    return true;
 }
 
@@ -478,7 +478,7 @@ NVC0LegalizePostRA::replaceZero(Instruction *i)
    for (int s = 0; i->srcExists(s); ++s) {
       ImmediateValue *imm = i->getSrc(s)->asImm();
       if (imm && imm->reg.data.u64 == 0)
-         i->setSrc(s, r63);
+         i->setSrc(s, rZero);
    }
 }
 
@@ -556,7 +556,7 @@ NVC0LegalizePostRA::visit(BasicBlock *bb)
          if (!i->getDef(0)->refCount())
             i->setDef(0, NULL);
          if (i->src(0).getFile() == FILE_IMMEDIATE)
-            i->setSrc(0, r63); // initial value must be 0
+            i->setSrc(0, rZero); // initial value must be 0
       } else
       if (i->isNop()) {
          bb->remove(i);

src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.cpp

@@ -334,7 +334,7 @@ TargetNVC0::getFileSize(DataFile file) const
 {
    switch (file) {
    case FILE_NULL:          return 0;
-   case FILE_GPR:           return 63;
+   case FILE_GPR:           return (chipset >= NVISA_GK110_CHIPSET) ? 255 : 63;
    case FILE_PREDICATE:     return 7;
    case FILE_FLAGS:         return 1;
    case FILE_ADDRESS:       return 0;
@@ -392,7 +392,7 @@ TargetNVC0::insnCanLoad(const Instruction *i, int s,
 {
    DataFile sf = ld->src(0).getFile();
 
-   // immediate 0 can be represented by GPR $r63
+   // immediate 0 can be represented by GPR $r63/$r255
    if (sf == FILE_IMMEDIATE && ld->getSrc(0)->reg.data.u64 == 0)
       return (!i->asTex() && i->op != OP_EXPORT && i->op != OP_STORE);
 

src/gallium/drivers/nvc0/codegen/nv50_ir_target_nvc0.h

@@ -38,6 +38,9 @@ public:
 
    virtual CodeEmitter *getCodeEmitter(Program::Type);
 
+   CodeEmitter *createCodeEmitterNVC0(Program::Type);
+   CodeEmitter *createCodeEmitterGK110(Program::Type);
+
    virtual bool runLegalizePass(Program *, CGStage stage) const;
 
    virtual void getBuiltinCode(const uint32_t **code, uint32_t *size) const;
@@ -64,7 +67,8 @@ public:
 
 private:
    void initOpInfo();
-
 };
 
+bool calculateSchedDataNVC0(const Target *, Function *);
+
 } // namespace nv50_ir