Commit Graph

93730 Commits

Author SHA1 Message Date
Marek Olšák a2b02c4948 gallium/radeon: fix VDPAU breakage, need VRAM with WC 2017-07-05 01:14:48 +02:00
Ilia Mirkin 1e73fc6b1a a5xx: enable polygon offset clamps
This is already set and emitted by the code.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin def1b94c33 a5xx: implement logicop support
The former 0x60 hardcoded in is equivalent to ROP_COPY with the shift.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin abe8740e33 a5xx: enable polygon mode selection
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin 8108b56023 a5xx: disable ARB_depth_clamp for now
We need to figure out how to implement it properly. Right now it doesn't
work at all.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin 5d9d1df183 a5xx: fix clip_halfz support
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin 02379b68f6 a5xx: improve 3d texture sampling
At least the first level works now. Eventually the later levels stop
working, there appears to be some alignment issue. But this improves the
situation immensely.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin c0f1efe04d a5xx: remove one of the MIPFILTER_LINEAR bits
It doesn't appear to do what we want. Removing this bit makes
lodclamp-between as well as a number of dEQP tests pass, with no visible
ill effect.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin f1fc619bd8 a5xx: enable formats newly added to the headers
This enables S3TC, BPTC, ETC2, and ASTC texture decoding. Additionally
this enables RGB32 texture buffer objects, as well as 11_11_10_FLOAT and
10_10_10_2 vertex formats (and related extensions).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin b68e22d5e2 a5xx: include color swap when decoding vertices
This fixes support for BGRA vertex formats

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Ilia Mirkin 5fdcddbeb4 a5xx: update headers
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Acked-by: Rob Clark <robdclark@gmail.com>
2017-07-04 18:27:57 -04:00
Marek Olšák 156832ee2b gallium/radeon: attempt to fix a compiler failure in radeon_winsys.h
trivial.
2017-07-04 22:40:35 +02:00
Marek Olšák 0591df025b winsys/amdgpu: use 128KB BOs for suballocations of up to 64KB BOs
This decreases the number of BOs, but might also increase memory usage.
It's better for small textures.

The gameplay is on the far right:
https://people.freedesktop.org/~mareko/suballoc.svg

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák c784015643 gallium/radeon: allow suballocating textures
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák 23446eedd1 gallium/radeon: generalize the function for in-place texture reallocation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák 91f72975ac gallium/radeon: add radeon_winsys::buffer_is_suballocated
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák 0f13451da3 gallium/radeon: clean up pb_cache bucket/usage determination
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák d4fac1e1d7 gallium/radeon: enable suballocations for VRAM with no CPU access
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák 64e5577cac gallium/radeon: clean up (domain, flags) <-> (slab heap) translations
This is cleaner, and we are down to 4 slabs.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák b09a22ad21 gallium/radeon: remove RADEON_FLAG_CPU_ACCESS
https://lists.freedesktop.org/archives/amd-gfx/2017-June/010591.html

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák 03c5ef195d gallium/radeon: disallow exports of sparse and suballocated BOs
I think it's unsafe, because the slabs can reuse exported storage.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák 047c34f0ac gallium/radeon: clean up r600_texture_get_handle
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák 7525c3e123 gallium/radeon: rename RADEON_FLAG_HANDLE -> RADEON_FLAG_NO_SUBALLOC
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák e6dbe975ef gallium/radeon: fix a possible crash for buffer exports
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák fee2883bd7 gallium/radeon: ignore PIPE_BIND_SHARED for buffers
BO exports can't be predicted this way.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Marek Olšák 5b373629fc radeonsi: add a HUD query for getting an average GFX BO list size
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-04 15:40:37 +02:00
Philipp Zabel 7d7bcd65d6 st/mesa: release EGLImage on EGLImageTarget* error
The smapi->get_egl_image() call in st_egl_image_get_surface() stores a
reference to the EGLImage's texture in stimg.texture. That reference is
released via pipe_resource_reference(&stimg.texture, NULL) before stimg
goes out of scope at the end of the function, but not in the error path
if !is_format_supported().

Fixes: 83e9de25f3 ("st/mesa: EGLImageTarget* error handling")
Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-04 11:05:40 +02:00
Juan A. Suarez Romero 2c240a7205 vc4: automake: include vc4_cl_dump.h in
Ensure vc4_cl_dump.h and $(BROADCOM_FILES) are distributed in the
dist-file.

This fixes `make distcheck`

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-07-04 09:37:19 +02:00
Marek Olšák 11a924c174 st/mesa: fix tessellation shaders with no support for shareable shaders
Broken by: b43c887a9b

Reported by Gert Wollny.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-07-03 23:08:28 +02:00
Dave Airlie 1bc40ae952 radv: enable Int64 capability (v2)
I'm not 100% sure this is all wired up but it looks like it is.

v2: actually enable extension.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-07-03 11:58:59 -07:00
Connor Abbott 2ec77f7a3c ac/nir: fix 64-bit shifts
NIR always makes the shift amount 32 bits, but LLVM asserts if the two
sources aren't the same type. Zero-extend the shift amount to make LLVM
happy.

Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-07-03 11:58:59 -07:00
Connor Abbott 7168425dd7 ac/nir: implement 64-bit packing and unpacking
We implement the split opcodes, and tell NIR to lower the original ones.
The lowering to LLVM is a little more complicated, but NIR can optimize
the split ones a little better, and some NIR lowering passes that we
might want to use (particularly for doubles) emit the split ones.

This should fix pack/unpackDouble2x32, which seems like a bug since when
we enabled the Float64 capability. It will also fix pack/unpackInt2x32
when we enable the Int64 capability.

Fixes: 798ae37c ("radv: Enable Float64 support.")
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-07-03 11:58:58 -07:00
Connor Abbott 196e6b60b1 spirv: fix OpBitcast when the src and dst bitsize are different (v3)
Before, we were just implementing it with a move, which is incorrect
when the source and destination have different bitsizes. To implement
it properly, we need to use the 64-bit pack/unpack opcodes. Since
glslang uses OpBitcast to implement packInt2x32 and unpackInt2x32, this
should fix them on anv (and radv once we enable the int64 capability).

v2: make supporting non-32/64 bit easier (Jason)
v3: add another assert (Jason)

Fixes: b3135c3c ("anv: Advertise shaderInt64 on Broadwell and above")
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-03 11:58:50 -07:00
Brian Paul 6158c0b5d8 svga: don't call svga_texture_device_format_has_alpha() for PIPE_BUFFER
svga_texture_device_format_has_alpha() is only intended to work for
texture resources, not buffer resources.  This fixes a failed assertion
in the svga_texture() cast function when running texture buffer tests.

Also, add an assertion in svga_texture_device_format_has_alpha() to
catch the issue sooner.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-07-03 10:10:14 -06:00
Brian Paul e6d1cc31fa svga: fix texture buffer object regression
With change 8aba778fa2 we stopped binding
sampler objects for texture buffers.  That broke our texture sample /
sampler view setup code.

Now, we loop over the max(num samplers, num sampler views) and handle
the sampler and view information separately.  For texture buffers,
the sampler will be NULL but the sampler view non-null.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-07-03 10:10:13 -06:00
Brian Paul 6b4bf7e8be svga: move assertion in draw_vgpu10()
The buffer binding flags aren't ensured until after the
svga_buffer_handle() call, so move the assertion after it.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-07-03 10:10:13 -06:00
Brian Paul 9bd047aa26 svga: fix buffer binding flags initialization
If a buffer is created/initialized with glNamedBufferData we will
have no target (GL_ARRAY_BUFFER, GL_UNIFORM_BUFFER, etc) so the
svga_buffer::bind_flags will be zero until we try to get the buffer
handle.

This patch initializes the svga_buffer::bind_flags field when it's
zero.

This fixes the Piglit arb_uniform_buffer_object-rendering-dsa test.

Note that there's still issues in this area that'll have to be
addressed in the future.  For example, creating a buffer object
as GL_UNIFORM_BUFFER and later using it as a vertex buffer will
fail.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-07-03 10:10:11 -06:00
Brian Paul 8e4559b3fc docs: update bug reporting guidelines
Suggest attaching output of glxinfo/wglinfo.  Suggest providing
an apitrace.
2017-07-03 08:14:08 -06:00
Nicolai Hähnle 2f89c39861 st/mesa: remove an obsolete comment
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-07-03 13:57:01 +02:00
Nicolai Hähnle 7c5b204e38 mesa: remove unused parameter/member of add_uniform_to_shader
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-07-03 13:57:01 +02:00
Nicolai Hähnle 8988571824 util/disk_cache: fix a comment
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-07-03 13:57:01 +02:00
Nicolai Hähnle da506cce8a glsl: simplify disable_varying_optimizations_for_sso
We always have stage == first and stage == last when first == last, so
drop the special case. Also rephrase the comment to make the logic
clearer.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-07-03 13:54:20 +02:00
Nicolai Hähnle 141d0831ff glsl: always print non-zero var->data.location_frac
This is helpful in debugging varying assignments.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2017-07-03 13:54:06 +02:00
Nicolai Hähnle b0b4b5e8f7 winsys/radeon: only call pb_slabs_reclaim when slabs are actually used
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=100242
Fixes: fb827c055c ("winsys/radeon: enable buffer allocation from slabs")
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-07-03 12:39:41 +02:00
Samuel Iglesias Gonsálvez 5dd96b1156 anv: check support for enabled features in vkCreateDevice()
From Vulkan spec, 4.2.1. "Device Creation":

  "vkCreateDevice verifies that extensions and features requested in
   the ppEnabledExtensionNames and pEnabledFeatures members of
   pCreateInfo, respectively, are supported by the implementation."

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@gmail.com>
2017-07-03 08:01:31 +02:00
Samuel Iglesias Gonsálvez ba05f6f72b anv: merge tessellation's primitive mode in merge_tess_info()
SPIR-V tessellation shaders that were created from HLSL will have
the primitive generation domain set in tessellation control shader
(hull shader in HLSL) instead of the tessellation evaluation shader.

v2:
- Add assert (Kenneth)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-07-03 08:00:43 +02:00
Bruce Cherniak 32c1a54bd0 swr: Limit memory held by defer deleted resources.
This patch limits the number of items on the fence work queue (the
deferred deletion list) by submitting a sync fence when the queue size
exceeds a threshold.  This initiates deferred deletion of all resources
on the list and decreases the total amount of memory held waiting for
"deferred deletion".

This resolves  bug 101467 filed against swr for the piglit
streaming-texture-leak test.  For those running on smaller memory
(16GB?) systems, this will prevent oom-killer.

Thus far, we have not seen any real world applications that exhibit
behavior like the streaming-texture-leak test; as any form of pipeline
flush will trigger the defer queue and properly free any retained
allocations.  But, this addresses those as well.

Cc: "17.1" <mesa-stable@lists.freedesktop.org>

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
2017-07-02 17:38:57 -05:00
Lionel Landwerlin 038c45a40e anv: fix reported timestampPeriod value
We lost some precision on a previous change due to switching to
integers. Since we report a float in timestampPeriod, we want the
division to happen in floats.

CID: 1413021
Fixes: c77d98ef32 ("intel: common: express timestamps units in frequency")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-07-02 12:11:55 +01:00
Lionel Landwerlin 34560ba9e5 intel: genxml: make a couple of enums show up in aubinator
In particular Shader Channel Select & Texture Address Control Mode.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2017-07-02 00:45:38 +01:00
Kenneth Graunke df1279e9df i965: Print access flags in INTEL_DEBUG=buf output.
Being able to see the access mode of various mappings is incredibly
useful for debugging.  With this patch, INTEL_DEBUG=buf now shows
data such as:

   bo_create: buf 7 (bufferobj) 640b
   bo_map_gtt: 7 (bufferobj) -> 0x7fca1fae5000, WRITE ASYNC
   brw_bo_map_cpu: 7 (bufferobj) -> 0x7fca1fae4000, READ
   bo_map_gtt: 5 (bufferobj) -> 0x7fca1fad4000, WRITE ASYNC
   brw_bo_map_cpu: 7 (bufferobj) -> 0x7fca1fae4000, READ

which makes it easy to see that there are async GTT writes with
intervening CPU reads.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-07-01 11:48:08 -07:00