Commit Graph

90675 Commits

Author SHA1 Message Date
Dave Airlie 5ab1289b48 radv/ac: add clip support for tess eval shader.
As this may be the last shader to emit clip distances.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:37 +10:00
Dave Airlie 326b9bc6dc radv/ac: hook up tessellation intrinsics.
This just adds support for the nir intrinsics that tessellation uses.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:32 +10:00
Dave Airlie d8ab71b207 radv/ac: hook up shader information handling for tessellation
This hooks up the tessellation shader info to the nir values
and ctx generated ones.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:27 +10:00
Dave Airlie 4c60c68bd1 radv/pipeline: start calculating tess stage.
This calculates the pipeline state for tessellation.

It moves the gs ring calculation down to below
where the tessellation shaders will be compiled,
as it needs the info from those shaders.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:19 +10:00
Dave Airlie 823b55a8a9 radv: add tessellation support to variant code.
This just fills out the rsrc registers for tess shaders.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:14 +10:00
Dave Airlie f239f59778 radv: add tessellation support to shader naming
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:08 +10:00
Dave Airlie 5b40eab00a radv: add tess ctrl stage barrier workaround for SI.
This just ports the workaround from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:16:04 +10:00
Dave Airlie 3a633cc2cb radv/ac: add support for patch inputs to unique index code.
This add support for tessellation patch inputs to the code
that finds the unique parameter index.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:57 +10:00
Dave Airlie aeb49bc2b9 radv: port polaris vgt vertex reuse workaround.
This ports the VGT_VERTEX_REUSE register settings
for Polaris GPUs from radeonsi.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:51 +10:00
Dave Airlie 46a820b383 radv: configure tessellation distribution register.
This just takes the radeonsi values.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:45 +10:00
Dave Airlie 60326a7afc radv/ac: setup tessellation shader inputs.
This just configures all the register inputs for the tessellation
related stages.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:41 +10:00
Dave Airlie 3968162751 radv/ac: setup tess rings on compiler side.
This just sets up the necessary pointers on the compiler
side for the rings needed for tessellation.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:35 +10:00
Dave Airlie 46e52df34d radv: add tessellation ring allocation support. (v2)
This patch adds support for the offchip rings for storing
tessellation factors and attribute data.

It includes the register setup for the TF ring

v2: always do tess ring size calcs (Bas)

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:30 +10:00
Dave Airlie bbfb62df16 radv: add support for some device specific tess information.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:26 +10:00
Dave Airlie 2b3c4bcc1f radv/ac: add tess changes to shader keys/info
This adds the tess pieces for shader keys and shader info,
it adds the necessary bits to the vertex key/info as well.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:22 +10:00
Dave Airlie a4b039db04 radv: add tess shader stage user data support.
This just adds support for tess to the shader stage conversion
and emits the per-stage descriptors/constants for tess stages.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:15 +10:00
Dave Airlie a5136a97f7 radv: use defines for ring descriptor offsets.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:15:12 +10:00
Dave Airlie 0604284e3f radv: add helper function to denote if tess is enabled on a pipeline.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:14:59 +10:00
Dave Airlie 97e0ff30c0 radv: handle clip dist in es outputs.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:14:53 +10:00
Dave Airlie 6279646306 radv: drop unneeded start
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:14:39 +10:00
Dave Airlie a58d03a5a2 radv: fixup geometry clip emission since using the geom pass
Fixes: 2b35b60d: radv: move to using nir clip/cull merge pass.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-04-01 07:14:38 +10:00
Marek Olšák 744317c9d2 radeonsi/gfx9: allow CMASK fast clear with RB+
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák ea59521475 radeonsi/gfx9: don't compare src_va w/ dst_va for CP_DMA_CLEAR
src_va contains the clear value in this case.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák e3cb67dc6b radeonsi/gfx9: fix 1D array fetches with derivs, bias, or Z compare value
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák 6ab2042761 radeonsi/gfx9: fix and enable single-sample CMASK fast clear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák d4bb4583b0 radeonsi/gfx9: fix and enable MSAA compression
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák 06d725ab2f radeonsi/gfx9: disable CE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák 35aaccaf81 radeonsi/gfx9: fix linear mipmap CPU access
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák 322eb13f09 radeonsi: add tests verifying that VM faults don't hang
GFX9 hangs instead of writing VM faults to dmesg.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák 283c31afa1 radeonsi: unify HS max_offchip_buffers workarounds
Vulkan doesn't set more than 508.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:57 +02:00
Marek Olšák 829bd77235 radeonsi: adjust checking for SC bug workarounds
no change in behavior, just making sure that no later chips will use
the workarounds

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 21:41:56 +02:00
Brian Paul 2936f5c37e glsl: use -O1 optimization for builtin_functions.cpp with MinGW
Some versions of MinGW-w64 such as 5.3.1 and 6.2.0 produce bad code
with -O2 or -O3 causing a random driver crash when running programs
that use GLSL.  Most Mesa demos in the glsl/ directory trigger the
bug, but not the fragcoord.c test.

Use a #pragma to force -O1 for this file for later MinGW versions.
Luckily, this is basically one-time setup code.  I suspect the bug
is related to the sheer size of this file.

This should let us move to newer versions of MinGW-w64 for Mesa.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 13:36:25 -06:00
Brian Paul 15bb0511d6 tnl: remove unused var to silence warning
Trivial.
2017-03-31 13:30:54 -06:00
Neha Bhende 2e24a11f1d st/wgl: Replace variable name hdc with hDrawDC
Reviewed-by: Brian Paul <brianp@vmware.com>
2017-03-31 13:30:54 -06:00
Brian Paul 7d0aac2392 st/wgl: add support for WGL_ARB_make_current_read
This adds the wglMakeContextCurrentARB() and wglGetCurrentReadDCARB()
functions.

Signed-off-by: Brian Paul <brianp@vmware.com>
2017-03-31 13:30:54 -06:00
Brian Paul 7753f040fa stw/wgl: add null context check in wglBindTexImageARB()
To avoid dereferencing a null pointer in case wglMakeCurrent() wasn't
called.  Found while debugging SWKOTOR game.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-03-31 13:30:53 -06:00
Marek Olšák 7d2fa8dc10 radeonsi: decompress DCC in set_sampler_view instead of create_sampler_view (v2)
v2: don't add a new decompress helper function

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 20:57:53 +02:00
Marek Olšák 8c7d1ded19 radeonsi: decompress DCC in set_framebuffer_state instead of create_surface (v2)
for threaded gallium, which can't use pipe_context in create_surface

v2: don't add a new decompress helper function

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-03-31 20:57:53 +02:00
Nicolai Hähnle d10fbe5159 st/glsl_to_tgsi: fix 64-bit integer bit shifts
Fix a bug that was caused by a type mismatch in the shift count between
GLSL and TGSI. I briefly considered adjusting the TGSI semantics, but
since both LLVM and AMD GCN require both arguments to be of the same type,
it makes more sense to keep TGSI as-is -- it reflects the underlying
implementation better.

I'm also sending out piglit tests that expose this error.

v2: use the right number of components for the temporary register

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 18:15:50 +02:00
Nicolai Hähnle c22841d8d2 tgsi: fix printing of 64-bit integer immediates
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 18:15:47 +02:00
Lionel Landwerlin 74a80d579d intel: genxml: fix out of tree builds
v2: use Emil's recommendation
    change rule to closer to genxml/genX_bits.h

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-03-31 15:29:57 +01:00
Thomas Hellstrom 18e2aa063c gbm/dri: Check dri extension version before flush after unmap
The commit mentioned below required the __DRI2FlushExtension to have
version 4 or above, for GBM functionality. That broke GBM with some
classic dri drivers. Relax that requirement so that we only flush
after unmap if we have version 4 or above. Drivers that require the flush
for correct functionality should implement the desired version.

Fixes: ba8df228 ("gbm/dri: Flush after unmap")
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Tested-by: Dylan Baker <dylan@pnwbakers.com>
2017-03-31 10:25:46 +02:00
Nicolai Hähnle 02112c3ef7 radeonsi: implement ARB_shader_group_vote
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 07:56:27 +02:00
Nicolai Hähnle cd3f386069 radeonsi: enable ARB_shader_clock
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 07:56:27 +02:00
Nicolai Hähnle 2290535d62 radeonsi: emit TGSI_OPCODE_CLOCK
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 07:56:26 +02:00
Nicolai Hähnle 65b542a7cc st/mesa: implement ARB_shader_clock
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 07:56:26 +02:00
Ilia Mirkin 94ec847cb0 tgsi: add CLOCK opcode
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 07:56:26 +02:00
Nicolai Hähnle d0c7f924a3 gallium: add PIPE_CAP_TGSI CLOCK
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 07:56:25 +02:00
Nicolai Hähnle 44125b29d1 glsl: fix clockARB builtin function
The underlying intrinsic is defined to always have a uvec2 return type.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-03-31 07:56:25 +02:00
Tapani Pälli 3535b87a1a anv: change BLOCK_POOL_MEMFD_SIZE to 1GB
This allows us to run 32bit Vulkan apps on Android, ftruncate
call would fail on 2GB (max size being 2GB - 1).

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-03-31 08:43:28 +03:00