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radeonsi/gfx9: fix and enable MSAA compression 

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2017-03-28 10:58:02 +02:00
parent 06d725ab2f
commit d4bb4583b0
3 changed files with 4 additions and 6 deletions
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5
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -4609,9 +4609,8 @@ static void tex_fetch_args(
* The sample index should be adjusted as follows:
* sample_index = (fmask >> (sample_index * 4)) & 0xF;
*/
if (ctx->screen->b.chip_class <= VI && /* TODO: fix FMASK on GFX9 */
(target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA)) {
if (target == TGSI_TEXTURE_2D_MSAA ||
target == TGSI_TEXTURE_2D_ARRAY_MSAA) {
struct lp_build_context *uint_bld = &bld_base->uint_bld;
struct lp_build_emit_data txf_emit_data = *emit_data;
LLVMValueRef txf_address[4];

3
src/gallium/drivers/radeonsi/si_state.c
View File

@ -2198,8 +2198,7 @@ static void si_initialize_color_surface(struct si_context *sctx,
S_028C74_NUM_FRAGMENTS(log_samples);
if (rtex->fmask.size) {
/* TODO: fix FMASK on GFX9: */
color_info |= S_028C70_COMPRESSION(sctx->b.chip_class <= VI);
color_info |= S_028C70_COMPRESSION(1);
unsigned fmask_bankh = util_logbase2(rtex->fmask.bank_height);
if (sctx->b.chip_class == SI) {

2
src/gallium/winsys/amdgpu/drm/amdgpu_surface.c
View File

@ -753,7 +753,7 @@ static int gfx9_compute_miptree(struct amdgpu_winsys *ws,
if (ret != ADDR_OK)
return ret;
surf->u.gfx9.fmask.swizzle_mode = in->swizzleMode;
surf->u.gfx9.fmask.swizzle_mode = fin.swizzleMode;
surf->u.gfx9.fmask.epitch = fout.pitch - 1;
surf->u.gfx9.fmask_size = fout.fmaskBytes;
surf->u.gfx9.fmask_alignment = fout.baseAlign;