Commit Graph

109866 Commits

Author SHA1 Message Date
Rob Clark fc865de777 freedreno/ir3: add pass to move varying loads
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-30 12:56:01 -04:00
Rob Clark 831f1a05c0 freedreno/ir3: rework varying packing
Originally we kept track of a table of inputs.  But with new-style frag
inputs this becomes awkward.  Re-work it so that initially we assigned
un-packed varying locations, and then after the shader is compiled scan
to find actual used inputs, and re-pack.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-30 12:56:01 -04:00
Rob Clark 91a1354cd6 freedreno/ir3: re-indent comment
Make it more clear that it applies to the following 'case' statements,
rather than the previous one.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-30 12:56:01 -04:00
Rob Clark 1ae0c030cb nir: add lower_all_io_to_elements
I need this part of lower_all_io_to_temps but without the actual
lowering to temps part.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-30 12:56:01 -04:00
Rob Clark e5e67228f5 nir: print var name for load_interpolated_input too
Signed-off-by: Rob Clark <robdclark@gmail.com>
Acked-by: Karol Herbst <kherbst@redhat.com>
2019-03-30 12:55:47 -04:00
Sergii Romantsov 72a921e12a i965,iris/blorp: do not blit 0-sizes
Seems there is no sense in blitting 0-sized sources
or destinations.
Additionaly it may cause segfaults for i965.

v2: Function call replaced with inline check

v3: Added check to avoid devision by zero (L. Landwerlin)

v4: Added simillar check for Iris (L. Landwerlin)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110239
Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-30 11:50:40 +00:00
Vinson Lee e757a2481f gallium: Fix autotools build with libxatracker.la.
CXXLD    libxatracker.la
/usr/bin/ld: ../../../../src/gallium/auxiliary/.libs/libgallium.a(tgsi_to_nir.o): in function `ttn_finalize_nir':
src/gallium/auxiliary/nir/tgsi_to_nir.c:2111: undefined reference to `gl_nir_lower_samplers_as_deref'
/usr/bin/ld: src/gallium/auxiliary/nir/tgsi_to_nir.c:2113: undefined reference to `gl_nir_lower_samplers'

Fixes: 9a834447d6 ("tgsi_to_nir: Produce optimized NIR for a given pipe_screen.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109929
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
2019-03-29 23:24:05 -07:00
Timur Kristóf 356ec7a219 gallium: fix autotools build of pipe_msm.la
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Fixes: 9a834447d6 ("tgsi_to_nir: Produce optimized NIR for a given pipe_screen.")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109929
2019-03-29 23:12:40 -07:00
Jason Ekstrand 7dbd934e26 nir: Lock around validation fail shader dumping
This prevents getting mixed-up results if a multi-threaded app has two
validation errors in different threads.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-03-29 21:57:51 -05:00
Brian Paul b8e077daee util: no-op __builtin_types_compatible_p() for non-GCC compilers
__builtin_types_compatible_p() is GCC-specific and breaks the
MSVC build.

This intrinsic has been in u_vector_foreach() for a long time, but
that macro has only recently been used in code
(nir/nir_opt_comparison_pre.c) that's built with MSVC.

Fixes: 2cf59861a ("nir: Add partial redundancy elimination for compares")

Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-03-29 15:33:43 -06:00
Caio Marcelo de Oliveira Filho 3b20ca34ae iris: Clean up compiler warnings about unused
Removed a few unused variables and iris_getparam_boolean().
Kept 'name' around since there's a commented debug that make use of it.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-29 12:07:26 -07:00
Eric Engestrom 8d9c2044a4 egl: hide entrypoints that shouldn't be exported when using glvnd
From GLVND author:
> From a functional standpoint, exporting additional symbols doesn't
> really matter, since libglvnd will load the vendor libraries with
> RTLD_LOCAL.

Suggested-by: Kyle Brenneman <kbrenneman@nvidia.com>
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Acked-by: Kyle Brenneman <kbrenneman@nvidia.com>
2019-03-29 16:54:08 +00:00
Karol Herbst fea0caea2b nir/validate: validate that tex deref sources are actually derefs
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-29 16:03:22 +01:00
Karol Herbst 6ffc72472c nir/print: fix printing the image_array intrinsic index
Fixes: 0de003be03 ("nir: Add handle/index-based image intrinsics")

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-29 16:03:22 +01:00
Timothy Arceri 4478c5374b Revert "ac/nir: use new LLVM 8 intrinsics for SSBO atomic operations"
This reverts commit 29132af234.

It seems the new intrinsic causes a hang on radeonsi (VEGA) when running the
piglit test:

tests/spec/arb_shader_storage_buffer_object/execution/ssbo-atomicCompSwap-int.shader_test
2019-03-29 21:04:01 +11:00
Samuel Pitoiset cc752dea61 ac: fix return type for llvm.amdgcn.frexp.exp.i32.64
This fixes the following piglit with RadeonSI
tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4.shader_test

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-03-29 09:18:24 +01:00
Gert Wollny a0edceb00d virgl: Add a caps feature check version
When we add new feature checks on the host side that is used to
enable a cap conditionally that was enabled unconditionally before
we might end up with a feature regression when a new mesa version
is used with an old virglrenderer version that doesn't check for
that cap.

To work around this problem add a version id to the caps that corresponds
to the features that are actually checked on the host and check that
version too when enabling the cap.

Fixes: 2ee197d6e8
    virgl: Enable mixed color FBO attachemnets only when the host supports it

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Pohsien Wang <pwang@chromium.org>
2019-03-29 07:55:31 +00:00
Samuel Pitoiset 62a9d757e6 radv: do not always initialize HTILE in compressed state
Especially when performing a transtion from UNDEFINED->GENERAL,
the driver shouldn't initialize HTILE metadata in compressed
state because it doesn't decompress when the src layout is
GENERAL.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110259
Fixes: 3a2e93147f ("radv: always initialize HTILE when the src layout is UNDEFINED")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-29 08:28:18 +01:00
Kenneth Graunke 3fee3d1319 iris: Print the memzone name when allocating BOs with INTEL_DEBUG=buf
This gives me an idea of what kinds of buffers are being allocated on
the fly which could help inform our cache decisions.
2019-03-28 23:37:32 -07:00
Brian Paul 4ee057eaef nir: use {0} initializer instead of {} to fix MSVC build
Trivial change.

Fixes: c6ee46a75 ("nir: Add nir_alu_srcs_negative_equal")
2019-03-28 20:34:23 -06:00
Ian Romanick 7832fb7889 intel/compiler: Use partial redundancy elimination for compares
Almost all of the hurt shaders are repeated instances of the same shader
in synmark's compilation speed tests.

shader-db results:

All Gen6+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 15256840 -> 15256389 (<.01%)
instructions in affected programs: 54137 -> 53686 (-0.83%)
helped: 288
HURT: 0
helped stats (abs) min: 1 max: 15 x̄: 1.57 x̃: 1
helped stats (rel) min: 0.06% max: 26.67% x̄: 1.99% x̃: 0.74%
95% mean confidence interval for instructions value: -1.76 -1.38
95% mean confidence interval for instructions %-change: -2.47% -1.50%
Instructions are helped.

total cycles in shared programs: 372286583 -> 372283851 (<.01%)
cycles in affected programs: 833829 -> 831097 (-0.33%)
helped: 265
HURT: 16
helped stats (abs) min: 2 max: 74 x̄: 11.81 x̃: 4
helped stats (rel) min: 0.04% max: 9.07% x̄: 0.99% x̃: 0.35%
HURT stats (abs)   min: 2 max: 130 x̄: 24.88 x̃: 8
HURT stats (rel)   min: <.01% max: 12.31% x̄: 1.44% x̃: 0.27%
95% mean confidence interval for cycles value: -12.30 -7.15
95% mean confidence interval for cycles %-change: -1.06% -0.64%
Cycles are helped.

Iron Lake and GM45 had similar results. (GM45 shown)
total instructions in shared programs: 5038653 -> 5038495 (<.01%)
instructions in affected programs: 13939 -> 13781 (-1.13%)
helped: 50
HURT: 1
helped stats (abs) min: 1 max: 15 x̄: 3.18 x̃: 4
helped stats (rel) min: 0.33% max: 13.33% x̄: 2.24% x̃: 1.09%
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 0.83% max: 0.83% x̄: 0.83% x̃: 0.83%
95% mean confidence interval for instructions value: -3.73 -2.47
95% mean confidence interval for instructions %-change: -3.16% -1.21%
Instructions are helped.

total cycles in shared programs: 128118922 -> 128118228 (<.01%)
cycles in affected programs: 134906 -> 134212 (-0.51%)
helped: 50
HURT: 0
helped stats (abs) min: 2 max: 60 x̄: 13.88 x̃: 18
helped stats (rel) min: 0.06% max: 3.19% x̄: 0.74% x̃: 0.70%
95% mean confidence interval for cycles value: -16.54 -11.22
95% mean confidence interval for cycles %-change: -0.95% -0.53%
Cycles are helped.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-28 15:35:53 -07:00
Ian Romanick 2cf59861a8 nir: Add partial redundancy elimination for compares
This pass attempts to dectect code sequences like

    if (x < y) {
        z = y - x;
	...
    }

and replace them with sequences like

    t = x - y;
    if (t < 0) {
        z = -t;
	...
    }

On architectures where the subtract can generate the flags used by the
if-statement, this saves an instruction.  It's also possible that moving
an instruction out of the if-statement will allow
nir_opt_peephole_select to convert the whole thing to a bcsel.

Currently only floating point compares and adds are supported.  Adding
support for integer will be a challenge due to integer overflow.  There
are a couple possible solutions, but they may not apply to all
architectures.

v2: Fix a typo in the commit message and a couple typos in comments.
Fix possible NULL pointer deref from result of push_block().  Add
missing (-A + B) case.  Suggested by Caio.

v3: Fix is_not_const_zero to work correctly with types other than
nir_type_float32.  Suggested by Ken.

v4: Add some comments explaining how this works.  Suggested by Ken.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-28 15:35:53 -07:00
Ian Romanick c6ee46a753 nir: Add nir_alu_srcs_negative_equal
v2: Move bug fix in get_neg_instr from the next patch to this patch
(where it was intended to be in the first place).  Noticed by Caio.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-28 15:35:52 -07:00
Ian Romanick be1cc3552b nir: Add nir_const_value_negative_equal
v2: Rebase on 1-bit Boolean changes.

Reviewed-by: Thomas Helland <thomashelland90@gmail.com> [v1]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-28 15:35:52 -07:00
Ian Romanick ae21b52e1d nir/algebraic: Add missing 16-bit extract_[iu]8 patterns
No shader-db changes on any Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
2019-03-28 15:35:52 -07:00
Ian Romanick cbad201c2b nir/algebraic: Add missing 64-bit extract_[iu]8 patterns
No shader-db changes on any Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
2019-03-28 15:35:52 -07:00
Ian Romanick bc17f5a2a3 nir/algebraic: Remove redundant extract_[iu]8 patterns
No shader-db changes on any Intel platform.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-28 15:35:52 -07:00
Ian Romanick c152672e68 nir/algebraic: Fix up extract_[iu]8 after loop unrolling
Skylake, Broadwell, and Haswell had similar results. (Skylake shown)
total instructions in shared programs: 15256840 -> 15256837 (<.01%)
instructions in affected programs: 4713 -> 4710 (-0.06%)
helped: 3
HURT: 0
helped stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
helped stats (rel) min: 0.06% max: 0.08% x̄: 0.06% x̃: 0.06%

total cycles in shared programs: 372286583 -> 372286583 (0.00%)
cycles in affected programs: 198516 -> 198516 (0.00%)
helped: 1
HURT: 1
helped stats (abs) min: 10 max: 10 x̄: 10.00 x̃: 10
helped stats (rel) min: <.01% max: <.01% x̄: <.01% x̃: <.01%
HURT stats (abs)   min: 10 max: 10 x̄: 10.00 x̃: 10
HURT stats (rel)   min: 0.01% max: 0.01% x̄: 0.01% x̃: 0.01%

No changes on any other Intel platform.

v2: Use a loop to generate patterns.  Suggested by Jason.

v3: Fix a copy-and-paste bug in the extract_[ui] of ishl loop that would
replace an extract_i8 with and extract_u8.  This broke ~180 tests.  This
bug was introduced in v2.

Reviewed-by: Matt Turner <mattst88@gmail.com> [v1]
Reviewed-by: Dylan Baker <dylan@pnwbakers.com> [v2]
Acked-by: Jason Ekstrand <jason@jlekstrand.net> [v2]
2019-03-28 15:35:52 -07:00
Dave Airlie b779baa9bf nir/deref: fix struct wrapper casts. (v3)
llvm/spir-v spits out some struct a { struct b {} }, but it
doesn't deref, it casts (struct a) to (struct b), reconstruct
struct derefs instead of casts for these.

v2: use ssa_def_rewrite uses, rework the type restrictions (Jason)
v3: squish more stuff into one function, drop unused temp (Jason)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-29 08:10:50 +10:00
Rafael Antognolli 8e0469f629 i965/blorp: Remove unused parameter from blorp_surf_for_miptree.
It seems pretty useless nowadays.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-03-28 14:38:23 -07:00
Anuj Phogat 9c421d6b47 iris/icl: Add WA_2204188704 to disable pixel shader panic dispatch
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-28 19:59:59 +00:00
Anuj Phogat e0f4359ec1 iris/icl: Set Enabled Texel Offset Precision Fix bit
h/w specification requires this bit to be always set.
See Mesa commit 5eb173304b.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-03-28 19:59:59 +00:00
Rob Clark 78825ca2d0 freedreno/ir3: align const size to vec4
This is no longer true since PIPE_CAP_PACKED_UNIFORMS was enabled.

Fixes: 3c8779af32 freedreno/ir3: Enable PIPE_CAP_PACKED_UNIFORMS
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-28 14:36:24 -04:00
Rob Clark 26e2906382 freedreno/ir3: reads/writes to unrelated arrays are not dependent
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-28 14:36:24 -04:00
Rob Clark d71ce69d9c freedreno/ir3: sched fix
Not sure why new-style frag inputs start triggering this.  But we
probably shouldn't consider src's from other blocks.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-28 14:36:24 -04:00
Rob Clark c557fcaf2b freedreno/a6xx: small cleanup
Signed-off-by: Rob Clark <robdclark@gmail.com>
2019-03-28 14:36:23 -04:00
Kenneth Graunke ee8370c766 iris: Fix blits with S8_UINT destination
For depth and stencil blits, we always want the main mask to be Z, and
the secondary pass mask to be S.  If asked to blit Z+S to S, we should
handle the blit in the second pass which properly gets the stencil
resources.

Before, we were trying to handle S as the main mask, and accidentally
blitting a Z source to a S destination, which doesn't work out well.

Fixes Piglit's "framebuffer-blit-levels {draw,read} stencil" tests.
2019-03-28 10:47:26 -07:00
Kenneth Graunke ce89c19b88 st/mesa: Fix blitting from GL_DEPTH_STENCIL to GL_STENCIL_INDEX
Fixes assertion failures in Piglit's "framebuffer-blit-levels
{draw,read} stencil" tests on iris.  Also fixes assert failures in
frameretrace, which tries to ReadPixels the stencil values (only)
from a Z24S8 depth/stencil attachment.

Reviewed-by: Kristian H. Kristensen <hoegsberg@chromium.org>
2019-03-28 10:47:23 -07:00
Kristian H. Kristensen 107a8ec3b3 freedreno/ir3: Add workaround for VS samgq
This instruction needs a workaround when used from vertex shaders.

Fixes:

  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler2dshadow_vertex
  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_fixed_vertex
  dEQP-GLES3.functional.shaders.texture_functions.texturegradoffset.sampler3d_float_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler2dshadow_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_fixed_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgradoffset.sampler3d_float_vertex
  dEQP-GLES3.functional.shaders.texture_functions.textureprojgrad.sampler2dshadow_vertex

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-28 10:26:32 -07:00
Kristian H. Kristensen f30d4a1cca freedreno/ir3: Don't access beyond available regs
emit_cat5() needs to check if the last optional reg is there before it
accesses it.

Signed-off-by: Kristian H. Kristensen <hoegsberg@chromium.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-03-28 10:26:32 -07:00
Eric Engestrom 7fefa4610d util/disk_cache: close fd in the fallback path
There are multiple `goto path_fail` with an open fd, but none that go to
`fail:` without going through `path_fail:` first, so let's just move the
`close(fd)` there.

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 16:41:27 +00:00
Samuel Pitoiset 6596eb2b30 radv: skip updating depth/color metadata for conditional rendering
I don't think we should update metadata when conditional rendering
is enabled. For some reasons, some CTS breaks only on SI.

This fixes the following CTS on SI:
dEQP-VK.conditional_rendering.draw_clear.clear.depth.*

Cc: 19.0 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 17:37:12 +01:00
Kenneth Graunke 1d72de3bcc st/nir: Free the GLSL IR after linking.
i965 does this, and st's tgsi path does this.  st/nir did not.

Cuts 138MB of memory from a DiRT Rally trace, which is about 44%
of the total GLSL IR memory.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-03-28 09:31:12 -07:00
Samuel Pitoiset 227b191206 radv: enable VK_AMD_gpu_shader_int16
This extension allows 16-bit support to Frexp/FrexpStruct.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 13:02:53 +01:00
Samuel Pitoiset 8a6e61cc52 radv: do not lower frexp_exp and frexp_sig
Hardware has two instructions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 13:02:51 +01:00
Samuel Pitoiset 52c02d921f ac: add ac_build_frex_exp() helper ans 16-bit/32-bit support
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 13:02:48 +01:00
Samuel Pitoiset 1bf9311c59 ac: add ac_build_frexp_mant() helper and 16-bit/32-bit support
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-03-28 13:02:46 +01:00
Kenneth Graunke de783a6897 iris: Actually advertise some modifiers
I neglected to fill out this driver function, causing us to advertise
0 modifiers.  Now we advertise the various tilings and let the driver
pick them.  I've verified that X tiling works with Weston (by hacking
the list to skip Y tiling).

Y+CCS doesn't work yet because it's multiplane and the Gallium dri
state tracker isn't really prepared for that.  Leave it off for now.
2019-03-27 21:27:54 -07:00
Toni Lönnberg 505854f84b intel/genxml: Media instructions and structures for gen11
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    - fix missing type
    - fix *_FQM_*/*_QM_* commands
    - shorten some media structs using groups
    - factor out memory attributes
    - switch MI_FLUSH_DW fields to bool

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00
Toni Lönnberg 4dccf2edef intel/genxml: Media instructions and structures for gen10
v2: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
    - fix missing type
    - fix *_FQM_*/*_QM_* commands
    - shorten some media structs using groups
    - factor out memory attributes
    - switch MI_FLUSH_DW fields to bool

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-03-28 04:26:30 +00:00