Commit Graph

109866 Commits

Author SHA1 Message Date
Guido Günther a5e24dc416 gallium: ddebug: Add missing fence related wrappers
Without that `GALLIUM_DDEBUG=always kmscube -A` would segfault like

  #0  0x0000000000000000 in  ()
  #1  0x0000ffffa72a3c54 in dri2_get_fence_fd (_screen=0xaaaaed4f2090, _fence=0xaaaaed9ef880) at ../src/gallium/state_trackers/dri/dri_helpers.c:140
  #2  0x0000ffffa8744824 in dri2_dup_native_fence_fd (drv=0xaaaaed5010c0, disp=0xaaaaed5029a0, sync=0xaaaaed9ef7c0) at ../src/egl/drivers/dri2/egl_dri2.c:3050
  #3  0x0000ffffa87339b8 in eglDupNativeFenceFDANDROID (dpy=0xaaaaed5029a0, sync=0xaaaaed9ef7c0) at ../src/egl/main/eglapi.c:2107
  #4  0x0000aaaabd29ca90 in  ()
  #5  0x0000aaaabd401000 in  ()

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2019-04-04 17:30:15 +02:00
Danylo Piliaiev 3fdfface3e st/mesa: Fix GL_MAP_COLOR with glDrawPixels GL_COLOR_INDEX
Documentation for glDrawPixels with GL_COLOR_INDEX says:
 "If the GL is in color index mode, and if GL_MAP_COLOR is true,
  the index is replaced with the value that it references in
  lookup table GL_PIXEL_MAP_I_TO_I"

We are always in RGBA mode and there is nothing in documentation
about GL_MAP_COLOR in RGBA mode for GL_COLOR_INDEX.

Scale and bias are also only applicable for RGBA format and not
mentioned for GL_COLOR_INDEX.

Thus the behaviour will be on par with i965.

Fixes: gl-1.0-drawpixels-color-index
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-04-04 10:38:32 -04:00
Eric Engestrom f6ceed205c gallium/hud: fix rounding error in nic bps computation
While at it, fix typo in "rounding error" :P

Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-04 13:59:24 +00:00
Eric Engestrom 9d6ea55263 gallium/hud: prevent buffer overflow
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-04 13:59:24 +00:00
Eric Engestrom 4633d13854 gallium/hud: fix memory leaks
Signed-off-by: Eric Engestrom <eric.engestrom@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-04 13:59:24 +00:00
Marek Olšák b563460b49 radeonsi: enable displayable DCC on Ravens 2019-04-04 09:53:24 -04:00
Marek Olšák 1f21396431 radeonsi: add support for displayable DCC for multi-RB chips
A compute shader is used to reorder DCC data from aligned to unaligned.
2019-04-04 09:53:24 -04:00
Marek Olšák 2c09eb4122 radeonsi: add support for displayable DCC for 1 RB chips
This is the simpler codepath - just disable RB and pipe alignment for DCC.
2019-04-04 09:53:24 -04:00
Marek Olšák 029bfa3d25 radeonsi: add ability to bind images as image buffers
so that we can bind DCC (texture) as an image buffer.
2019-04-04 09:53:24 -04:00
Marek Olšák fe3bfd7971 radeonsi/gfx9: add support for PIPE_ALIGNED=0
Needed by displayable DCC.

We need to flush L2 after rendering if PIPE_ALIGNED=0 and DCC is enabled.
2019-04-04 09:53:24 -04:00
Marek Olšák e457454cb6 amd/addrlib: fix uninitialized values for Addr2ComputeDccAddrFromCoord
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-04 09:30:40 -04:00
Tapani Pälli 41f76dd513 iris: move variable to the scope where it is being used
iris_upload_border_color is passed a pointer which points to
variable that is introduced in a different scope.

CID: 1444296
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-04 04:43:20 +00:00
Tapani Pälli 3cea9f981a st/nir: run st_nir_opts after 64bit ops lowering
CID: 1444309
Fixes: 9ab1b1d022 "st/nir: Move 64-bit lowering later"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2019-04-04 07:38:10 +03:00
Alyssa Rosenzweig b34d8222c7 panfrost: Size tiled temp buffers correctly
This should lower transient memory usage and improve performance
slightly (due to less memory to malloc/free, better cache locality,
etc).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-04 03:51:43 +00:00
Alyssa Rosenzweig c0183e8eed panfrost: Respect box->width in tiled stores
This fixes a regression uploading partial tiled textures introduced
sometime during the cubemap series.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-04 03:51:43 +00:00
Alyssa Rosenzweig 3b38a7e505 panfrost: Cleanup some indirection in pan_resource
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-04 03:51:43 +00:00
Alyssa Rosenzweig 7e8de5a707 panfrost: Implement system values
This patch implements system values via specially-crafted uniforms.
While we previously had an ad hoc system for passing the viewport into
the vertex shader, this commit generalizes the system to allow for
arbitrary system values to be added to both shader stages. While we're
at it, we clean up uniform handling code (which was considerably muddied
to handle the ad hoc viewport uniform).

This commit serves as both a cleanup of the existing codebase and the
precursor to new functionality, like implementing textureSize().

Concurrent with these changes is respecting the depth transform, which
was not possible with the old fixed uniform system and here serves as a
proof-of-correctness test (as well as justifying the NIR changes).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2019-04-04 03:44:15 +00:00
Alyssa Rosenzweig a83862754e nir: Add "viewport vector" system values
While a partial set of viewport system values exist, these are scalar
values, which is a poor fit for viewport transformations on vector ISAs
like Midgard (where the vec3 values for scale and offset each need to be
coherent in a vec4 uniform slot to take advantage of vectorized
transform math). This patch adds vec3 scale/offset fields corresponding
to the 3D Gallium viewport / glViewport+depth

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-04-04 03:44:09 +00:00
Erik Faye-Lund b85ca86c1e virgl: also destroy all read-transfers
For texture write-transfers, we either free them on the transfer-queue
or right away. But for read-transfers, we currently only destroy them in
case they used a temp-resource. This leads to occasional resource-leaks.

Let's add a call to virgl_resource_destroy_transfer in the missing case.

Do the same thing for buffers as well, but the logic is a bit easier to
follow there.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Fixes: f0e71b1088 ("virgl: use transfer queue")
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-03 18:59:23 +02:00
Dylan Baker 4c332a1f9f meson: Error if LLVM is turned off but clover it turned on
Since clover has a hard requirement on LLVM

v2: - make error message more specific

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-04-03 09:41:24 -07:00
Dylan Baker 29912f2ea4 meson: Error if LLVM doesn't have rtti when building clover
We already do this for nouveau, but it's required for clover too.
2019-04-03 09:41:24 -07:00
Alyssa Rosenzweig 138865e676 panfrost: Remove support for legacy kernels
Previously, there was minimal support for interoperating with legacy
kernels (reusing kernel modules originally designed for proprietary
legacy userspaces, rather than for upstream-friendly free software
stacks). Now that the Panfrost kernel is stabilising, this commit drops
the legacy code path.

Panfrost users need to use a modern, mainline kernel supporting the
Panfrost kernel driver from this commit forward.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
2019-04-03 15:21:30 +00:00
Lucas Stach 43db0632e7 etnaviv: only try to construct scanout resource when on KMS winsys
Trying to construct a scanout capable buffer will only ever work when
when we are on top of a KMS winsys, as the render node isn't capable
of allocating contiguous buffers.

Tested-by: Marius Vlad <marius.vlad@collabora.com>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-04-03 12:54:09 +02:00
Lucas Stach 3d8da347ac etnaviv: flush all pending contexts when accessing a resource with the CPU
When setting up a transfer to a resource, all contexts where the resource
is pending must be flushed. Otherwise a write transfer might be started
in the current context before all contexts that access the resource in
shared (read) mode have been executed.

Fixes: 64813541d5 (etnaviv: fix resource usage tracking across
different pipe_context's)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-By: Guido Günther <agx@sigxcpu.org>
2019-04-03 12:54:09 +02:00
Lucas Stach f317ee1aff etnaviv: don't flush own context when updating resource use
The context is self synchronizing at the GPU side, as commands are
executed in order. We must not flush our own context when updating the
resource use, as that leads to excessive flushing on effectively every
draw call, causing huge CPU overhead.

Fixes: 64813541d5 (etnaviv: fix resource usage tracking across
different pipe_context's)
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2019-04-03 12:54:09 +02:00
Christian Gmeiner c7cddc2787 etnaviv: shrink struct etna_3d_state
Drop struct members which are only written to but never read from.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
2019-04-03 12:54:09 +02:00
Dave Airlie 11e1fa11d6 intel/compiler: use defined size for vector components
If we increase vector sizing later it would be nice to avoid
tripped over this again.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-04-03 13:59:06 +10:00
Dave Airlie eb8fefe090 nir: use proper array sizing define for vectors
If we increase the vector size in the future it would be good
to not have to fix these up, this should change nothing at present.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-04-03 13:59:06 +10:00
Timothy Arceri d8ce915a61 Revert "nir: propagate known constant values into the if-then branch"
This reverts commit 4218b6422c.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110311
2019-04-03 13:24:18 +11:00
Timothy Arceri 4218b6422c nir: propagate known constant values into the if-then branch
Helps Max Waves / VGPR use in a bunch of Unigine Heaven
shaders.

shader-db results radeonsi (VEGA):
Totals from affected shaders:
SGPRS: 5505440 -> 5505872 (0.01 %)
VGPRS: 3077520 -> 3077296 (-0.01 %)
Spilled SGPRs: 39032 -> 39030 (-0.01 %)
Spilled VGPRs: 16326 -> 16326 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 744 -> 744 (0.00 %) dwords per thread
Code Size: 123755028 -> 123753316 (-0.00 %) bytes
Compile Time: 2751028 -> 2560786 (-6.92 %) milliseconds
LDS: 1415 -> 1415 (0.00 %) blocks
Max Waves: 972192 -> 972240 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

vkpipeline-db results RADV (VEGA):

Totals from affected shaders:
SGPRS: 160 -> 160 (0.00 %)
VGPRS: 88 -> 88 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 18268 -> 18152 (-0.63 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 26 -> 26 (0.00 %)
Wait states: 0 -> 0 (0.00 %)

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
2019-04-03 10:04:48 +11:00
Lepton Wu 250fffac15 virgl: close drm fd when destroying virgl screen.
This fd was create in virgl_drm_screen_create and should be closed
in virgl_drm_screen_destroy.

Signed-off-by: Lepton Wu <lepton@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
2019-04-02 15:29:47 -07:00
Rafael Antognolli 08c44b47a9 iris: Enable fast clears on gen8.
Since we are now properly storing the clear color with SCS bits, we can
now enable fast clears on gen8 too.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-02 15:26:48 -07:00
Rafael Antognolli 7339660e80 iris: Add aux.sampler_usages.
We want to skip some types of aux usages (for instance,
ISL_AUX_USAGE_HIZ when the hardware doesn't support it, or when we have
multisampling) when sampling from the surface.

Instead of checking for those cases while filling the surface state and
leaving it blank, let's have a version of aux.possible_usages for
sampling. This way we can also avoid allocating surface state for the
cases we don't use.

Fixes: a8b5ea8ef0 "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-02 15:26:45 -07:00
Rafael Antognolli dfc5620a41 iris: Do not allocate clear_color_bo for gen8.
Since we are not using it for the clear color, there's no need to
allocate it.

Fixes: a8b5ea8ef0 "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-02 15:26:41 -07:00
Rafael Antognolli c26d8a887d iris: Manually apply fast clear color channel overrides.
At the fast clear time, the only swizzle we have available is actually
the identity swizzle (which we use for most rendering). So the call to
swizzle_color_value() becomes simply a no-op, and doesn't properly zero
out the unused channels.

We have to manually override those channels.

Fixes: a8b5ea8ef0 "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-02 15:26:38 -07:00
Rafael Antognolli 2660667284 iris/gen8: Re-emit the SURFACE_STATE if the clear color changed.
The swizzle for rendering surfaces is always identity. So when we are
doing the fast clear, we don't have enough information to store the
clear color OR'ed with the Shader Channel Select bits for the dword in
the SURFACE_STATE.

Instead of trying to patch up the SURFACE_STATE correctly later, by
reading the color from the clear color state buffer and then doing all
the operations to store it, let's just re-emit the whole SURFACE_STATE.
That should make things way simpler on gen8, and we can still use the
clear color state buffer for gen9+.

Fixes: a8b5ea8ef0 "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-02 15:26:33 -07:00
Rafael Antognolli 6a02873687 iris: Only update clear color for gens 8 and 9.
Newer gens can read it directly.

Also properly skip updating the ISL_AUX_USAGE_NONE surface.

Fixes: a8b5ea8ef0 "iris: Add function to update clear color in surface state."
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-02 15:24:15 -07:00
Alexander von Gluck IV 5f467fe08e haiku: Fix hgl dispatch build. Tested under meson/scons.
Reviewed-by: Brian Paul <brianp@vmware.com>
2019-04-02 16:06:00 -05:00
Guido Günther 10b90570d1 docs: Fix 19.0.x version numbers
The list has 19.0.2 twice.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
2019-04-02 09:12:47 -07:00
Marek Olšák 40b9eec8bd docs/relnotes: document parallel_shader_compile changes in 19.1.0, not 19.0.0 2019-04-02 10:47:37 -04:00
Benjamin Tissoires 7f8a9a1fbb CI: use wayland ci-templates repo to create the base image
There shouldn't be a difference for users, but this way we do manage
all of our containers from freedesktop.org

note: compared to the provious Dockerfile, we need to manually
      add gcc, g++ and python*-wheel

Signed-off-by: Benjamin Tissoires <benjamin.tissoires@gmail.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2019-04-02 13:41:05 +00:00
Marek Olšák 7be26976b8 radeonsi: don't use PFP_SYNC_ME with compute-only contexts
Compute rings don't have PFP.

Fixes: a1378639ab "radeonsi: always use compute rings for clover on CI and newer (v2)"

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Jan Vesely <jan.vesely@rutgers.edu>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-04-02 08:46:49 -04:00
Gert Wollny 1e5381f934 virgl: define MAX_VERTEX_STREAMS based on availability of TF3
Since with gles hosts we lie about the GLSL feature level it is better
to set the number of streams based on actual hosts capabilities.

v2: Make use of feature check level to avoid regressions.

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By:  Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-02 11:28:09 +00:00
Gert Wollny 33d9b9436c softpipe: Implement ATOMFADD and enable cap TGSI_ATOMFADD
This enables the following piglits with PASS:
  nv_shader_atomic_float/execution/
    shared-atomicadd-float
    shared-atomicexchange-float
    ssbo-atomicadd-float
    ssbo-atomicexchange-float

v2: Minimize the patch by using type punning (Eric Anholt)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-04-02 09:58:16 +00:00
Erik Faye-Lund 4f153fcd5c virgl: stricter usage of compressed 3d textures
Using RGTC, ETC1, ETC2 or S3TC for 3D-textures isn't alowed by any of
OpenGL 4.6, OpenGL ES 3.2, ARB_texture_compression_rgtc,
EXT_texture_compression_rgtc, OES_compressed_ETC1_RGB8_texture,
S3_s3tc or EXT_texture_compression_s3tc specifications.

So let's not allow any of those compressed 3d-textures at all. It's not
going to work once it hits the OpenGL driver in virglrenderer.

Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-02 07:48:46 +00:00
Erik Faye-Lund f53001324f virgl: do not allow compressed formats for buffers
Signed-off-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
2019-04-02 07:48:45 +00:00
Eric Anholt edc7deec42 dri3: Return the current swap interval from glXGetSwapIntervalMESA().
We were caching only the value set with glXSwapIntervalSGI(), missing out
on the default setting of the swap interval by the loader.  This fixes
glxgears's warning about being vblank synchronized by default.

Fixes: 9777c4234b ("loader: drop the [gs]et_swap_interval callbacks")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2019-04-01 16:06:38 -07:00
Anuj Phogat 82f6a746e8 intel: Add support for Comet Lake
Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2019-04-01 14:07:40 -07:00
Chris Wilson 80e1ca9d28 iris: Adapt to variable ppGTT size
Not all hardware is made equal and some does not have the full
complement of 48b of address space. Ask what the actual size of virtual
address space allocated for contexts, and bail if that is not enough to
satisfy our static partitioning needs.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-04-01 10:01:02 -07:00
Samuel Pitoiset c25f63872b radv: partially enable VK_KHR_shader_float16_int8
Only 8-bit integers for now, float16 requires a bit more work.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-04-01 18:53:59 +02:00