Commit Graph

87756 Commits

Author SHA1 Message Date
Chad Versace 464b23b1f2 mesa/shaderobj: Fix races on refcounts
Use atomic ops when updating gl_shader::RefCount.

Fixes intermittent failures and crashes in
'dEQP-EGL.functional.sharing.gles2.multithread.*'.
All tests in that group now pass except
'dEQP-EGL.functional.sharing.gles2.multithread.simple_egl_server_sync.textures.copyteximage2d_texsubimage2d_render'.

Tested with:
  mesa: branch 'master' at d6545f2
  deqp: branch 'nougat-cts-dev' at 4acf725 with additional local fixes
  DEQP_TARGET: x11_egl
  hw: Intel Broadwell 0x1616

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99085
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Cc: Mark Janes <mark.a.janes@intel.com>
Cc: Haixia Shi <hshi@chromium.org>
2016-12-28 11:10:43 -08:00
Rob Clark ec01ef2db1 freedreno/ir3: fix linkage::var size
It should actually be 32 for a4xx/a5xx.. we still only advertise 16 but
for a5xx the linkage map includes position/psize.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27 16:54:01 -05:00
Rob Clark c416ea31cf freedreno/ir3: treat clipvertex like a normal varying
We need this in case it is streamed out.  Not sure why we were treating
it specially before.  Having it as a VS out is harmless if FS doesn't
have a matching input.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27 16:54:01 -05:00
Rob Clark d10c5a2481 freedreno/a5xx: transform-feedback support
We'll need to revisit when adding hw binning pass support, whether we
can still do this in main draw step, as we do w/ a3xx/a4xx, or if we
needed to move it to the binning stage.

Still some failing piglits but most tests pass and the common cases seem
to work.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27 16:54:01 -05:00
Rob Clark 928e9bd602 freedreno: update generated headers
Pull in a5xx streamout related regs.  Also fixes a couple incorrect
register definitions.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27 16:54:01 -05:00
Rob Clark 6d77ceb701 freedreno/ir3: UBO support for 64b GPUs (a5xx)
Update address calculation to support 64b addresses.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27 16:54:01 -05:00
Rob Clark fc10dc9fde freedreno/ir3: rework location of driver constants
Rework how we lay out driver constants (driver-params, UBO/TFBO buffer
addresses, immediates) for more flexibility.  For a5xx+ we need to deal
with the fact that gpu ptrs are 64b instead of 32b, which makes the
fixed offset scheme not work so well.  While we are dealing with that
we might also make the layout more dynamic to account for varying # of
UBOs, etc.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27 16:54:01 -05:00
Rob Clark 09202cde7e freedreno/a5xx: fix emit for bo addresses
Reloc for the buffer address is two dwords on 64b devices (a5xx+)

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27 16:54:01 -05:00
Rob Clark f043904080 freedreno/a5xx: texture layout
Seems to be imilar to a4xx, and sampler state "array-pitch" needs
to be aligned to page size.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2016-12-27 16:54:01 -05:00
Rob Clark 859cb24d94 ttn: set ->info->num_ubos
For dealing w/ 32b vs 64b gpu addresses, I need to rework how we pass
UBO buffer addresses to shader, and knowing up front the # of UBOs is
useful.  But I noticed ttn wasn't setting this.

Signed-off-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
2016-12-27 16:54:01 -05:00
Chad Versace d6545f2345 anv: Handle vkGetPhysicalDeviceQueueFamilyProperties with count == 0
The spec implicitly allows the incoming count to be 0. From the Vulkan
1.0.38 spec, Section 4.1 Physical Devices:

    If the value referenced by pQueueFamilyPropertyCount is not 0 [then
    do stuff].

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-27 12:31:34 -08:00
Chad Versace b85c0b569f egl: Emit correct error when robust context creation fails
Fixes dEQP-EGL.functional.create_context_ext.robust_*
on Intel with GBM.

If the user sets the EGL_CONTEXT_OPENGL_ROBUST_ACCESS_BIT_KHR in
EGL_CONTEXT_FLAGS_KHR when creating an OpenGL ES context, then
EGL_KHR_create_context spec requires that we unconditionally emit
EGL_BAD_ATTRIBUTE because that flag does not exist for OpenGL ES. When
creating an OpenGL context, the spec requires that we emit EGL_BAD_MATCH
if we can't support the request; that error is generated in the egl_dri2
layer where the driver capability is actually checked.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99188
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2016-12-27 10:21:29 -08:00
Damien Grassart 75252826e8 anv: return count of queue families written
The Vulkan spec indicates that
vkGetPhysicalDeviceQueueFamilyProperties() should overwrite
pQueueFamilyPropertyCount with the number of structures actually
written to pQueueFamilyProperties.

Signed-off-by: Damien Grassart <damien@grassart.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Cc: mesa-stable@lists.freedesktop.org
2016-12-27 10:15:47 -08:00
Chad Versace e2d69d5e2d i965: Allow import/export of ARGB1555 images
To my knowledge, this fixes no tests. I simply wrote the patch for
completeness as a follow-up to the previous two patches.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2016-12-27 09:14:04 -08:00
Chad Versace f3739810e3 mesa/texformat: Handle GL_RGBA + GL_UNSIGNED_SHORT_5_5_5_1
_mesa_choose_tex_format() already handles GL_RGBA + GL_UNSIGNED_SHORT_1_5_5_5_REV
by converting it to MESA_FORMAT_B5G5R5A1_UNORM. Teach it do the same for
the non-reversed type. Otherwise, the switch's fallthrough converts it
to an 8888 format, which has incompatible precision in the alpha
channel.

Patch 2/2 to fix dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8
on Intel.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99185
Cc: Haixia Shi <hshi@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-12-27 09:14:00 -08:00
Chad Versace 9aa6ab0748 dri: Add __DRI_IMAGE_FORMAT_ARGB1555
This allows eglCreateImage() to accept textures of said format.

Patch 1/2 to fix
dEQP-EGL.functional.image.modify.tex_rgb5_a1_tex_subimage_rgba8
on Intel.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99185
Cc: Haixia Shi <hshi@chromium.org>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-12-27 09:13:43 -08:00
Tapani Pälli 4d6d4f939e egl/dri2: implement query surface hook
This makes better guarantee that the values we return are
in sync what the underlying drawable currently has.

Together with dEQP change in bug #98327 this fixes following test:

   dEQP-EGL.functional.resize.surface_size.grow

v2: avoid unnecessary x11 roundtrips (Chad Versace)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98327
2016-12-27 08:01:08 +02:00
Dave Airlie d8423772ca radv: add some asserts for operations on general queue
These might be useful in the future, or not.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-27 03:27:14 +00:00
Bas Nieuwenhuizen 059af2515a radv: Also skip DCC clear flushes for compute.
(airlied: fixes DOOM hang with compute queue enabled)
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
2016-12-27 03:27:13 +00:00
Dave Airlie 3fd306b423 radv: handle queue present directly to winsys
Don't call the QueueSubmit interface, just call direct to the
winsys, so we can pass the wait semaphores.

Noticed while debugging doom, doesn't fix anything.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-26 22:20:35 +00:00
Jordan Justen 097c9dc2d4 intel/blorp_blit: Fix max blit size for gen6
Fixes ES3-CTS.gtf.GL3Tests.framebuffer_blit.framebuffer_blit_functionality_stencil_blit

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-12-26 08:50:21 -08:00
Dave Airlie b5bb8b54cf radv: fix rendering to b10g11r11_ufloat_pack32
doom was causing a printf about an illegal color, it was due the
non-void returning -1, and the other function checking for 4,
align these.

Reviewed-by: Edward O'Callaghan <funfunctor@folklore1984.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-26 10:31:20 +10:00
Dave Airlie 4813c9ade7 radv: handle multi-component shared load/stores.
This was seen in doom shaders, so handle it properly.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave AIrlie <airlied@redhat.com>
2016-12-26 10:31:20 +10:00
Vedran Miletić d9fef848a6 clover: Use Clang's diagnostics
Presently errors from frontend are handled only if they occur in
clang::CompilerInvocation::CreateFromArgs(). This patch uses
clang::DiagnosticsEngine to detect errors such as invalid values for
Clang frontend arguments.

Fixes Piglit's cl/program/build/fail/invalid-version-declaration.cl
test.

v2: fix inconsistent code formatting

Signed-off-by: Vedran Miletić <vedran@miletic.net>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Tested-by: Aaron Watry <awatry@gmail.com>
2016-12-24 18:35:09 -08:00
Damien Grassart 3a30b1a556 radv: return count of queue families written
The Vulkan spec indicates that
vkGetPhysicalDeviceQueueFamilyProperties() should overwrite
pQueueFamilyPropertyCount with the number of structures actually
written to pQueueFamilyProperties.

Signed-off-by: Damien Grassart <damien@grassart.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2016-12-25 02:25:02 +01:00
Jason Ekstrand 88b5acfa09 i965/generator/tex: Handle an immediate sampler with an indirect texture
In this case we were dying when we tried to do SHL addr sampler imm(8)
because that puts an immediate in src0 of a two source instruction. This
fixes 2704 of the new separate sampler Vulkan CTS tests on Sky Lake.

Reviewed-by: Eduardo Lima Mitev <elima@igalia.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-12-23 07:27:13 -08:00
Bruce Cherniak 9e35426731 swr: fix icc compile error
ICC doesn't like the use of nullptr (std::nullptr_t) argument in
p_atomic_set.  GCC and clang don't complain.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99119
Reviewed-by: Tim Rowley <timothy.o.rowley@intel.com>
2016-12-23 08:36:21 -06:00
Dave Airlie e7279f16a0 radv: set some proper values for interp offset limits.
These are taken from the amdgpu-pro driver, and cause no
CTS change.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-23 14:36:54 +10:00
Dave Airlie 14737bcdd5 radv: bump texel offsets to align with radeonsi
it appears from the amdgpu-pro results the hw can do more,
but let's just align with radeonsi for now.

No CTS regressions.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2016-12-23 14:36:50 +10:00
Jason Ekstrand d55835b8bd nir/algebraic: Add optimizations for "a == a && a CMP b"
This sequence shows up The Talos Principal, at least under Vulkan,
and prevents loop analysis from properly computing trip counts in a
few loops.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2016-12-22 16:27:19 -08:00
Jason Ekstrand 8962cc96ec i965: Use nir_opt_trivial_continues and nir_opt_if
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-12-22 16:27:19 -08:00
Jason Ekstrand 6d9f576b56 nir: Add a pass for moving SPIR-V continue blocks to the ends of loops
When shaders come in from SPIR-V, we handle continue blocks by placing
the contents of the continue inside of a "if (!first_iteration)".  We do
this so that we can properly handle the fact that continues in SPIR-V
jump to the continue block at the end of the loop rather than jumping
directly to the top of the loop like they do in NIR.  In particular, the
increment step of a simple for loop ends up in the continue block.  This
pass looks for this case in loops that don't actually have any continues
and moves the continue contents to the end of the loop instead.  We need
this because loop unrolling doesn't work if the increment is inside of a
condition.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-12-22 16:27:19 -08:00
Jason Ekstrand 1111a05f90 nir: Add an optimization pass to remove trivial continues
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-12-22 16:27:19 -08:00
Jason Ekstrand 993e9195d4 nir: Correctly handle blocks in cf_node_cf_tree_next
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-12-22 16:27:19 -08:00
Timothy Arceri 3321eb4c36 i965: make use of nir_lower_returns() for GL
Fixes two new piglit tests:

spec/glsl-1.10/execution/vs-nested-return-sibling-loop.shader_test
spec/glsl-1.10/execution/vs-nested-return-sibling-loop2.shader_test

shader-db results for BDW:

total instructions in shared programs: 12903158 -> 12903134 (-0.00%)
instructions in affected programs: 27100 -> 27076 (-0.09%)
helped: 32
HURT: 6

total cycles in shared programs: 294922518 -> 294922804 (0.00%)
cycles in affected programs: 4372828 -> 4373114 (0.01%)
helped: 31
HURT: 8

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-12-23 10:59:32 +11:00
Timothy Arceri f20ba7ad44 nir: update nir_lower_returns to only predicate instructions when needed
Unless an if statement contains nested returns we can simply add
any following instructions to the branch without the return.

V2: fix handling if_nested_return value when there is a sibling if/loop
that doesn't contain a return. (Spotted by Ken)

V3:
 - add a better comment to the new variable
 - remove instructions after if when both branches return

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:59:32 +11:00
Timothy Arceri 40e9f2f138 i965: disable loop unrolling in GLSL IR
There is a single regression in loop unrolling which is:

loops HURT:   shaders/orbital_explorer.shader_test GS SIMD8:    0 -> 1

However the loop is huge so it seems reasonable not to unroll it. It's
surprising that GLSL IR does unroll it.

shader-db results BDW:

total instructions in shared programs: 13037455 -> 13036947 (-0.00%)
instructions in affected programs: 17982 -> 17474 (-2.83%)
helped: 63
HURT: 25

total cycles in shared programs: 262217870 -> 262227990 (0.00%)
cycles in affected programs: 2287046 -> 2297166 (0.44%)
helped: 969
HURT: 844

total loops in shared programs: 2951 -> 2952 (0.03%)
loops in affected programs: 0 -> 1
helped: 0
HURT: 1

LOST:   0
GAINED: 1

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Timothy Arceri 715f0d06d1 i965: use nir loop unrolling pass
shader-db results for BDW:

total instructions in shared programs: 12589614 -> 12590119 (0.00%)
instructions in affected programs: 50525 -> 51030 (1.00%)
helped: 7
HURT: 145

total cycles in shared programs: 241524604 -> 241490502 (-0.01%)
cycles in affected programs: 1941404 -> 1907302 (-1.76%)
helped: 302
HURT: 449

total loops in shared programs: 4245 -> 2947 (-30.58%)
loops in affected programs: 1535 -> 237 (-84.56%)
helped: 1142
HURT: 0

total spills in shared programs: 14453 -> 14453 (0.00%)
spills in affected programs: 0 -> 0
helped: 0
HURT: 0

total fills in shared programs: 18984 -> 18984 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0

LOST:   26
GAINED: 15

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Timothy Arceri e729504fb1 nir: pass compiler rather than devinfo to functions that call nir_optimize
Later we will pass compiler to nir_optimise to be used by the loop unroll
pass.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Timothy Arceri 51daccb289 nir: add a loop unrolling pass
V2:
- tidy ups suggested by Connor.
- tidy up cloning logic and handle copy propagation
 based of suggestion by Connor.
- use nir_ssa_def_rewrite_uses to fix up lcssa phis
  suggested by Connor.
- add support for complex loop unrolling (two terminators)
- handle case were the ssa defs use outside the loop is already a phi
- support unrolling loops with multiple terminators when trip count
  is know for each terminator

V3:
- set correct num_components when creating phi in complex unroll
- rewrite update remap table based on Jasons suggestions.
- remove unrequired extract_loop_body() helper as suggested by Jason.
- simplify the lcssa phi fix up code for simple loops as per Jasons suggestions.
- use mem context to keep track of hash table memory as suggested by Jason.
- move is_{complex,simple}_loop helpers to the unroll code
- require nir_metadata_block_index
- partially rewrote complex unroll to be simpler and easier to follow.

V4:
- use rzalloc() when creating nir_phi_src but not setting pred right away
 fixes regression cause by ralloc() no longer zeroing memory.

V5:
- simplify calling of complex_unroll()
- use new loop terminator fields to get the break/continue from blocks
  and simplify loop unrolling code
- handle slightly less trivial loop terminators. if branches can
  now have instructions but can only contain a single block.
- use nir print type IR snippets in unroll function descriptions
- add better explanation and variable for why we need to clone
  additional times when the second terminator it the limiting
  terminator.
- partially convert out of ssa before unrolling loops (suggested by Jason)

v6:
- remove unused nir_builder
- use Jasons new from ssa helper
- tidy/fixup cursor use
- unroll terminators that contain control flow correctly
- unroll complex loops with control flow before the terminators
  correctly

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Timothy Arceri f8407a5398 nir: add helper for cloning nir_cf_list
V2:
- updated to create a generic list clone helper nir_cf_list_clone()
- continue to assert on clone when fallback flag not set as suggested
  by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Timothy Arceri b84dfa0f62 nir: update fixup_phi_srcs() to handle registers
We need to do this because we partially get out of SSA when unrolling
and cloning loops.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Timothy Arceri d781320974 nir: create helper for fixing phi srcs when cloning
This will be useful for fixing phi srcs when cloning a loop body
during loop unrolling.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Thomas Helland ec8423a4b1 nir: Add a LCSAA-pass
V2: Do a "depth first search" to convert to LCSSA

V3: Small comment fixup

V4: Rebase, adapt to removal of function overloads

V5: Rebase, adapt to relocation of nir to compiler/nir
    Still need to adapt to potential if-uses
    Work around nir_validate issue

V6 (Timothy):
 - tidy lcssa and stop leaking memory
 - dont rewrite the src for the lcssa phi node
 - validate lcssa phi srcs to avoid postvalidate assert
 - don't add new phi if one already exists
 - more lcssa phi validation fixes
 - Rather than marking ssa defs inside a loop just mark blocks inside
   a loop. This is simpler and fixes lcssa for intrinsics which do
   not have a destination.
 - don't create LCSSA phis for loops we won't unroll
 - require loop metadata for lcssa pass
 - handle case were the ssa defs use outside the loop is already a phi

V7: (Timothy)
- pass indirect mask to metadata call

v8: (Timothy)
- make convert to lcssa a helper function rather than a nir pass
- replace inside loop bitset with on the fly block index logic.
- remove lcssa phi validation special cases
- inline code from useless helpers, suggested by Jason.
- always do lcssa on loops, suggested by Jason.
- stop making lcssa phis special. Add as many source as the block
  has predecessors, suggested by Jason.

V9: (Timothy)
- fix regression with the is_lcssa_phi field not being initialised
  to false now that ralloc() doesn't zero out memory.

V10: (Timothy)
- remove extra braces in SSA example, pointed out by Topi

V11: (Timothy)
- add missing support for LCSSA phis in if conditions.

V12: (Timothy)
- small tidy up suggested by Jason.
- always create lcssa phi even if it just points to an lcssa
  phi from an inner loop

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Thomas Helland 6772a17acc nir: Add a loop analysis pass
This pass detects induction variables and calculates the
trip count of loops to be used for loop unrolling.

V2: Rebase, adapt to removal of function overloads

V3: (Timothy Arceri)
 - don't try to find trip count if loop terminator conditional is a phi
 - fix trip count for do-while loops
 - replace conditional type != alu assert with return
 - disable unrolling of loops with continues
 - multiple fixes to memory allocation, stop leaking and don't destroy
   structs we want to use for unrolling.
 - fix iteration count bugs when induction var not on RHS of condition
 - add FIXME for && conditions
 - calculate trip count for unsigned induction/limit vars

V4: (Timothy Arceri)
- count instructions in a loop
- set the limiting_terminator even if we can't find the trip count for
 all terminators. This is needed for complex unrolling where we handle
 2 terminators and the trip count is unknown for one of them.
- restruct structs so we don't keep information not required after
 analysis and remove dead fields.
- force unrolling in some cases as per the rules in the GLSL IR pass

V5: (Timothy Arceri)
- fix metadata mask value 0x10 vs 0x16

V6: (Timothy Arceri)
- merge loop_variable and nir_loop_variable structs and lists suggested by Jason
- remove induction var hash table and store pointer to induction information in
  the loop_variable suggested by Jason.
- use lowercase list_addtail() suggested by Jason.
- tidy up init_loop_block() as per Jasons suggestions.
- replace switch with nir_op_infos[alu->op].num_inputs == 2 in
  is_var_basic_induction_var() as suggested by Jason.
- use nir_block_last_instr() in and rename foreach_cf_node_ex_loop() as suggested
  by Jason.
- fix else check for is_trivial_loop_terminator() as per Connors suggetions.
- simplify offset for induction valiables incremented before the exit conditions is
  checked.
- replace nir_op_isub check with assert() as it should have been lowered away.

V7: (Timothy Arceri)
- use rzalloc() on nir_loop struct creation. Worked previously because ralloc()
  was broken and always zeroed the struct.
- fix cf_node_find_loop_jumps() to find jumps when loops contain
  nested if statements. Code is tidier as a result.

V8: (Timothy Arceri)
- move is_trivial_loop_terminator() to nir.h so we can use it to assert is
  the loop unroll pass
- fix analysis to not bail when looking for terminator when the break is in the else
  rather then the if
- added new loop terminator fields: break_block, continue_from_block and
  continue_from_then so we don't have to gather these when doing unrolling.
- get correct array length when forcing unrolling of variables
  indexed arrays that are the same size as the iteration count
- add support for induction variables of type float
- update trival loop terminator check to allow an if containing
  instructions as long as both branches contain only a single
  block.

V9: (Timothy)
 - bunch of tidy ups and simplifications suggested by Jason.
 - rewrote trivial terminator detection, now the only restriction is there
   must be no nested jumps, anything else goes.
 - rewrote the iteration test to use nir_eval_const_opcode().
 - count instruction properly even when forcing an unroll.
 - bunch of other tidy ups and simplifications.

V10: (Timothy)
 - some trivial tidy ups suggested by Jason.
 - conditional fix for break inside continue branch by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Timothy Arceri eda3ec7957 i965: use nir_lower_indirect_derefs() for GLSL
This moves the nir_lower_indirect_derefs() call into
brw_preprocess_nir() so thats is called by both OpenGL and Vulkan
and removes that call to the old GLSL IR pass
lower_variable_index_to_cond_assign()

We want to do this pass in nir to be able to move loop unrolling
to nir.

There is a increase of 1-3 instructions in a small number of shaders,
and 2 Kerbal Space program shaders that increase by 32 instructions.
The changes seem to be caused be the difference in the GLSL IR vs
NIR variable index lowering passes. The GLSL IR pass creates a
simple if ladder for arrays of size 4 or less, while the NIR pass
implements a binary search for all arrays regardless of size.

Shader-db results BDW:

total instructions in shared programs: 13021176 -> 13021819 (0.00%)
instructions in affected programs: 57693 -> 58336 (1.11%)
helped: 20
HURT: 190

total cycles in shared programs: 299805580 -> 299750826 (-0.02%)
cycles in affected programs: 2290024 -> 2235270 (-2.39%)
helped: 337
HURT: 442

total fills in shared programs: 19984 -> 19984 (0.00%)
fills in affected programs: 0 -> 0
helped: 0
HURT: 0

LOST:   4
GAINED: 0

V2: remove the do_copy_propagation() call from the i965 GLSL IR
linking code. This call was added in f7741c5211 but since we are
moving the variable index lowering to NIR we no longer need it and
can just rely on the nir copy propagation pass.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:36 +11:00
Timothy Arceri 976859ce57 i965: allow sampler indirects on all gens
Without this we will regress the max-samplers piglit test on Gen6
and lower when loop unrolling is done in NIR. There is a check
in the GLSL IR linker that errors when it finds indirects and
EmitNoIndirectSampler is set.

As far as I can tell there is no reason for not enabling this for
all gens regardless of whether they fully support ARB_gpu_shader5
or not.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-12-23 10:15:35 +11:00
Jason Ekstrand a620f66872 nir: Add a couple quick-and-dirty out-of-SSA helpers
These are designed for use within an optimization pass when SSA becomes
more pain than it's worth.  They're very naive and don't generate
anything close to optimal register-based NIR.  Also, they may result in
shaders which do not validate because of, for instance, registers in phi
sources.  However, the register-based into-SSA pass should be pretty
efficient at cleaning up the mess.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-12-23 10:15:35 +11:00
Arda Coskunses 99de7b7525 vulkan/wsi/x11: don't crash on null wsi x11 connection
Without this check driver crash when application window
closed unexpectedly.

Acked-by: Edward O'Callaghan <funfunctor@folklore194.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-12-22 14:09:46 -08:00
Arda Coskunses 01dd363e67 vulkan/wsi/x11: don't crash on null visual
When application window closed unexpectedly due to
lost window visualtypes getting invlaid parameters
which is causing a crash. Necessary check is added
to prevent the crash.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2016-12-22 14:09:34 -08:00