4fb0c92c69
i965: Add support for EXT_texture_swizzle to the new FS backend.
2010-10-02 23:44:44 -07:00
8f7177e0de
r300g: add support for L8A8 colorbuffers
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Blending with DST_ALPHA is undefined. SRC_ALPHA works, though.
I bet some other formats have similar limitations too.
2010-10-02 23:19:38 +02:00
e75bce026c
r300g: add support for R8G8 colorbuffers
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The hw swizzles have been obtained by a brute force approach,
and only C0 and C2 are stored in UV88, the other channels are
ignored.
R16G16 is going to be a lot trickier.
2010-10-02 21:42:22 +02:00
71a079fb4e
mesa/st: initial attempt at RG support for gallium drivers
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passes all piglit RG tests with softpipe.
2010-10-02 17:03:15 +10:00
f317713432
i965: Fix incorrect batchbuffer size in gen6 clip state command.
...
FORCE_ZERO_RTAINDEX should be in the fourth (and final) dword.
2010-10-01 21:53:28 -07:00
64a9fc3fc1
i965: Don't try to emit code if we failed register allocation.
2010-10-01 17:19:04 -07:00
6397addd61
i965: Fix off-by-ones in handling the last members of register classes.
...
Luckily, one of them would result in failing out register allocation
when the other bugs were encountered. Applies to
glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined, which still
fails register allocation, but now legitimately.
2010-10-01 17:19:04 -07:00
afb64311e3
i965: Add a sanity check for register allocation sizes.
2010-10-01 17:19:03 -07:00
5ee0941316
i965: When producing a single channel swizzle, don't make a temporary.
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This quickly cuts 8% of the instructions in my glsl demo.
2010-10-01 17:19:03 -07:00
a0799725f5
i965: Restore the forcing of aligned pairs for delta_xy on chips with PLN.
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By doing so using the register allocator now, we avoid wasting a
register to make the alignment happen.
2010-10-01 17:19:03 -07:00
fb0eed84ca
r600c: fix segfault in evergreen stencil code
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Fixes:
https://bugs.freedesktop.org/show_bug.cgi?id=30551
2010-10-01 20:14:25 -04:00
7af2a22d1f
r600g: Remove unnecessary headers.
2010-10-01 17:06:33 -07:00
20846a8ce1
r600g: Remove unused variable.
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Fixes this GCC warning.
r600_shader.c: In function 'tgsi_split_literal_constant':
r600_shader.c:818: warning: unused variable 'index'
2010-10-01 17:02:01 -07:00
1ca6cbec1b
rgtc: Detect RGTC formats as color formats and as compressed formats
2010-10-01 16:55:35 -07:00
5ebbabc5cc
mesa: Trivial correction to comment
2010-10-01 16:55:35 -07:00
69c78bf2c2
mesa: Fix misplaced #endif
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If FEATURE_texture_s3tc is not defined, FXT1 formats would erroneously
fall through to the MESA_FORMAT_RGBA_FLOAT32 case.
2010-10-01 16:55:35 -07:00
7c6147014a
ARB_texture_rg: Add GL_COMPRESSED_{RED,RG} cases in _mesa_is_color_format
2010-10-01 16:55:35 -07:00
e2a054b70c
mesa: Add ARB_texture_compression_rgtc as an alias for EXT_texture_compression_rgtc
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Change the name in the extension tracking structure to ARB (from EXT).
2010-10-01 16:55:35 -07:00
e5fd15199d
savage: Remove unnecessary header.
2010-10-01 16:57:19 -07:00
841503fddf
glsl: Remove unnecessary header.
2010-10-01 16:27:58 -07:00
c77cd9ec10
i965: Enable GL_ARB_texture_rg
2010-10-01 15:49:13 -07:00
9ef390dc14
mesa: Enable GL_ARB_texture_rg in software paths
2010-10-01 15:49:13 -07:00
421f4d8dc1
ARB_texture_rg: Allow RED and RG textures as FBO color buffer attachments
2010-10-01 15:49:13 -07:00
5d1387b2da
ARB_texture_rg: Add R8, R16, RG88, and RG1616 internal formats
2010-10-01 15:49:13 -07:00
214a33f610
ARB_texture_rg: Handle RED and RG the same as RGB for tex env
2010-10-01 15:49:13 -07:00
cd5dea6401
ARB_texture_rg: Add GL_RED as a valid GL_DEPTH_TEXTURE_MODE
2010-10-01 15:49:13 -07:00
cc6f13def5
ARB_texture_rg: Add GL_TEXTURE_{RED,GREEN}_SIZE query support
2010-10-01 15:49:12 -07:00
3ebbc176f9
ARB_texture_rg: Correct some errors in RED / RG internal format handling
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Fixes several problems:
The half-float, float, and integer internal formats depend on
ARB_texture_rg and other extensions.
RG_INTEGER is not a valid internal format.
Generic compressed formats depend on ARB_texture_rg, not
EXT_texture_compression_rgtc.
Use GL_RED instead of GL_R.
2010-10-01 15:49:12 -07:00
bb45ab0a96
ARB_texture_rg: Add GLX protocol support
2010-10-01 15:49:12 -07:00
96efa8a923
i965g: use Elements macro instead of manual sizeofs
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Signed-off-by: Nicolas Kaiser <nikai@nikai.net>
Signed-off-by: Brian Paul <brianp@vmware.com>
2010-10-01 16:41:13 -06:00
e9bcc83289
i965: Fix up copy'n'pasteo from moving coordinate setup around for gen4.
2010-10-01 14:09:00 -07:00
bfd9715c3c
i965: Add real support for pre-gen5 texture sampling to the new FS.
...
Fixes 36 testcases, including glsl-fs-shadow2d*-bias which fail on the
Mesa IR backend.
2010-10-01 14:02:48 -07:00
92eb07a281
evergreen : fix z format setting, enable stencil.
2010-10-01 16:10:02 -04:00
8f63a44636
i965: Pre-gen6, map VS outputs (not FS inputs) to URB setup in the new FS.
...
We should fix the SF to actually give us just the data we need, but
this fixes regressions in the new FS until then.
Fixes:
glsl-kwin-blur
glsl-routing
2010-10-01 12:21:51 -07:00
ff5ce9289b
i965: Also increment attribute location when skipping unused slots.
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Fixes glsl1-texcoord varying.
2010-10-01 12:19:21 -07:00
354c40a624
i965: Fix the gen6 jump size for BREAK/CONT in new FS.
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Since gen5, jumps are in increments of 64 bits instead of increments
of 128-bit instructions.
2010-10-01 12:19:21 -07:00
efc4a6f790
i965: Add gen6 attribute interpolation to new FS backend.
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Untested, since my hardware is not booting at the moment.
2010-10-01 12:19:21 -07:00
29b491bd03
r600g: indentation fixes
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Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2010-10-01 10:26:58 -04:00
738aa29289
r600g: setup basic loop consts on r600 + evergreen.
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this sets up a single loop constant like r600c does.
2010-10-01 16:06:31 +10:00
7777c997e0
r600g: only set the Z export if shader exports it.
2010-10-01 16:06:30 +10:00
0c39a53aa6
r600c: pull over 6xx/7xx vertex fixes for evergreen
2010-10-01 00:51:37 -04:00
539a2978ed
r600g: flush SH cache on constant change on evergreen
2010-10-01 14:43:02 +10:00
b67aa5311f
r600g: fix evergreen draw-buffers
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just a typo in the register headers.
2010-10-01 14:24:14 +10:00
14c95bb4ee
r600g: add cb flushing for extra buffers + depth buffer on r600/evergreen
2010-10-01 14:05:02 +10:00
ac225c76a6
r600g: sync vertex/texture cache on resources on evergreen
...
this gets rid of lots of the instability on evergreen,
which isn't surprising since it really broken not to flush caches.
2010-10-01 14:04:32 +10:00
d662195f00
r600g: fixup vertex format picking.
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there are some vertex formats defined in r600c not in the docs.
2010-10-01 13:36:56 +10:00
e973221538
r600g: add assembler support for other vtx fetch fields.
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this shouldn't change behaviour, just push the choice of what
to do out to the shader.
2010-10-01 13:36:56 +10:00
1d073cb2d9
i965: Split the gen4 and gen5 sampler handling apart.
...
Trying to track the insanity of the different argument layouts for
normal/shadow crossed with normal/lod/bias one generation at a time is
enough.
Fixes: glsl1-texture2D() with bias.
(first test passing in this code that doesn't pass without it!)
2010-09-30 20:23:40 -07:00
5f237a1ccb
i965: Use the lowering pass for texture projection.
...
We should end up with the same code, but anyone else with this issue
could share the handling (which I got wrong for shadow comparisons in
the driver before).
2010-09-30 20:23:40 -07:00
aae338104f
glsl: Add a lowering pass for texture projection.
2010-09-30 20:23:36 -07:00
Eric Anholt
Marek Olšák
Dave Airlie
Kenneth Graunke
Alex Deucher
Vinson Lee
Ian Romanick
Nicolas Kaiser
richard
Jerome Glisse