r600g: add cb flushing for extra buffers + depth buffer on r600/evergreen
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ac225c76a6
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14c95bb4ee
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@ -1865,9 +1865,18 @@
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#define S_0085F0_DB_DEST_BASE_ENA(x) (((x) & 0x1) << 14)
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#define G_0085F0_DB_DEST_BASE_ENA(x) (((x) >> 14) & 0x1)
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#define C_0085F0_DB_DEST_BASE_ENA 0xFFFFBFFF
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#define S_0085F0_CR_DEST_BASE_ENA(x) (((x) & 0x1) << 15)
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#define G_0085F0_CR_DEST_BASE_ENA(x) (((x) >> 15) & 0x1)
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#define C_0085F0_CR_DEST_BASE_ENA 0xFFFF7FFF
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#define S_0085F0_CB8_DEST_BASE_ENA(x) (((x) & 0x1) << 15)
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#define G_0085F0_CB8_DEST_BASE_ENA(x) (((x) >> 15) & 0x1)
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#define S_0085F0_CB9_DEST_BASE_ENA(x) (((x) & 0x1) << 16)
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#define G_0085F0_CB9_DEST_BASE_ENA(x) (((x) >> 16) & 0x1)
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#define S_0085F0_CB10_DEST_BASE_ENA(x) (((x) & 0x1) << 17)
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#define G_0085F0_CB10_DEST_BASE_ENA(x) (((x) >> 17) & 0x1)
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#define S_0085F0_CB11_DEST_BASE_ENA(x) (((x) & 0x1) << 18)
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#define G_0085F0_CB11_DEST_BASE_ENA(x) (((x) >> 18) & 0x1)
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#define S_0085F0_TC_ACTION_ENA(x) (((x) & 0x1) << 23)
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#define G_0085F0_TC_ACTION_ENA(x) (((x) >> 23) & 0x1)
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#define C_0085F0_TC_ACTION_ENA 0xFF7FFFFF
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@ -727,6 +727,7 @@ void evergreen_context_pipe_state_set_vs_sampler(struct r600_context *ctx, struc
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void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
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{
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struct radeon_bo *cb[12];
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struct radeon_bo *db;
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unsigned ndwords = 9;
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if (draw->indices) {
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@ -738,6 +739,7 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
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}
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/* find number of color buffer */
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db = r600_context_reg_bo(ctx, R_028048_DB_Z_READ_BASE);
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cb[0] = r600_context_reg_bo(ctx, R_028C60_CB_COLOR0_BASE);
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cb[1] = r600_context_reg_bo(ctx, R_028C9C_CB_COLOR1_BASE);
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cb[2] = r600_context_reg_bo(ctx, R_028CD8_CB_COLOR2_BASE);
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@ -755,6 +757,8 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
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ndwords += 7;
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}
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}
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if (db)
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ndwords += 7;
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/* queries need some special values */
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if (ctx->num_query_running) {
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@ -808,11 +812,15 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
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ctx->pm4[ctx->pm4_cdwords++] = EVENT_TYPE_CACHE_FLUSH_AND_INV_EVENT;
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/* flush color buffer */
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for (int i = 0; i < 8; i++) {
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for (int i = 0; i < 12; i++) {
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if (cb[i]) {
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ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
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ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
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S_0085F0_CB_ACTION_ENA(1);
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if (i > 7)
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ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB8_DEST_BASE_ENA(1) << (i - 8)) |
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S_0085F0_CB_ACTION_ENA(1);
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else
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ctx->pm4[ctx->pm4_cdwords++] = (S_0085F0_CB0_DEST_BASE_ENA(1) << i) |
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S_0085F0_CB_ACTION_ENA(1);
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ctx->pm4[ctx->pm4_cdwords++] = (cb[i]->size + 255) >> 8;
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ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
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ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
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@ -821,6 +829,17 @@ void evergreen_context_draw(struct r600_context *ctx, const struct r600_draw *dr
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r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]);
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}
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}
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if (db) {
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ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
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ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_DB_DEST_BASE_ENA(1) |
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S_0085F0_DB_ACTION_ENA(1);
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ctx->pm4[ctx->pm4_cdwords++] = (db->size + 255) >> 8;
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ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
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ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
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ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
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ctx->pm4[ctx->pm4_cdwords++] = 0;
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r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], db);
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}
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/* all dirty state have been scheduled in current cs */
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ctx->pm4_dirty_cdwords = 0;
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@ -878,6 +878,7 @@ struct radeon_bo *r600_context_reg_bo(struct r600_context *ctx, unsigned offset)
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void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
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{
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struct radeon_bo *cb[8];
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struct radeon_bo *db;
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unsigned ndwords = 9;
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if (draw->indices) {
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@ -889,6 +890,7 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
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}
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/* find number of color buffer */
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db = r600_context_reg_bo(ctx, R_02800C_DB_DEPTH_BASE);
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cb[0] = r600_context_reg_bo(ctx, R_028040_CB_COLOR0_BASE);
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cb[1] = r600_context_reg_bo(ctx, R_028044_CB_COLOR1_BASE);
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cb[2] = r600_context_reg_bo(ctx, R_028048_CB_COLOR2_BASE);
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@ -902,6 +904,8 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
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ndwords += 7;
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}
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}
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if (db)
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ndwords += 7;
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/* queries need some special values */
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if (ctx->num_query_running) {
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@ -970,6 +974,17 @@ void r600_context_draw(struct r600_context *ctx, const struct r600_draw *draw)
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r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], cb[i]);
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}
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}
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if (db) {
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ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_SURFACE_SYNC, 3);
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ctx->pm4[ctx->pm4_cdwords++] = S_0085F0_DB_DEST_BASE_ENA(1) |
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S_0085F0_DB_ACTION_ENA(1);
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ctx->pm4[ctx->pm4_cdwords++] = (db->size + 255) >> 8;
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ctx->pm4[ctx->pm4_cdwords++] = 0x00000000;
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ctx->pm4[ctx->pm4_cdwords++] = 0x0000000A;
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ctx->pm4[ctx->pm4_cdwords++] = PKT3(PKT3_NOP, 0);
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ctx->pm4[ctx->pm4_cdwords++] = 0;
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r600_context_bo_reloc(ctx, &ctx->pm4[ctx->pm4_cdwords - 1], db);
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}
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/* all dirty state have been scheduled in current cs */
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ctx->pm4_dirty_cdwords = 0;
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