Commit Graph

137662 Commits

Author SHA1 Message Date
Marek Olšák 0580d4c1a2 radeonsi: enable HTILE with mipmapping on gfx9+
Everything seems to be there except fast clears.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 4e35eb1d69 radeonsi: set better default depth clear value
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 3345e32de7 radeonsi: group and parallelize all clears in si_texture_create_object
This reduces aux_context flushes significantly.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák cb6e1c7c11 radeonsi: add num_layers variable into si_do_fast_color_clear
in preparation for the next commit

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 1936a046b1 radeonsi: return success/failure from si_alloc_separate_cmask
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 8cd61d1248 radeonsi: parallelize CMASK and DCC clears
Clearing 8 RTs with both DCC and CMASK caused 16 synchronized clears where
we also did 16 times WAIT_REG_MEM for CB flushes that were 15 times
useless.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák d0f06e5c47 radeonsi: remove si_screen::dcc_msaa_allowed
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 4707dc6a64 radeonsi: determine accurately whether the framebuffer state has DCC MSAA
We only need to check storage samples, which is what affects DCC.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 933df67296 ac/surface: add CMASK info for level 0
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák b3e7c77f13 amd: fix parsing the last dword of DMA_DATA packets
It was parsing it as SQ_WAVE_GPR_ALLOC instead of COMMAND.
Change the offset to an odd number to work around it.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 95940459be radeonsi: pack the variable block size in one SGPR, 10 bits per component
The side effect of this is that the compute copy image shader now has
enough free user SGPRs that it passes the src image via user SGPRs,
resulting in lower wave lifetime.

Previous copy shader:
    s_load_dwordx8
    image_load
    s_load_dwordx8
    s_waitcnt
    image_store

Current copy shader:
    image_load
    s_load_dwordx8
    s_waitcnt
    image_store

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 034c1e4845 radeonsi: decrease the maximum variable block size
to allow packing the block size in 1 user SGPR with 10 bits per component,
so that block sizes such as 512x1x1 fit in there.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák ad71ef9326 radeonsi: don't use a constant buffer for the copy_image compute shader
just use user SGPRs and 16-bit values for the x,y,z coordinates.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 5701baa34b radeonsi: don't use constbuf and set cache policy for 12-byte clear shader
This removes the constant buffer and sets the cache policy like other
compute shaders.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 7d14eb623b radeonsi: return false from si_is_format_supported instead of NULL
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák c53261645d radeonsi: add SI_CONTEXT_PFP_SYNC_ME to skip syncing PFP for image operations
DCC/CMASK/HTILE clears will not set this. We could do a better job
at not setting this in other cases too

Image copies also don't set this.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 4fb1b7b2d8 radeonsi: use the optimal packet order before draw packets for VS flushes too
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák b1a73ec99b radeonsi: rename and apply SI_OP_CPDMA_SKIP_CACHE_FLUSH to compute as well
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 419e05d5f6 radeonsi: don't do an L2 flush in compute_do_clear_or_copy if we're not syncing
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák aed881e34e radeonsi: reduce syncing in si_compute_expand_fmask when it's already idle
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 5c827bde29 radeonsi: reduce syncing for initializing new buffers
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 207bafd4dd radeonsi: reduce syncing in si_dcc_decompress
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 7e2b5ce722 radeonsi: set compute/cpdma sync flags in the outermost caller
This allows us to control syncing everywhere.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák a4ad08b455 radeonsi: inline clear_buffer in si_screen_clear_buffer
We'll add a new parameter there.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 1af99a28a0 radeonsi: merge CP DMA flags with internal compute flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák dd5e9af78f radeonsi: remove unused SI_CP_DMA_SKIP_* definitions
The existing uses had no effect.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 938dc0e291 radeonsi: rename internal compute sync flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 69ff9c16bb radeonsi: never set DISABLE_WR_CONFIRM for CP DMA clears and copies
Only prefetches set it. Unsynchronized clears and copies shouldn't set it
because syncing later wouldn't wait for the writes.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 28d065d3e5 radeonsi: don't insert start/stop pipeline stat events if it has no effect
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák cb59cae04c radeonsi: set the clear/copy cache policy based on L2 cache size
This matches the intent.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák 8ea685dfc0 radeonsi: disable sparse buffers on gfx7-8
Cc: 20.3 21.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Marek Olšák ac78b12e23 ac/llvm: don't set unsupported xnack options to fix LLVM crashes on gfx6-8
LLVM prints an error if xnack is unsupported and it uses a global stream
object that is not thread-safe. Since Mesa uses multiple threads to compile
shaders, there is a small chance that it will crash.

Just don't set any xnack options to use LLVM defaults.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4439

Cc: 20.3 21.0 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
2021-04-02 12:05:00 +00:00
Samuel Pitoiset 57916fbdcd radv: use COLOR_ATTACHMENT_OPTIMAL for fast clear/hw resolve operations
This should be equivalent without needed to force enable FMASK for
some specific internal pipelines.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9940>
2021-04-02 08:36:19 +02:00
Samuel Pitoiset fc2186d302 radv: do not force enable FMASK during MSAA blits
This is no longer needed since FMASK is also compressed for
transfer dst operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9940>
2021-04-02 08:36:16 +02:00
Samuel Pitoiset 6dbf975cb9 radv: cleanup FMASK expand transitions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9990>
2021-04-02 06:34:45 +00:00
Samuel Pitoiset 87c8764448 radv: compress FMASK for all layouts except GENERAL
The COMPRESSION bit is FMASK and this is much faster! Should
speedup transfer dst operations with MSAA images considerably.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9990>
2021-04-02 06:34:45 +00:00
Eric Anholt adf04d1af4 ci/freedreno: Switch to the trimmed glxgears trace.
The old one had a ton of frames and took ~5 minutes on a306.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9957>
2021-04-01 21:04:11 +00:00
Eric Anholt fe5349f70c freedreno/a6xx: Fix alpha tests.
Apparently I inverted the sense of this flag back when we didn't have
piglit testing.  Fixes terrible rendering in minetest, HL2, CS:Source, and
CS.

Fixes: 0369dd9077 ("freedreno/a6xx: Add ARB_depth_clamp and separate clamp support.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9957>
2021-04-01 21:04:11 +00:00
Eric Anholt 3043940183 freedreno/a5xx: Fix alpha test vs early Z bugs.
Just like with discards, we have to disable early Z writes when alpha test
is enabled.

Fixes rendering on HL2, CS: Source, counter-strike, and minetest.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9957>
2021-04-01 21:04:11 +00:00
Eric Anholt c9fd8c2570 ci/freedreno: Add trace testing on a3xx, a5xx.
Having compared rendering between a6xx and these, I found several bugs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9957>
2021-04-01 21:04:11 +00:00
Eric Anholt 8e3a1d0dd2 ci/freedreno: Rename a306-test and a530-test to drop "arm64" from the name.
We don't have an armhf variant, and probably won't.  Now matches a630.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9957>
2021-04-01 21:04:11 +00:00
Eric Anholt ec54546b2a ci/freedreno: Add more new traces for a630 (minetest, TDM, pioneer, glyphy).
These are all recent traces that have been added.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9957>
2021-04-01 21:04:11 +00:00
Mike Blumenkrantz 3d55998504 zink: emit ImageCubeArray cap when accessing arrayed cube dimension images
required by spec

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9987>
2021-04-01 20:05:06 +00:00
Mike Blumenkrantz ccbaf31f3c zink: use max_rt to determine number of blend state attachments
this is more consistent with how gallium applies the states

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9988>
2021-04-01 19:55:00 +00:00
Erik Faye-Lund 7dc1b57abb bin/gen_release_notes.py: more robust rST escaping
This copies code from the xml2rst to escape rST strings. Hopefully this
will be more robust than what we've done so far.

I really wish docutils would have utils for this directly, seems kinda
essential.

Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9917>
2021-04-01 19:53:03 +00:00
Erik Faye-Lund 997c94eb33 ci: turn sphinx-build warnings into errors
This should make it harder to accidentally introduce formatting issues
into the docs.

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9914>
2021-04-01 19:36:05 +00:00
Erik Faye-Lund ecc677a02f docs: fix release notes for 20.3.5
This is incorrect escaping of the RST.

Fixes: 930d2a92a3 ("docs: add release notes for 20.3.5")
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9914>
2021-04-01 19:36:05 +00:00
Pierre-Eric Pelloux-Prayer d0fefddf4a vbo/dlist: use DrawGallium(Complex)
We can build the needed structs during list compilation and then
use DrawGallium (if one draw or a single primitive mode is used) or DrawGalliumComplex
otherwise.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9533>
2021-04-01 19:16:39 +00:00
Pierre-Eric Pelloux-Prayer 43e243762f mesa: make _mesa_HashTable InDeleteAll debug only
It's only used in asserts so we can wrap it inside

This makes the struct 32 bytes instead of 40 in release
builds.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9533>
2021-04-01 19:16:39 +00:00
Pierre-Eric Pelloux-Prayer e26f261c7e mesa/hash: switch to simple_mtx
simple_mtx are faster and smaller (4 bytes instead of 8) so switch to using them.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9533>
2021-04-01 19:16:39 +00:00