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radeonsi: set the clear/copy cache policy based on L2 cache size 

This matches the intent.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9795>
This commit is contained in:
Marek Olšák 2021-03-19 17:41:59 -04:00 committed by Marge Bot
parent 8ea685dfc0
commit cb59cae04c
1 changed files with 1 additions and 1 deletions
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2
src/gallium/drivers/radeonsi/si_compute_blit.c
View File

@ -37,7 +37,7 @@ static enum si_cache_policy get_cache_policy(struct si_context *sctx, enum si_co
coher == SI_COHERENCY_DB_META ||
coher == SI_COHERENCY_CP)) ||
(sctx->chip_class >= GFX7 && coher == SI_COHERENCY_SHADER))
return size <= 256 * 1024 ? L2_LRU : L2_STREAM;
return size <= sctx->screen->info.l2_cache_size / 8 ? L2_LRU : L2_STREAM;
return L2_BYPASS;
}